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Circuit I La

The document contains diagrams and equations describing the electrical characteristics and models of diodes, BJTs, and MOSFETs. It shows the I-V characteristics and relationships for diodes in both forward and reverse bias, as well as Zener diodes. It also shows the common emitter configuration and characteristics of NPN and PNP BJTs, including the early effect. Finally, it outlines the regions of operation and equations for NMOS and PMOS transistors.

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Hermann Vallieri
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0% found this document useful (0 votes)
78 views6 pages

Circuit I La

The document contains diagrams and equations describing the electrical characteristics and models of diodes, BJTs, and MOSFETs. It shows the I-V characteristics and relationships for diodes in both forward and reverse bias, as well as Zener diodes. It also shows the common emitter configuration and characteristics of NPN and PNP BJTs, including the early effect. Finally, it outlines the regions of operation and equations for NMOS and PMOS transistors.

Uploaded by

Hermann Vallieri
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DIODO

vD

iD

DIODO OFF DIODO ON

Modello a iD = 0 iD > 0 iD
Soglia v D < Vγ v D = Vγ

Vγ vD

Modello iD ≅ − I S ⎛ vD



iD
Esponenziale i D = I S ⎜ e VT − 1⎟
⎜ ⎟
⎝ ⎠

vD IS
0.0
iD ≅ I S ⋅ e VT
0.0 vD

DIODO ZENER
vD

iD

DIODO DIODO OFF DIODO ON


in ZENER
Modello a i D < 0 iD = 0 iD > 0 iD
Soglia v D = −VZ − VZ < v D < Vγ v D = Vγ
-VZ
Vγ vD
BJT NPN
Collettore (C)
vBC iC

iB
Base (B) i E = iC + i B
vCE
vCE = v BE − v BC
iE
vBE

Emettitore (E)

R. INT. (OFF) R. N. (ON) R. SAT

v BE < 0, v BC < 0 v BE > 0, v BC < 0, vCE > VCEsat iC < β F ⋅ i B


Modello
iC = i B = i E = 0 ⎛ vBE ⎞ v BE > 0, v BC > 0
a2 ⎜ VT ⎟
iC = I S ⎜ e − 1⎟ vCE = VCEsat
⎜ ⎟
parametri ⎝ ⎠
iC = β F ⋅ i B , i E ≅ iC
(IS , βF)

Modello v BE < 0, v BC < 0 v BE > 0, v BC < 0, vCE > VCEsat iC < β F ⋅ i B


iC = i B = i E = 0 ⎛ v ⎞ v BE > 0, v BC > 0
a3 I S = I S 0 ⎜⎜1 + CB ⎟⎟
⎝ VA ⎠ vCE = VCEsat
parametri ⎛ v ⎞
β F = β F 0 ⎜⎜1 + CB ⎟⎟
(IS0 , βF0 , VA) ⎝ VA ⎠
⎛ vBE ⎞
⎜ ⎟
iC = I S ⎜ e VT − 1⎟
⎜ ⎟
⎝ ⎠
iC = β F ⋅ i B ed i E ≅ iC

Modello a v BE < Vγ , v BC < V γ' v BE = Vγ , v BC < V γ' , vCE > VCEsat iC < β F ⋅ i B

iC = i B = i E = 0 iC = β F ⋅ i B > 0, i E ≅ iC v BE = Vγ , v BC = V γ'
soglia
vCE = VCEsat
BJT PNP
Emettitore (E)

vEB iE

iB
Base (B) i E = iC + i B
vEC
v EC = v EB − vCB
vCB iC

Collettore (C)

R. INT. (OFF) R. N. (ON) R. SAT

v EB < 0, vCB < 0 v EB > 0, vCB < 0, v EC > V ECsat iC < β F ⋅ i B


Modello
iC = i B = i E = 0 ⎛ vEB ⎞ v EB > 0, vCB > 0
a2 ⎜ VT ⎟
iC = I S ⎜ e − 1⎟ v EC = V ECsat
⎜ ⎟
parametri ⎝ ⎠
iC = β F ⋅ i B , i E ≅ iC
(IS , βF)

Modello v EB < 0, vCB < 0 v EB > 0, vCB < 0, v EC > VECsat iC < β F ⋅ i B
iC = i B = i E = 0 ⎛ v ⎞ v EB > 0, vCB > 0
a3 I S = I S 0 ⎜⎜1 + BC ⎟⎟
⎝ VA ⎠ v EC = V ECsat
parametri ⎛ v ⎞
β F = β F 0 ⎜⎜1 + BC ⎟⎟
(IS0 , βF0 , VA) ⎝ VA ⎠
⎛ vEB ⎞
⎜ ⎟
iC = I S ⎜ e VT − 1⎟
⎜ ⎟
⎝ ⎠
iC = β F ⋅ i B ed i E ≅ iC

Modello a v EB < Vγ , vCB < V γ' v EB = Vγ , vCB < V γ' , v EC > V ECsat iC < β F ⋅ i B

iC = i B = i E = 0 iC = β F ⋅ i B > 0, i E ≅ iC v EB = Vγ , vCB = V γ'


soglia
v EC = VECsat
NMOS: modello regionale
Drain lineare
vGS = vDS +VTn
vGD iD
iD iG = 0
iG iD = iS saturazione
Gate vDS
vDS = vGS – vGD
vGS
iS kn = k’nW/L
vGS interdizione
(W/L: fattore di forma)
vGS ≤ VTn
Source
vDS
INTERDIZIONE LINEARE SATURAZIONE
(OFF) o TRIODO (ON) o PINCH OFF
v GS < VTn v GS > VTn , v GD > VTn ⇔ 0 < v DS < v GS − VTn v GS > VTn , v GD < VTn ⇔
iD = 0 ⎡ ⎤ v DS > v GS − VTn > 0
i D = k n ⎢ (v GS − VTn ) ⋅ v DS − v DS 2 ⎥
1
⎣ ⎦
k n (v GS − VTn )2
2 1
iD =
(se v DS << (v GS − VTn ) 2
⇒ i D ≅ k n (v GS − VTn ) ⋅ v DS

PMOS: modello regionale


Source lineare
vSG = vSD +|VTp|
vSG iD
iS iG = 0
iG iD = iS saturazione
Gate vSD vSD = vSG – vDG
vSG
kp = k’pW/L
vDG iD interdizione
(W/L: fattore di forma)
vSG ≤ |VTp|
Drain vSD

INTERDIZIONE LINEARE SATURAZIONE


(OFF) o TRIODO (ON) o PINCH OFF

v SG < VTp v SG > VTp , v DG > VTp ⇔ 0 < v SD < v SG − VTp v SG > VTp , v DG < VTp ⇔
iD = 0 ⎡
( 1
) ⎤
i D = k p ⎢ v SG − VTp ⋅ v SD − v SD 2 ⎥
v SD > v SG − VTp > 0

(
(se v SD << v SG − VTp
2 ⎦
) iD =
1
2
(
k p v SG − VTp ) 2

⇒ iD ≅ k p (v SG − VTp )⋅ v SD
BJT NPN: stadi amplificatori elementari
configurazione EMETTITORE COLLETTORE BASE
COMUNE COMUNE COMUNE
caratteristiche (EC) (CC) (BC)
Schema +VCC +VCC +VCC
RC
RC Q1
Q1
VIN VIN VOUT
Q1 VOUT VOUT
VIN RE

Amplificazione in Si Si No
Corrente (Iout / Iin ≈ 1+βF) (Iout / Iin ≈ 1)

Amplificazione in Si No Si
Tensione (Invertente) (Vout / Vin ≈ 1) (NON Invertente)

BJT PNP: stadi amplificatori elementari


configurazione EMETTITORE COLLETTORE BASE
COMUNE COMUNE COMUNE
caratteristiche (EC) (CC) (BC)
Schema -VCC -VCC -VCC

RC Q1 RC
VIN Q1
VOUT VIN VOUT
Q1 RE VOUT
VIN

Amplificazione in Si Si No
Corrente (Iout / Iin ≈ 1+βF) (Iout / Iin ≈ 1)
Amplificazione in Si No Si
Tensione (Invertente) (Vout / Vin ≈ 1) (NON Invertente)
OPAMP: configurazioni elementari

Modello a “soglia” o PWL:


vID = 0 V -VUM < vu < +VUM
vu = -VUM vID < 0 V
vu = +VUM vID > 0 V

BUFFER RILEVATORE DI ZERO (COMPARATORE)

NON INVERTENTE INVERTENTE

CONVERTITORE I/V SOMMATORE INVERTENTE

SOMMATORE NON INVERTENTE SOTTRATTORE

INTEGRATORE IDEALE DERIVATORE IDEALE

AMP. LOGARITMICO AMP. ESPONENZIALE


VD R
ID VD
⎛ V ⎞ ⎛ VVi ⎞
R
Vu = −VT ln⎜⎜ i + 1⎟⎟ ⎜ ⎟
Vu RIs ⎜e T −1⎟
= −
- ⎝ s ⎠
RI - ⎜ ⎟
Vi Vi ID ⎝ ⎠
Vu Vu
+ +

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