4446 Design of Microprocessor-Based Systems
Hardware Detail of Intel 8088
Dr. Esam Al_Qaralleh
CE Department
Princess Sumaya University for Technology
4-1
8088 Pin Configuration
GND 1 40 VCC
A14 2 39 A15
A13 3 38 A16 / S3
A12 4 37 A17 / S4
A11 5 36 A18 / S5
A10 6 35 A19 / S6
A9 7 34 SS0 (High)
A8 8 33 MN / MX
AD7 9 32 RD
AD6 10 31 HOLD (RQ / GT0)
AD5 11 30 HLDA (RQ / GT1)
AD4 12 29 WR (LOCK)
AD3 13 28 IO / M (S2)
AD2 14 27 DT / R (S1)
AD1 15 26 DEN (S0)
AD0 16 25 ALE (QS0)
NMI 17 24 INTA (QS1)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
4-2
10.3 CPU pin descriptions
Minmode operation
Time-
signals (MN/MX=1)
0V=“0”, GND 1 40 Vcc multiplexed
5V±10% Address
reference A14 A15
for all A13 A16/S3 Bus /Status
voltages A12 A17/S4 Maxmode operation signals
A11 A18/S5 signals (MN/MX=0) (outputs)
Address Bus A10 A19/S6
(outputs) A9 SS0 (HIGH) Control Operation Mode,
A8 MN/MX Bus (input):
Time-multiplexed AD7 RD (in,out) 1 = minmode
Address (outputs)/ AD6 8088 HOLD (RQ/GT0)
(8088 generates all
Data Bus AD5 HLDA (RQ/GT1)
the needed control
(bidirectional) AD4 WR (LOCK)
signals for a small
AD3 IO/M (S2) Status system),
Hardware AD2 DT/R (S1) signals
interrupt requests AD1 DEN (S0) (outputs) 0 = maxmode
(inputs) AD0 ALE (QS0)
(8288 Bus
NMI INTA (QS1)
Controller expands
2...5MHz, INTR TEST Interrupt the status signals
1/3 duty cycle CLK READY acknowledge to generate more
(input) GND 20 21 RESET (output) control signals)
8088 Pin Description
Pin Name Pin Number Direction Description
GND: 1 & 20 Both need to be connected to ground
VCC: 21 VCC = 5V
CLK: 19 Input 33% duty cycle
2/3*T1/3*T
MN/MX: 33 Input High Minimum mode
Low Maximum mode
RESET: 21 Input Reset 8088
Duration of logic high must be greater
than 4*T
After reset, 8088 fetches instructions
starting from memory address FFFF0H
4-4
8088 Pin Description
Pin Name Pin Number Direction Description
READY 22 Input Informs the processor that the selected memory
or I/O device is ready for a data transfer
READY READY
8088 Selected memory
or I/O device wait for
memory Start data transfer
Data bus
or I/O ready
4-5
8088 Pin Description
Pin Name Pin Number Direction Description
HOLD 31 Input The execution of the processor is suspended
as long as HOLD is high
HLDA 30 Output Acknowledges that the processor is suspended
Procedure for Device 2 to use bus
8088 HOLD
Device 2 Drive the HOLD signal of 8088 high
HLDA
Wait for the HLDA signal of 8088
Bus becoming high
Now, Device2 can send data to bus
Memory
4-6
8088 Pin Description
Pin Name Pin Number Direction Description
NMI 17 Input Causes a non-maskable type-2 interrupt
INTR 18 Input Indicates a maskable interrupt request
INTA 24 Output Indicates that the processor has received an
INTR request and is beginning interrupt
processing
NMI (non-maskable interrupt): a rising edge on NMI causes a type-2 interrupt
INTR: logic high on INTR poses an interrupt request. However, this request can
be masked by IF (Interrupt enable Flag). The type of interrupt caused by
INTR is read from data bus
INTA: control when the interrupt type should be loaded onto the data bus
INTR
8088 INTR
External INTA
device
INTA
Data Bus Int. type
Data bus 4-7
8088 Pin Description
Pin Name Pin Number Direction Description
ALE 25 Output Indicates the current data on 8088 address/data
bus are address
A[19:8]
Buffer A[19:8]
ALE
8088 A[7:0]
AD[7:0] D Q
G
D latches
D[7:0]
4-8
8088 Pin Description
Pin Name Pin Number Direction Description
DEN 26 Output Disconnects data bus connection
DT / R 27 Output Indicates the direction of data transfer
DEN DT/R
1 X Disconnected
DEN
0 0 To 8088
0 1 From 8088
8088
DT/R
D[7:0]
Data
DEN DT/ R
bus
AD[7:0]
4-9
8088 Pin Description
Pin Name Pin Number Direction Description
WR 29 Output Indicates that the processor is writing to memory
or I/O devices
RD 32 Output Indicates that the processor is reading from
memory or I/O devices
IO/ M 28 Output Indicates that the processor is accessing whether
memory (IO/M=0) or I/O devices (IO/M=1)
WR WE WR or
RD OE RD Addr. I/O
Addr. CS Dec.
IO/M Dec. Memory
IO/M
8088
4-10
8088 Pin Description
Pin Name Pin Number Direction Description
AD[7:0] 9-16 I/O Address / Data bus
A[19:8] 2-8, 35-39 Input Address bus
SS0 34 Output Status Output
TEST 23 Input It is examined by processor testing instructions
LOCK 29 Input Lock output is used to lock peripherals off
the system. Activated by using the LOCK:
prefix on any instruction.
QS1 and QS0 24, 25 Input The queue status bits show status of
internal instruction queue. Provided for
access by the numeric coprocessor (8087).
4-11
10.3 CPU pin descriptions
8088 Status Signals 8088 Signal Summary
S2 S1 S0 Indicated Operation Signal Input Output Tri-State Minmode Maxmode
0 0 0 Interrupt acknowledge CLK * * *
0 0 1 I/O read MN/MX * * *
0 1 0 I/O write S0,S1,S2 * * *
0 1 1 Halt RESET * * *
1 0 0 Code access READY * * *
1 0 1 Memory read HOLD * *
1 1 0 Memory write HLDA * *
1 1 1 Passive NMI * * *
INTR * * *
INTA * *
Comparison of NMI and INTR
RQ/GT0 * * *
Disabled RQ/GT1 * * *
via LOCK * * *
Interrupt Triggered on: Software Priority ALE * *
NMI Rising edge No High DEN * * *
INT High level Yes Low DT/R * * *
WR * * *
RD MEMRD
RD * * * *
IO/M * * *
WR MEMWR AD0-AD7 * * * * *
A8-A19 * * * *
IORD
IOWR Decoding 8088 memory and I/O read/write signals
IO/M
8284 Clock Generator
8284 8088 Basic functions:
Ready1 RDY1 Clock generation.
Ready2 RDY2 RESET synchronization.
Ready Ready READY synchronization.
X1 Peripheral clock signal.
510
CLK CLK
X2
510
+5V RESET RESET
RES
100K
Generates 33% duty cycle clock signal
10uF Generates RESET signal
Synchronizes ready signals from memory
and I/O devices
4-14
10.4 The 8284 Clock Generator
5V
READY1 RDY1
READY2 RDY2
EFI CLK CLK
0 = crystal oscillator F/C
1 = TTL clock on EFI, CSYNC
synchronized on CSYNC AEN1 8088
4K7 AEN2 8284
qualifiers for 5V ASYNC
READY1,-2 2X510
X1 READY READY
X2 RES RESET RESET
1 = one WAIT state 10MHz
forced by READY 100K 0 = forces the P
10F 5V to froze the
1/3 fosc 1N4148 current bus cycle
1/3 duty cycle inserting WAIT
RES STATES (all
CLK [V] signals keep their
t values), allowing
X1,2 RESET slower devices
[V] 1L time to properly
t 0L t answer.
8288 Bus Controller
Separate signals are used for I/O ( IORC and IOWC ) and memory ( MRDC and MWTC ).
Also provided are advanced memory ( AIOWC ) and I/O ( AIOWC ) write strobes plus INTA .
4-16
74LS244
10.5 The 8288 Bus Controller
A8-A15 CPU Address Bus Identify the Memory Byte
(A16-A19, (one of 220 (216 in example))
if needed, OR the I/O port (one of 216)
G1 G2
should be to be read OR write
8282 latched the in the current bus cycle
AD0-AD7 D Q same way like
LE AD0-AD7) Advanced Write Commands,
STB OE providing additional access time
Data to be transferred
8088 for the selected circuit
8286 in the current bus cycle
CPU Data Bus Max one active at a time,
identifying Memory vs. I/O
OE T Data Transmit/Receive and Read vs. Write
DEN DT/R MRDC Memory ReaD Command
ALE MWTC Memory WriTe Command
S0 S0 IORC Input/Output Read Command
S1 S1 8288 IOWC Input/Output Write Command
S2 S2 INTA INTerrupt Acknowledge
Address AMWC Advanced Memory Write Command
Status Signals
Latch AIOWC Advanced Input/Output Write Command
(codify the bus
Enable IOB AEN CEN 5V Command Enable Control
cycle type)
Data Enable CLK I/O Bus only Address Enable Bus
System Timing Diagrams
T-State:
— One clock period is referred to as a T-State
T-State
— An operation takes an integer number of T-States
CPU Bus Cycle:
— A bus cycle consists of 4 or more T-States
T1 T2 T3 T4
4-18
Memory Read Timing Diagrams
• Dump address on address bus.
• Issue a read ( RD ) and set M/ IO to 1.
• Wait for memory access cycle.
4-19
Memory Read Timing Diagrams
T1 T2 T3 T4
CLK A[15:8]
ALE Buffer
A[15:0]
A[19:16] A[19:16] S3-S6
8088
AD[7:0]
A[15:8] A[15:8] D latch
AD[7:0] A[7:0] D[7:0]
Memory
IO/M D[7:0]
Trans
DT/R
DT/R -ceiver
DEN
DEN
IO/M
RD WR
RD
WR
4-20
Memory Write Timing Diagrams
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.
4-21
Memory Write Timing Diagrams
T1 T2 T3 T4
CLK A[15:8]
ALE Buffer
A[15:0]
A[19:16] A[19:16] S3-S6
8088
AD[7:0]
A[15:8] A[15:8] D latch
AD[7:0] A[7:0] D[7:0]
Memory
IO/M D[7:0]
Trans
DT/R
DT/R -ceiver
DEN
DEN
IO/M
RD WR
RD
WR
4-22
Bus Timing
During T 1 :
• The address is placed on the Address/Data bus.
• Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the
address onto the address bus and set the direction of data transfer on data
bus.
During T 2 :
• 8086 issues the RD or WR signal, DEN , and, for a write, the data.
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
• This cycle is provided to allow memory to access data.
• READY is sampled at the end of T 2 .
• If low, T 3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
• All bus signals are deactivated, in preparation for next bus cycle.
• Data is sampled for reads, writes occur for writes.
4-23
Setup & Hold Time
Setup time – The time before the rising edge of the clock, while the data must
be valid and constant
Hold time – The time after the rising edge of the clock during which the data
must remain valid and constant
4-24
Bus Timing Diagram
4-25
Bus Timing
Timing:
– Each BUS CYCLE on the 8086 equals four system clocking periods (T states).
– The clock rate is 5MHz , therefore one Bus Cycle is 800ns .
– The transfer rate is 1.25MHz .
Memory specs (memory access time) must match constraints of system timing.
For example, bus timing for a read operation shows almost 600ns are needed to
read data.
• However, memory must access faster due to setup times, e.g. Address setup and data
setup.
• This subtracts off about 150ns .
• Therefore, memory must access in at least 450ns minus another 30-40ns guard band for
buffers and decoders.
• 420ns DRAM required for the 8086.
4-26
4-27
10.6 System Time Diagrams - CPU Bus Cycle
CLK T1 T2 T3 TW T4
ALE Address latches store the actual values
IO/M Memory Cycle (I/O cycle is similar but IO/M = 1)
A16- A19 A16-A19 S3- S6
A8- A15 A8- A15
READY the P samples READY
The slow device drives READY= 0 (if 0 a WAIT state follows)
Read Cycle
RD (instruction fetch and memory operand read) P reads Data Bus
AD0- AD7 A0- A7 D0- D7 (Data in)
Tri-state
DT/R Direction “READ” for the Data Buffer
DEN Enables Data Buffer
Memory reads Data Bus
WR Write Cycle (memory operand write)
AD0- AD7 A0- A7 D0- D7 (Data out)
DT/R Direction “READ” for the Data Buffer
DEN Enables Data Buffer
Interrupt Acknowledge Timing Diagrams
T1 T2 T3 T4
CLK •••
INTR 8088 INTR
External
••• device
INTA
INTA
D[7:0] ••• Int. Type Data bus
It takes one bus cycle to perform an interrupt acknowledge
During T1, the process tri-states the address bus
During T2, INTA is pulled low and remains low until it becomes inactive in T4
The interrupting devices places an 8-bit interrupt type during INTA is active
4-29
HOLD/HLDA Timing Diagrams
T2 T3 T4
CLK ••• 8088 HOLD
Device 2
HOLD ••• HLDA
HLDA
Bus
Hold State Memory
The processor will examine HOLD signal at every rising clock edge
If HOLD=1, the processor will pull HLDA high at the end of T4 state (end of
the execution of the current instruction) and suspend its normal operation
If HOLD=0, the processor will pull down HLDA at the falling clock edge
and resume its normal operation
4-30
10.6 System Time Diagrams - INT and HOLD
Maxmode Interrupt acknowledge timing
CLK T1 T2 T3 T4 T1 T2 T3 T4
LOCK Prevents P to enter a HOLD state
INTA
AD0- AD7 INT type
Tri-state
First INTA cycle Second INTA cycle
two INTA cycles in maxmode, the device
Minmode Interrupt acknowledge timing requesting INT has to drive the “INT type”
CLK T1 T2 T3 T4 on the Data Bus, during the second cycle.
INTA a single INTA cycle in minmode.
AD0- AD7
Tri-state
INT type HOLD/HLDA Timing
CLK T4 T1
only after ending the current bus cycle
HOLD
HOLD state: the P releases the Address, HLDA
Data, Control and Status buses (these pins
are tri-sated (high impedance)
10.7 Personal Computer Bus Standards
CPU Medium Complexity PC Architecture
Simple P System Cash
P Bus Memory Main
Architecture Memory Bus
Memory Controller Memory
CPU
I/O Bus Plug-in I/O
P Bus I/O Bus
Memory Controller Boards
I/O
Motherboard - ISA = Industry Standard
PCI (Peripheral Component Interconnect bus) I/O Circuits Architecture (8 data bits =
based Architecture PC-XT bus, or 16 data bits
CPU = PC-AT bus)
- EISA = Extended ISA
Cash Memory Main - MCA = Micro Channel
P Bus Memory Bus
Architecture (only IBM)
Memory Controller Memory
Bridge Motherboard- and Fast
PCI Bus
Controller Plug-in I/O Circuits
I/O Bus Slow Plug-in
I/O Bus
Controller I/O Boards
Dual Independent Bus (DIB)
• Backside Bus
• Frontside Bus
4-33
Different level of Busses
4-34
