Dataflow VHDL

Bit Vector operations and conditional

concurrent signal assignments

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 1
 Outline
• Vector types and declarations
• Vector literal values
• Vector operations
• Slice reference and assignment
• Conditional concurrent assignment
• Relational operators
• Selected assignment
• Vector attributes

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 2
 Bit Vectors
• Signals can be more than one bit (a vector)
– Represent P address and data, function
selection, etc.
• Declaration is similar to single bit signals
– Type is bit_vector or std_logic_vector
• We also must specify vector index range
and direction
– big endian: (low to high)
– little endian: (high downto low)

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 3
 Vector Declarations

port (
A, B: in std_logic_vector(7 downto 0);
Z: out std_logic_vector(1 to 16)
);

A and B: 7 6 5 4 3 2 1 0

Z: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Note! The first bit and last bit index numbers define
the number of bits in the vector (i.e. max - min + 1)
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 4
 Vector Literals
• Single bit binary literals are ‘0’ and ‘1’
• Vector binary literals are “0101”, “10_01”
– literal values may have an underscore embedded to
improve readability
• For bit_vectors we can also specify values
using octal, decimal, or hexadecimal.
– O”1234” D”1999” X”ABCD”
– NOTE: This doesn’t work for std_logic_vectors;
use function “To_std_logic_vector” to translate

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 5
 Vector Logical Operations
• Single bit logical operations also apply to
vectors
– Operands MUST be the same size (generally
applies to all vector operations)
– Assignment target must also have the same
number of bits as the result
– Operations are applied bitwise to operands to
produce the vector result

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 6
 Vector Operations

Given:

Signal A, B, Z: std_logic_vector(7 downto 0);

Then the following logical operation and assignment

Z <= A and B;

Is equivalent to:
for i  0 to 7
Zi  A i and Bi ;

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 7
 Vector Arithmetic Operations
• Vector arithmetic operations are basically the
same as vector logical operations
– Operands MUST be the same size
– Assignment target must also have the same
number of bits as the result
– Operations are applied bitwise to operands to
produce the vector result
• The only difference is the carry or borrow
– Carry in/out must be specially handled
– Result can be 1 bit larger than operands (CO)
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 8
 4 bit Adder (Data Flow VHDL)
entity add4 is
port (a, b: in std_logic_vector (3 downto 0);
cin: in std_logic; cout: out std_logic;
s: out std_logic_vector(3 downto 0)
);
end add4;

architecture df of add4 is
signal tmpsum std_logic_vector(4 downto 0);
begin
tmpsum <= (‘0’ & a) + (‘0’ & b) + (“0000” & ci);
s <= tmpsum(3 downto 0);
co <= tmpsum(4);
end df;
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 9
 Add4 Example
• In the previous example note:
– The “&” symbol is the concatenation operator
• joins operands together so that result length is sum
of lengths of operands.
– In order to be able to access the MSB carry out
we had to add 5-bit values (used & operator to
add leading zeros to operands)
– To assign result to S, we had to access only the
least significant 4 bits of S; this is a SLICE
– The carry out is a single bit assignment of the
LSB of the result
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 10
 Multiplication and VHDL
• Again, for arithmetic operations
– Operands MUST be the same size
– Assignment target must also have the same
number of bits as the result
• However, for multiplication (*) what is not
stated is that the result of the operation is
twice the size of the operands
– For F <= A * B;
– If A and B are 4-bit vectors, result is 8 bits
– F must be declared as an 8-bit vector
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 11
 Slice Reference and Assignment

• A slice is a part of a vector

– accessed by a range clause
• (hi downto lo) or (lo to hi)
• indexes must be inside original range declaration
• range direction match the original range declaration
• e.g. tmpsum(3 downto 0);
– a single index is use to access a single bit
• e.g. tmpsum(4);
– Assignee must be the same size as the slice
• co <= tmpsum(4);

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 12
 Conditional Concurrent Assignment
• Up to now, signal assignment has been only
based on evaluation of operand changes
– expressions are boolean algebra only
– hard to understand what is being implemented

E.G. 4 to 1 mux:

Z <= (a and not s(1) and not s(0)) or

(b and not s(1) and s(0)) or
(c and s(1) and not s(0)) or
(d and s(1) or s(0));
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 13
 Conditional Concurrent Assignment
General Form:

target_signal <= value1 when cond1 else

value2 when cond2 else
*
valuem when condm else
valuen;

Note that the condition clauses must evaluate to a

logical expression.

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 14
 4 to 1 Mux (Cond. Concurrent Form)

Z <= A when s = “00” else

B when s = “01” else
C when s = “10” else
D;

Note that in the last case, we did not specify a

condition; this is the “when no other condition
is met” case.
Note also that we can conditionalize the last
case by if so, we must ensure that all possible
condition combinations are addressed.
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 15
 Relational Operators
• In the previous example we introduced a
new operator, the relational “equals”
– The relational operators are
= (equals) /= (not equals)
> (greater than) < (less than)
>= (greater or equal) <= (less or equal)
– Note that <= (less or equal) is same operator as
<= (signal assignment); i.e. context dependent
– Precedence of relational operators is between
“not” and the other logical operators.

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 16
 Selected Signal Assignment
• Another form of concurrent signal
assignment is the Select assignment
– Similar to a software CASE statement
• we first identify the “discriminator” signal or
expression we will test
• values and associated conditions are then identified
– Like conditional signal assignment we must
ensure that all cases of discriminator are
covered
• “others” condition makes this easy

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 17
 Selected Signal Assignment

General Form:

WITH discriminator SELECT

target_signal <= value1 WHEN choices1,
value2 WHEN choices2,
*
valuem WHEN choicesm,
valuen WHEN others;

The “choices” are values of the discriminator; either single,

multiple or a range.

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 18
 Selected Signal Assignment
• All possible values of the discriminator must be
covered
– single value: when “0001”,
– multiple values: when “0100” | “0110” | “1000”,
– value range: when“1010” to “1111”,
– everything else: when others;
• The last case “when others” must be the last
clause if used
• Comma separates clauses, semicolon ends the
statement
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 19
 Selected Signal Assignment

WITH digit SELECT

segs <= “1110111” when “0000”,
“0010010” when “0001”,
“1011101” when “0010”,
“1011011” when “0011”,
“0111010” when “0100”,
“1101011” when “0101”,
“0101111” when “0110”,
“1010010” when “0111”,
“1111111” when “1000”,
“1111010” when “1001”,
“1101101” when others;

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 20
 Vector Attributes
• Attributes allow access to signal definition
information
– useful when designing generic VHDL
– tells use range, index, length of a signal
• General form is
signal_name’attr_name

• Some attributes are pre-defined

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 21
 Pre-defined Attributes

Name: Definition

‘left index value on left of range

‘right index value on right of range
‘high greatest index value of range
‘low least index value of range
‘range range expression if signal
‘reverse_range reversed signal range expression
‘length number of bits in range

55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 22
 Pre-defined Attributes
signal ex: std_logic_vector(11 downto 8);

Attribute Value

ex‘left 11
ex‘right 8
ex‘high 11
ex‘low 8
ex‘range (11 downto 8)
ex‘reverse_range (8 to 11)
ex‘length 4
55:032 - Intro. to Digital Design Bit Vectors and Data Flow VHDL Slide 23