THE MICROPROCESSOR

Von Neumann’s Architecture Model

Input/Output unit P

Memory unit S

Arithmetic and logic unit P

Control unit C

Central processing unit = ALU + CU

Stored program 7→ P

1
 System Bus Architecture Model

System bus

Data bus

Address bus fi

Control bus fi

Power bus

I/O bus fi /

2
 Central Processing Unit

MAR
M
A MDR
I
N OpCode OpAddr A
DS
M
E
RW
M PC
O
R
Y Control HZN
ALU

3
 Instruction Cycle

Program counter (PC) -

Instruction register (IR)

Fetch-execute cycle: T
:

1. F

2. D

3. R ( ) ,

4. E

5. G 1

Opcode: ( )

Decoding D , -
( )
4
 Instruction Types

Formats: I
fi . ’C ’ 1
’C ’

Format 1: C ( : HLT)

Format 2: C A ( : JMP $0123)

Format 3: C D ( : ADD R, $01)

Format 4: C A 1 A 2
( : MOV $0123, $0200)

Register Transfer Language (RTL) I

microinstructions
.

Types:

• A : SUB R1, R2

• L : XOR R, $1010

• T : MOV R1, R2

• B : JNE $3210

• C : CLA
5
 Fetch-Execute Cycle
(E )

Step 0: A CPU
MAR
M
A Program MDR
I
N ... OpCode OpAddr
$002E: ... $05
$0030: ADD DS
M
$0032: $0036
E
$0034: HLT RW
M
$0036: $0001 $0030
O
$0038: ...
R
... HZN
Y Control
ALU

PC (P C ) = $0030, A = $0005

Step 1: F
MAR=$0030, PC = $0030
$0030
M
A Program $0099
I
N ...
$002E: ... ADD OpAddr $0005
$0030: ADD DS
M
$0032: $0036
E
$0034: HLT RW
M
$0036: $0001 $0032
O
$0038: ...
R
... HZN
Y Control
ALU

MDR = $0099 (ADD), O C = $0099,

PC = $0032
6
 Fetch-Execute Cycle
(E )

Step 2: D O C
$0099 = ADD,

Step 3a: F
MAR=$0032, PC = $0032
$0032
M
A Program $0036
I
N ...
$002E: ... ADD $0036 $0005
$0030: ADD DS
M
$0032: $0036
E
$0034: HLT RW
M $0034
$0036: $0001
O
$0038: ...
R
... HZN
Y Control
ALU

MDR = $0036, O A = $0036, PC = $0034

7
 Fetch-Execute Cycle
(E )

Step 3b: F
MAR=$0036
$0036
M
A Program $0001
I
N ...
$002E: ... ADD $0036 $0005
$0030: ADD DS
M
$0032: $0036
E
$0034: HLT RW
M $0034
$0036: $0001
O
$0038: ...
R
... HZN
Y Control
ALU

MDR = $0001

Step 4: E
A = $0005
$0036
M
A Program $0001
I
N ...
$002E: ... ADD $0036 $0006
$0030: ADD DS
M
$0032: $0036
E
$0034: HLT RW
M $0034
$0036: $0001
O
$0038: ...
R
... HZN
Y Control
ALU

MDR = $0001, A = A + MDR = $0006

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 Control Unit and Status Register

Control Unit . D -
: -
(O C ) -

Status Register: ALU CU

status register. E ( )

. E

C H N Z ... V

C: C (1 , 0 )

H: H (1 , 0 )

N: S (1 , 0 )

Z: Z (1 , 0 )

. . . . . . (1 ... , 0 )

V: O fl (1 fl , 0 )

.
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 Implementations of Control Unit

A :

Hardwired control: A
-
CPU. T :
CU . W
, CPU -
, ffi .

Microprogrammed control: B -
CU
control memory (CM). CM
PLD (ROM, PLA PAL). E
CM -
. T

CPU. I
-
( ) . T :
CU fi -
. W , CPU -
, . M
-
.
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 Microprogramming

M = -
fi -

Example of microprogram: A -
(ADD) CPU
3 4 -
,
.

Fetch cycle

1. F ( CPU)

2. D ( O C )

3. I P C (PC++)

Execute cycle

1. F fi

2. F

3. A ( )

4. S
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 Register Transfer Language (RTL)

Microoperations: A
: -
.
F , 3
ADD 2 -
:

1. A A: A ← A+ MDR

2. U N : N ← An−1

RTL . E

S R. I
RTL,

D←S
← S D. D -
fi S .

12
Register Transfer Language (RTL)
( )

Basic symbols for RTL

Arithmetic microoperations

Logic microoperations

Shift microoperations ( 350)

13
 Registers

Addressing Modes

S ’
, -
.

• I fl

• R

• A

• A

Effective address = -

14
 Addressing Modes

Implied mode: O
O C . E :

ADD #31

Immediate mode: O -
fi . E :

ADD R, #10

Register mode: O fi
. E :

ADD S, D

Register indirect mode: O -

fi
. E :

ADD (D), #3

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 Addressing Modes

Direct mode: A -
fi . E :

ADD @1234, S

Indirect mode: A -
. E :

ADD [@1234 , #10

Relative mode: C PC + O A . E -
:

ADD D, $S

Indexed mode: C +O -
A . E :

ADD D, @500(S)

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Summary of Addressing Modes

17
 Instruction Set Architecture

Machine language: B fi -
. L . V ffi
. E : CISC ,
2 37

100010 00000010 00100101

Assembly language: S

. E : RISC -
, 2 37 ( -
D S)

ADD D, S

Instruction set -
CPU. T
:

Reduced Instruction Set Computers: S

. H

Complex Instruction Set Computers: L

. M -

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 Elementary Instruction Set

T D T I

T A I

19
 Elementary Instruction Set
( )

T L B M I

T S I

20
 Elementary Instruction Set
( )

T P C I

C B I R S
B

21
 Elementary Instruction Set
( )

C B I U
N

C B I S
N

22
 RISC Architectures

1. M

2. A

3. I

4. S

5. I

6. L

7. S ( )

8. S

9. H

10. F

11. D ”
”
23
RISC Architectures
( )

24
 CISC Architectures

1. M

2. A

3. I ff

4. L

5. I -

6. S

7. S ( )

8. C

9. M

10. S
25
CISC Architectures
( )

26
CISC Architectures
( )

27
Example of Assembly Language Programming
under CISC architecture

Example: W -
x y. O −1 x < y; 0
x = y; +1 x > y.

MOVE R1, x
MOVE R2, y
MOVE R3, #0
SUB R1, R2
BN L
BZ Z
MOVE R3, #+1
L :
MOVE R3, #−1
Z :
MOVE R3, #0
HLT

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Example of Assembly Language Programming
under CISC architecture
( )

Example: W
1’ x

MOVE R1, x
MOVE R2, #1
MOVE R3, #0
MOVE R4, #32
L :
AND R2, R1
BZ U
INC R3
U :
MOVE R2, #1
ROR R1
DEC R4
BZ S
JMP L
S :
HLT

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