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The document lists 12 experiments involving designing various digital circuits using SPICE modeling and layout design: 1) Modeling a CMOS inverter 2) Modeling a CMOS NAND gate 3) Modeling a CMOS NOR gate 4) Designing a D-latch using NAND gates 5) Designing a half adder using NAND gates 6) Designing a full adder using half adders 7) Layout design of a PMOS transistor 8) Layout design of an NMOS transistor 9) Layout design of a CMOS inverter with equal rise/fall times 10) Layout design of 2-input and 3-input NAND gates 11

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32 views1 page

Vlsi

The document lists 12 experiments involving designing various digital circuits using SPICE modeling and layout design: 1) Modeling a CMOS inverter 2) Modeling a CMOS NAND gate 3) Modeling a CMOS NOR gate 4) Designing a D-latch using NAND gates 5) Designing a half adder using NAND gates 6) Designing a full adder using half adders 7) Layout design of a PMOS transistor 8) Layout design of an NMOS transistor 9) Layout design of a CMOS inverter with equal rise/fall times 10) Layout design of 2-input and 3-input NAND gates 11

Uploaded by

supreet23
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© Attribution Non-Commercial (BY-NC)
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LIST OF EXPERIMENTS:

1. Write a spice programme for CMOS Inverter with following details PMOS, L=8um,
W=12.0um, NMOS L=8um, W=2.4um, NMOS (kp=60u V to = 0.6 U). PMOS (kp=20U, V +0
= 008v).

2. Write a spice programme for CMOS NAND Gate with following details: Vdd = 5V, PMOS;
L=8um W=20um, NMOS, L=8um W=8um NMOS (kp=45v V to = 1.0 V) PMOS (kp=25U,
Vto =1.2V).

3. Write a spice programme for CMOS NOR gate with following details: Vdd = SV, PMOS;
L=8um W=20um NMOS L=8um W=8um NMOS (kp=45U V to = 1.0V) PMOS (kp = 25U,
V+0 = 1.2V).

4. Design a D-Latch with clock time period = 6ns using NAND gate with following
specifications L = 2U W=100U for nd PMOS. For N-MOS. Kn=60U V +0 = 0.6V for PMOS ,
kp = 20U V+0=0.8V.

5. Design a half Adder using NAND gates with following specification for NMOS L=2U.
W=100U for PMOS L=2U W=550U. For nMOS K n=60U V+0=0.6V and for PMOS KP=20U
V+0 = 0.8V.

6. Design a full Adder using half Adder (As per specification given above for half adder.

7. Design the Layout for PMOS in Layout Editor.

8. Design the Layout for NMOS in Layout Editor.

9. Design the Layout for CMOS inverter with equal rise time and fall time in L-editor.

10. Design the Layout for 2-input and 3-input NAND gate.

11. Design the Layout for 2-input of 3 input NOR Gate.

12. Design the Layout for Clocked S-R flip-flop.

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