1 2 3 4 5 6

D D

VCC
VCC

R1
2k2
R2 R3
4k7 4k7

D1 JP2 VCC
SCH P11
1 2
P10
3 4
5 6 C6
JP1 U1
7 8 1uF
P1 1 20 OSC1 27pF P9
1 2 RA2 RA1 9 10
P2 2 19 C4 P8
3 4 RA3 RA0 X1 11 12
C P3 3 18 P7 C
5 6 RA4 OSC1 3.68MHZ 13 14
MCLR 4 17 P6
7 8 MCLR OSC2 15 16
GND 5 16 OSC2 27pF
9 10 VSS VDD
P4 6 15 C5 Header 2x8
11 12 VSS VDD
P5 7 14
13 14 RB0 RB7
8 13
15 16 RX RB6
9 12
TX RB5
Header 2x8 10 11
RB3 RB4
PIC16LF628

C1
.1uF

VCC
C1+ U2
.1uF
C2 2 19 C8 C3
C1+ VCC 1uF .1uF
C1- 4 3 V+
C7 C1- V+
C2+ 5
1uF C2+
C2- 6
C2-
TX 13 17
C9
12 8 1uF JP3
1
RX 15 16 6
B Q1 TXdb9 2 B
NMOS 10 9 7
RXdb9 3
1 11 8
EN INVALID
20 DTRdb9 4
FORCEOFF
14 9
FORCEON
18 7 V- 5
GND V-
MAX3223 DB9

PIC16F628 Configuration Bits

Design Engineer Date
Oscillator: HS
Project Manager Date
WatchDog Timer: Off
PowerUp Timer: On
A Code Protect: Off A
Bownout Detect: disabled
MCLR: enabled
Low Voltage Programming: disabled
Data EE Protect: disabled
Revision History:
Ltr: Description: Date: Approved by: Dallas Semiconductor
Title PIC Reference Design for AN206 4401 S Beltwood Pkwy
Dallas Tx., 75491
Size: Tabloid Number:1 Revision: 1.0
USA
Date: 31-May-2002 Time: 09:11:10 Sheet 1 of 1
File: C:\Protel Hardware\DSIO\DSIO\DSIO.ddb - AN206\AN206 Reference Design.Sch
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