D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Abstraction levels
0234 2FE4 14DA
0F AB 34

System level
+

>

Algorithmic level &

RT level

Logic level

Physical level

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Y-chart
S ystem level

A lgorithm ic level
B eh aviou ral D om ain S tru ctu ral D om ain
R egister transfer level
System Sp ecification
L ogic level C P U , M em ory
A lgorithm P rocessor, Su b-system
R egister-transfer specification C ircu it level A L U , R egister, M U X
B oo lean E qu ation G ate, F lip -flop
D ifferen tial E qu ation Tran sistor

R ectangle / P olygon -G rou p

S tan dard -C ell / Su b-cell

M acro-cell

B lock / C h ip

C hip / B oard

P h ysical D om ain

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 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Y-transformations

S y n th esis

B eh aviou ral D om ain A n aly sis S tru ctu ral D om ain

Re
fin
em
Ab ent
s tr a
c tio O p tim iz atio n
n G en era tio n

E x tra ctio n

P hysical D om ain
(G e o m e trica l D o m a in )

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Levels revealed
Hierarchy
Abstraction Supporting tools
level
System space-time behavior as instruction, flow-charts, diagrams,
timing & pin assignment specifications high-level languages
Architecture global organization of HDLs, floor-planning block diagrams
functional entities for clock cycle and area estimation
Register binding data flow functional modules synthesis, simulation, verification, test
transfer and microinstructions analysis, resource use evaluation
Functional primitive operations and libraries, module generators, sche-
modules control methods matic entry, test
Logic Boolean function of Schematic entry, synthesis and simu-
gate circuits lation, verification, PLA tools
Switch electrical properties of RC extraction, timing verification,
transistor circuits electrical analysis
Layout geometric constraints layout editor/compactor, netlist extrac-
tor, DRC, placement and routing

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 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Synthesis systems

• System synthesis

• Interface synthesis

• High-level synthesis

• Formal synthesis

• RTL synthesis

• Logic synthesis

• Test synthesis

• Physical synthesis

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Synthesis levels and tasks

• System Level Synthesis
• Clustering
• Communication synthesis
• High-Level Synthesis
• Resource or time constrained scheduling
• Resource allocation
• Binding
• Register-Transfer Level Synthesis
• Data-path synthesis
• Controller synthesis
• Logic Level Synthesis
• Logic minimization
• Optimization, overhead removal
• Physical Level Synthesis
• Library mapping
• Placement
• Routing

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 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Hierarchical decomposition

control control

PE C M PE C M

control control control

PE C M PE C M PE C M

• Control units - micro-controllers, FSMs, etc.

• Processing elements - CPUs, DSPs, custom made, etc.
• Communication units - hard-wired, programmable, etc.
• Memories - DRAMs, SRAMs, register files, etc.

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Design phases
• Design phases in a top-down language driven design methodology

Level Behavioral domain Structural domain Physical domain

Architectural design
System Specification
System partitioning
High Level Synthesis
Algorithm Structural Design
RTL Synthesis
Controller Synthesis
Datapath
RTL Logic Design
synthesis
Datapath controller
Logic Synthesis
Logic Layout Design
Datapath Compiler
FPGA Compilation
ASIC P+R
Circuit
Custom Cell Systems
[Turnbull1992] and P+R

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 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

ASIC design flow

• [Smith97]

VHDL/Verilog
Prelayout Design entry
simulation
netlist
Logic synthesis

System partitioning

Postlayout Floorplanning chip

simulation
Placement
back-annotated
netlist block
Circuit Routing
extraction logic cells

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

System-on-a Chip Design Process

• [Keating98]
The canonical or generic form of System-on-a-Chip design consists of
• a microprocessor and its memory subsystem
(8 -- 64 bit, RISC/CISC, multiple processors, DSPs, single/multilevel memory system,
SRAM/DRAM, ...);
• a datapath that includes interfaces to the external system
(PCI, Ethernet, USB, A/D, D/A, ...);
• blocks that perform transformations on data received from the external system
(graphical coprocessor, network router, ...);
• another I/O interface to the external system.

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 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Canonical HW view

Pheripherals

Memory
PROCESSOR controller MEMORY

System bus

I/O Data I/O

Interface transformation Interface

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Waterfall vs. Spiral

• Traditional ASIC development follows so called waterfall model.

• In WF model, the project transitions from phase to phase in a step function,

never returning to the activities of the previous phase.
(“Tossing” the project over the wall from one team to the next)
But:
• Complexity increases
• Geometry shrinks
• Time-to-market pressure increases

• In the spiral model, the design teams work on multiple aspects of the design
simultaneously, incrementally improving in each area as the design converges
on completion.

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Waterfall model

Specification
1111
0000
development
RTL code
0000
1111
0000
1111
development
Functional
0000
1111
00000
11111 Design
verification
00000 information
11111
Synthesis 0000
1111
0000
1111
flow
0000
1111
Timing 00000
11111
00000
11111
verification
00000
11111
Works well until Place and 00000
11111
100k gates 00000
11111
0.5 µ m
route
00000
11111
Prototype 0000
1111
0000
1111
build and test
0000
1111
Deliver to system integration and software test

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

System-on-a-chip design flow

• Parallel, concurrent development of HW and SW

• Parallel verification and synthesis of modules

• Floor-planning and place-and-route included in the synthesis

• Modules developed only if a predesigned hard and soft macro is not available

• Planned iteration throughput

• All aspects of HW and SW design are addressed concurrently -

functionality, timing, physical design, and verification

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System-on-a-chip design flow

TIME
SYSTEM DESIGN AND VERIFICATION
S P E C I F I C A T I O N S
PHYSICAL TIMING HARDWARE SOFTWARE
Area, power, I/O timing, Algorithm Application
clock tree clock freq. development, prototype
design macro decom. development
Preliminary Block Block Applicaton
timing selection/ prototype
floorplan specification design testing
Updated Block Block Application
floorplans synthesis verification development
Updated Top−level Application
floorplans HDL testing

Trial Top−level Top−level Application

placement synthesis verification testing

FINAL PLACE AND ROUTE

TAPEOUT

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Top-down

• Write complete specifications for the system or subsystem being designed

• Refine its architecture and algorithms, including SW design and HW/SW

cosimulation if necessary

• Decompose the architecture into well-defined macros

• Design or select macros (recursion here!)

• Integrate macros into the top level; verify functionality and timing

• Deliver the subsystem/system to the next higher level of integration;

at the top level this is tapeout

• Verify all aspects of the design (functionality, timing, etc.)

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... vs. Bottom-up

• There are:
• Synthesis and emulation tools
• Libraries of reusable macros

• The design can be started at lowest level as well!

• At top level is difficult to estimate acceptable complexity of lowest level blocks

==> let’s mix approaches to meet in the middle.
• Faster
• Fewer iterations

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Construct by correction

• SUN Microsystems approach on developing UltraSPARC processor

• Single team form architectural definition through place and route

• Fast first pass

• Multiple consequential iterations

• Another approach is “correct by construction”, where the intent is to get the

design completely right during the first pass
• Complexity of the UltraSparc processor (processor system) excluded the use of
“correct by construction” approach

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The Specification Problem

• Specification phase is considered to be the most crucial, challenging, and

lengthy phase of the project

• Initial specifications has to be recursively developed, verified, and refined until

they are detailed enough to allow RTL coding to begin

• Perfect specification yields:

• fast recovery of mistakes during following stages
• cheaper documentation

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Specification requirements

HW SW
Functionality Functionality
Timing Timing
Performance Performance
Interface to SW Interface to HW
Physical design issues SW structure, kernel
such as area, power

• There are:
• Formal specifications - no implementation details (VSPEC for VHDL)
• Executable specification (C, C++, SDL, VHDL, Verilog)

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System Design Process

• System specification
• Functions, performance, cost, development time

• Model refinement and test

• Focus on the algorithm, not the implementation!

• HW/SW partitioning (decomposition)

• ... largely a manual process
• Finally, define interfaces between SW and HW, and specify communication protocol

• Block specification
• Elaborate hardware specification and software specification

• System behavioral model and cosimulation

• Cosimulate and refine (The cosimulation continues throughout the design process)

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D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Inventory of tools for the IP Creator

Specifications Adobe Framemaker
Revision Control Rational Clearcase
Project Tracking Microsoft Project
Design Entry GNU Emacs
Verification Language Synopsys VERA
HDL Language Verilog
HDL Lint LEDA Proton
Simulation Synopsys VCS
Code Coverage Synopsys Covermeter
Synthesis Synopsys Design Compiler
Static Timing Synopsys Primetime
RTL Translation Avant! Nova-Trans
Formal Verification Synopsys Formality
IP Packaging Synopsys coreBuilder
IP Delivery Synopsys coreConsultant
Building Block IP Synopsys DesignWare

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