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Memory Hierarchy

The document summarizes the memory hierarchy and organization of main memory. It describes how memory chips like RAM and ROM are connected to the CPU through address and data buses. The address bus selects the specific byte location in a chip, while other lines use chip select inputs to select individual chips. This allows the CPU to read and write data to different memory locations through the connection between memory chips and address/data buses.

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108 views4 pages

Memory Hierarchy

The document summarizes the memory hierarchy and organization of main memory. It describes how memory chips like RAM and ROM are connected to the CPU through address and data buses. The address bus selects the specific byte location in a chip, while other lines use chip select inputs to select individual chips. This allows the CPU to read and write data to different memory locations through the connection between memory chips and address/data buses.

Uploaded by

nancy_01
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Memory Organization 1 Memory Hierarchy

MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible


access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape

Computer Organization Computer Architectures Lab


Memory Organization 2 Main Memory

MAIN MEMORY
RAM and ROM Chips
Typical RAM chip

Chip select 1 CS1


Chip select 2 CS2
Read RD 128 x 8 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus


0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedence

Typical ROM chip

Chip select 1 CS1


Chip select 2 CS2
512 x 8 8-bit data bus
ROM
9-bit address AD 9

Computer Organization Computer Architectures Lab


Memory Organization 3 Main Memory

MEMORY ADDRESS MAP


Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus


Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU


- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select


the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs

Computer Organization Computer Architectures Lab


Memory Organization 4 Main Memory

CONNECTION OF MEMORY TO CPU


Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2
RD 128 x 8 Data
RAM 4
WR
AD7

CS1
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM

Computer Organization Computer Architectures Lab

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