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Logic Design Lab

LOGIC DESIGN LABORATORY LIST OF EXPERIMENTS. (i) REALISATION of parallel adder / subtractor using 7483 chip. (ii) BCD to XS3 code conversion and vice versa.

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0% found this document useful (0 votes)
38 views

Logic Design Lab

LOGIC DESIGN LABORATORY LIST OF EXPERIMENTS. (i) REALISATION of parallel adder / subtractor using 7483 chip. (ii) BCD to XS3 code conversion and vice versa.

Uploaded by

manjubmg
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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LOGIC DESIGN LABORATORY

LIST OF EXPERIMENTS
1.Simplification and realization of given Boolean expression using Logic
gates/universal gates....................................................................
2.Realization of half/full adder and half/full subtractor using logic gates.... .
3.(i) REALISATION of parallel adder/subtractor using 7483 Chip..............
(ii) BCD to XS3 code conversion and vice versa.
4.Realisation of Binary to Gray code converter and vice versa.................
5.Realization of one/two bit comparator and study of 7485 magnitude
comparator...................................................................................
6 MUX/DEMUX and use of 74153, 74139 for arithmetic circuits and code
Converter.......................................................................................
7. Use of
Decoder chip to drive LED/LCD display.
Priority encoder.................................................................. .
8.Truth table verification of flip flops.
(i) J -K master slave
(ii) T-Type
(iii) D-Type............................................................................... .
9.Realization of 3-bit counters as a sequential circuit and mod-N counter design
(7476,7490,74192,74193)......................................................... .
10.Shift left, shift right, SIPO, SISO, PISO, PIPO operations using 7495...
11.Design and testing of Ring counter/Johnson counter........................
12.Design of sequence generator.......................................................

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