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Reconfigurable Cryptographic RISC Microprocessor

This document proposes a reconfigurable cryptographic microprocessor with instruction-controlled coprocessors that can perform encryption algorithms like AES (Rijndael) and DES in parallel. The microprocessor reduces the need for large lookup tables by using a RISC instruction set and specialized coprocessors. The Rijndael coprocessor can encrypt/decrypt 128-bit blocks efficiently in parallel with other operations. A DES coprocessor supports bit permutation instructions to reorder bits for encryption methods like Twofish and Serpent. The microprocessor utilizes these coprocessors along with standard CPU components via control signals to manipulate data for cryptographic results.

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Kalidas Selvaraj
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39 views1 page

Reconfigurable Cryptographic RISC Microprocessor

This document proposes a reconfigurable cryptographic microprocessor with instruction-controlled coprocessors that can perform encryption algorithms like AES (Rijndael) and DES in parallel. The microprocessor reduces the need for large lookup tables by using a RISC instruction set and specialized coprocessors. The Rijndael coprocessor can encrypt/decrypt 128-bit blocks efficiently in parallel with other operations. A DES coprocessor supports bit permutation instructions to reorder bits for encryption methods like Twofish and Serpent. The microprocessor utilizes these coprocessors along with standard CPU components via control signals to manipulate data for cryptographic results.

Uploaded by

Kalidas Selvaraj
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Reconfigurable Cryptographic RISC Microprocessor

ABSTRACT:

An instruction controlled reconfigurable cryptographic microprocessor


is proposed in this paper for safe keeping digital life from various
malicious attacks.

The need for dedicating a large memory for LUTs to perform Bit
permutation operations is greatly reduced by the introduction of RISC
instruction set. Two Advanced encryption standards Rijndael and DES
are programmed as coprocessors for parallel processing and to optimize
the cryptographic instructions by reducing it footprint cache.

The Rijndael coprocessor has been designed to perform Rijndael with a


128-bit key and data length in as few cycles as possible while being
resource efficient. This coprocessor also operates in parallel to the
RISC pipeline, therefore the coprocessor can be instructed to
encrypt/decrypt a block of data in parallel to extraneous functions.

DES coprocessor is supporting unit for Bit permutation instructions,


in which encryption is achieved by re-ordering bits within a register
to different locations, combining arbitrary bits within several
registers, and duplicating arbitrary bits and inserting into a chosen
location. Twofish, and Serpent are the other bit permutation methodologies for data dependent diffusion performed using
DES coprocessor instructions.

Rijendeal and Twofish algorithm implies Galosis field arithmetic for


manipulating polynomial Matrix multiplications using POINT ADDITION
and POINT DOUBLING.

A typical CPU unit with RAM, ALU, PC, Register bank and Buses are
included as prioritized units for utilizing the Cryptographic co
processers which consists of Parallel Processing Unit, Bit permutation
unit, sequencing cache and Byte permutation unit.

The typical CPU issues the control signal for coprocessors by fetching
and decoding the instruction set from memory and the instructions can
be executed with that control signal by shifting, rotating and
manipulating the cipher text using PPU,BPU and Galosis Field designs
the cryptic results are written back to the memory locations.

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