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Vlsi Design

1) The document contains instructions for a 3 hour exam with 12 questions divided into two sections worth a total of 100 marks. Questions can have multiple parts requiring explanations, derivations, diagrams and VHDL code. 2) The first section deals with topics like VLS1 design flow, VHDL code for counters and shift registers, metastability solutions, state diagrams for controllers, architectural blocks of CPLDs and FPGAs. 3) The second section covers two phase clock systems, SRAM architecture, power distribution techniques, CMOS inverters, transmission gates, design for testability, fault coverage, boundary scan and JTAG. Students are required to answer questions by writing in separate books and

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137 views2 pages

Vlsi Design

1) The document contains instructions for a 3 hour exam with 12 questions divided into two sections worth a total of 100 marks. Questions can have multiple parts requiring explanations, derivations, diagrams and VHDL code. 2) The first section deals with topics like VLS1 design flow, VHDL code for counters and shift registers, metastability solutions, state diagrams for controllers, architectural blocks of CPLDs and FPGAs. 3) The second section covers two phase clock systems, SRAM architecture, power distribution techniques, CMOS inverters, transmission gates, design for testability, fault coverage, boundary scan and JTAG. Students are required to answer questions by writing in separate books and

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XXX
Copyright
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Total No~of Questions : 12 [Total No.

of Pages :2
Pl170 [3064]-464
B.E. (E & TIC)
VLSIDESIGN
(2003 Course)
Time: 3 Hours] {Max. Marks: 100
Instructions to candidates:
1) Answers to the two sections should be written in separate books.
2) Neat diagrams must be drawn wherever necessary.
3) Use of electronic pocket calculator is allowed.
4) Assume suitable data, if necessary.

SECTION -I
Ql) a) Explain VLS1design flow in qetail. [9]
b) Write VHDL code for 4 bit UP/ DOWN counter. Also write test bench
for it. [9]
OR
Q2) a) Differentiate function and procedure What do you mean by subprogram
overloading? [9]
. b) Write Vl-IpL code for 4 bit shift Register for S1SO operation. Also,
write test bench for it. [9]

Q3) a) What do you mean by metastability? What are the solutions? Explain
anyone. solution in detail. [8]
b) Draw the state diagram & write VHDL code for Traffic Light Controller.
. [8]
OR
Q4) a) Differentiate Moore & Mealy Machines with suitable example. [8]
b) Draw the state diagram & write VHDL code for Lift controller. [8]

Q5) a) With neat schematic explain the architectural building blocks of CPLD.
. [10]
b) Differentiate CPLD w.r.t. FPGA. [6]
OR

P. T.O.
(

Q6) a) What is the difference between logic implemented in CPLD & FPGA?
[6]
b) Withneat schematic explain the architectural building blocks ofFPGA.
[10]
SECTION- II

Q7) a) What are the limitations of single phase clock? Explain with neat
schematic two phase clock system in detail. [9]
b) What is need of clock distribution. Explain tecjJ.niques of clock
distribution. [9)
OR
Q8) a) Draw and explain the CMOS architecture of SRAM. [9]
b) Why is power distribution to be taken care of? Explain on chip power
distribution and optimization techniques in brief. [9]

Q9) a) Explain CMOS Inverter and its tranfer characteristics in detail. How to
achieve symmetry in this characteristics. [8]
b) What is mean by dynamic power dissipation? Derive the expression for
it. [8]
OR
Ql0) a) Explain Transmission Gate and anyone application of it in detail. [8]
b) Draw the equivallent ckt. of MOSFET..What is Body effect? What are
the device parasitics? [8]

Ql1) a) What is need of designfor tes!ability?What do you mean.by observability


& controllability? [8]
b) With suitable schematic explain stuck at faults. What is mean by Fault
coverage? [8]
OR
Q12) a) Explain Boundary -Scanin detail. What isBIST? [8]
b) Explain JTAG.What are the various pins involved? [8] -

:ft:ft:ft

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