dsPIC30F6010A/6015

Data Sheet
High-Performance, 16-bit
Digital Signal Controllers

© 2008 Microchip Technology Inc. DS70150D

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS70150D-page ii © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
High-Performance, 16-bit Digital Signal Controllers

Peripheral Features:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • High-current sink/source I/O pins: 25 mA/25 mA
intended to be a complete reference • Timer module with programmable prescaler:
source. For more information on the CPU,
- Five 16-bit timers/counters; optionally pair
peripherals, register descriptions and
16-bit timers into 32-bit timer modules
general device functionality, refer to the
“dsPIC30F Family Reference Manual” • 16-bit Capture input functions
(DS70046). For more information on the • 16-bit Compare/PWM output functions
device instruction set and programming, • 3-wire SPI modules (supports 4 Frame modes)
refer to the “dsPIC30F/33F Programmers • I2CTM module supports Multi-Master/Slave mode
Reference Manual” (DS70157). and 7-bit/10-bit addressing
• 2 UART modules with FIFO Buffers
High-Performance Modified RISC CPU: • 2 CAN modules, 2.0B compliant (dsPIC306010A)
• Modified Harvard architecture • 1 CAN module, 2.0B compliant (dsPIC306015)
• C compiler optimized instruction set architecture
with flexible Addressing modes Motor Control PWM Module Features:
• 83 base instructions
• 8 PWM output channels:
• 24-bit wide instructions, 16-bit wide data path
- Complementary or Independent Output
• 144 Kbytes on-chip Flash program space modes
(Instruction words)
- Edge and Center-Aligned modes
• 8 Kbytes of on-chip data RAM
• 4 duty cycle generators
• 4 Kbytes of nonvolatile data EEPROM
• Dedicated time base
• Up to 30 MIPS operation:
• Programmable output polarity
- DC to 40 MHz external clock input
• Dead-Time control for Complementary mode
- 4 MHz-10 MHz oscillator input with
• Manual output control
PLL active (4x, 8x, 16x)
• Trigger for A/D conversions
- 7.37 MHz internal RC with PLL active
(4x, 8x, 16x)
Quadrature Encoder Interface Module
• 44 interrupt sources:
Features:
- 5 external interrupt sources
- 8 user selectable priority levels for each • Phase A, Phase B and Index Pulse input
interrupt source • 16-bit up/down position counter
- 4 processor trap sources • Count direction status
• 16 x 16-bit working register array • Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
DSP Engine Features: • Alternate 16-bit Timer/Counter mode
• Dual data fetch • Interrupt on position counter rollover/underflow
• Accumulator write-back for DSP operations
Analog Features:
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional • 10-bit Analog-to-Digital Converter (ADC) with
saturation logic 4 S/H Inputs:
• 17-bit x 17-bit single-cycle hardware fractional/ - 1 Msps conversion rate
integer multiplier - 16 input channels
• All DSP instructions single cycle - Conversion available during Sleep and Idle
• ±16-bit single-cycle shift • Programmable Brown-out Reset

© 2008 Microchip Technology Inc. DS70150D-page 3

dsPIC30F6010A/6015
Special Microcontroller Features: CMOS Technology:
• Enhanced Flash program memory: • Low-power, high-speed Flash technology
- 10,000 erase/write cycle (min.) for • Wide operating voltage range (2.5V to 5.5V)
industrial temperature range, 100K (typical) • Industrial and Extended temperature ranges
• Data EEPROM memory: • Low-power consumption
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip,
low-power RC oscillator for reliable operation
• Fail-Safe Clock Monitor operation detects clock
failure and switches to on-chip, low-power RC
oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes

dsPIC30F Motor Control and Power Conversion Family

Program Output Motor

UART
SRAM EEPROM Timer Input A/D 10-bit Quad

I2C™

CAN
SPI
Device Pins Mem. Bytes/ Comp/Std Control
Bytes Bytes 16-bit Cap 1 Msps Enc
Instructions PWM PWM

dsPIC30F6010A 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

dsPIC30F6015 64 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 1

DS70150D-page 4 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
Pin Diagram

80-Pin TQFP

OC8/UPDN/CN16/RD7

EMUD2/OC2/RD1
OC6/CN14/RD5
OC7/CN15/RD6

IC6/CN19/RD13
OC5/CN13/RD4
PWM2H/RE3

PWM1H/RE1
PWM2L/RE2

PWM1L/RE0
PWM3L/RE4

C2RX/RG0
C2TX/RG1

C1RX/RF0
C1TX/RF1

IC5/RD12
OC4/RD3
OC3/RD2
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1 60 EMUC1/SOSCO/T1CK/CN0/RC14
PWM3H/RE5
59 EMUD1/SOSCI/CN1/RC13
PWM4L/RE6 2
58 EMUC2/OC1/RD0
PWM4H/RE7 3
57 IC4/RD11
T2CK/RC1 4
56 IC3/RD10
T4CK/RC3 5
55 IC2/RD9
SCK2/CN8/RG6 6
54 IC1/RD8
SDI2/CN9/RG7 7
SDO2/CN10/RG8 8 53 INT4/RA15
MCLR 9 52 INT3/RA14
51 VSS
SS2/CN11/RG9 10 dsPIC30F6010A
VSS 11 50 OSC2/CLKO/RC15
49 OSC1/CLKI
VDD 12
FLTA/INT1/RE8 48 VDD
13
FLTB/INT2/RE9 47 SCL/RG2
14
AN5/QEB/CN7/RB5 46 SDA/RG3
15
AN4/QEA/CN6/RB4 16 45 EMUC3/SCK1/INT0/RF6
AN3/INDX/CN5/RB3 17 44 SDI1/RF7
AN2/SS1/CN4/RB2 18 43 EMUD3/SDO1/RF8
PGC/EMUC/AN1/CN3/RB1 19 42 U1RX/RF2
PGD/EMUD/AN0/CN2/RB0 20 41 U1TX/RF3
21
22

34
35
36
37
38
39
40
23
24
25
26
27
28
29
30
31
32
33

IC7/CN20/RD14
AVSS

VSS
VREF+/RA10
AN6/OCFA/RB6
AN7/RB7
VREF-/RA9

AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11

AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15

IC8/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
AVDD

VDD

Note: Pinout subject to change.

© 2008 Microchip Technology Inc. DS70150D-page 5

dsPIC30F6010A/6015
Pin Diagram

64-Pin TQFP

OC8/UPDN/CN16/RD7

OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4

EMUD2/OC2/RD1
OC7/CN15/RD6
PWM2H/RE3

PWM1H/RE1
PWM3L/RE4

PWM2L/RE2

PWM1L/RE0

C1RX/RF0
C1TX/RF1

OC4/RD3
OC3/RD2
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3H/RE5 1 48 EMUC1/SOSCO/T1CK/CN0/RC14
PWM4L/RE6 2 47 EMUD1/SOSCI/T4CK/CN1/RC13
PWM4H/RE7 3 46 EMUC2/OC1/RD0
SCK2/CN8/RG6 4 45 IC4/INT4/RD11
SDI2/CN9/RG7 5 44 IC3/INT3/RD10
SDO2/CN10/RG8 6 43 IC2/FLTB/INT2/RD9
MCLR 7 42 IC1/FLTA/INT1/RD8
SS2/CN11/RG9 8 dsPIC30F6015 41 VSS
VSS 9 40 OSC2/CLKO/RC15
VDD 10 39 OSC1/CLKI
AN5/QEB/IC8/CN7/RB5 11 38 VDD
AN4/QEA/IC7/CN6/RB4 12 37 SCL/RG2
AN3/INDX/CN5/RB3 13 36 SDA/RG3
AN2/SS1/CN4/RB2 14 35 EMUC3/SCK1/INT0/RF6
AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2
AN0/VREF+/CN2/RB0 16 33 EMUD3/U1TX/SDO1/RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6

AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11

AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
AVDD
AVSS

VSS
VDD

U2RX/CN17/RF4
U2TX/CN18/RF5

Note: Pinout subject to change.

DS70150D-page 6 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Address Generator Units............................................................................................................................................................ 35
5.0 Interrupts .................................................................................................................................................................................... 41
6.0 Flash Program Memory.............................................................................................................................................................. 49
7.0 Data EEPROM Memory ............................................................................................................................................................. 55
8.0 I/O Ports ..................................................................................................................................................................................... 59
9.0 Timer1 Module ........................................................................................................................................................................... 65
10.0 Timer2/3 Module ........................................................................................................................................................................ 69
11.0 Timer4/5 Module ....................................................................................................................................................................... 77
12.0 Input Capture Module ................................................................................................................................................................ 81
13.0 Output Compare Module ............................................................................................................................................................ 85
14.0 Quadrature Encoder Interface (QEI) Module ............................................................................................................................. 89
15.0 Motor Control PWM Module ....................................................................................................................................................... 95
16.0 SPI Module............................................................................................................................................................................... 105
17.0 I2C™ Module ........................................................................................................................................................................... 109
18.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 117
19.0 CAN Module ............................................................................................................................................................................. 125
20.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module ................................................................................................ 137
21.0 System Integration ................................................................................................................................................................... 149
22.0 Instruction Set Summary .......................................................................................................................................................... 165
23.0 Development Support............................................................................................................................................................... 173
24.0 Electrical Characteristics .......................................................................................................................................................... 177
25.0 Packaging Information.............................................................................................................................................................. 217
Appendix A: ....................................................................................................................................................................................... 221
Index ................................................................................................................................................................................................. 223
The Microchip Web Site ..................................................................................................................................................................... 229
Customer Change Notification Service .............................................................................................................................................. 229
Customer Support .............................................................................................................................................................................. 229
Reader Response .............................................................................................................................................................................. 230
Product Identification System ............................................................................................................................................................ 231

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© 2008 Microchip Technology Inc. DS70150D-page 7

dsPIC30F6010A/6015
NOTES:

DS70150D-page 8 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmers
Reference Manual” (DS70157).
This document contains device-specific information for
the dsPIC30F6010A and dsPIC30F6015 devices. The
dsPIC30F devices contain extensive Digital Signal
Processor (DSP) functionality within a
high-performance 16-bit microcontroller (MCU)
architecture. Figure 1-1 shows a device block diagram
for the dsPIC30F6010A device. Figure 1-2 shows a
device block diagram for the dsPIC30F6015 device.

© 2008 Microchip Technology Inc. DS70150D-page 9

dsPIC30F6010A/6015
FIGURE 1-1: dsPIC30F6010A BLOCK DIAGRAM

Y Data Bus
X Data Bus
16 16 16 16 VREF-/RA9
16
VREF+/RA10
Interrupt Data Latch Data Latch
PSV & Table INT3/RA14
Controller Y Data X Data
Data Access 8 INT4/RA15
24 Control Block 16 RAM RAM
(4 Kbytes) (4 Kbytes)
PORTA
Address Address
24 Latch Latch PGD/EMUD/AN0/CN2/RB0
16 16 16 PGC/EMUC/AN1/CN3/RB1
AN2/SS1/CN4/RB2
24 X RAGU
Y AGU AN3/INDX/CN5/RB3
PCU PCH PCL X WAGU
AN4/QEA/CN6/RB4
Program Counter
AN5/QEB/CN7/RB5
Address Latch Stack Loop
Control Control AN6/OCFA/RB6
Program Memory Logic Logic AN7/RB7
(144 Kbytes) AN8/RB8
AN9/RB9
Data EEPROM
AN10/RB10
(4 Kbytes) Effective Address
AN11/RB11
Data Latch 16 AN12/RB12
AN13/RB13
AN14/RB14
ROM Latch 16 AN15/OCFB/CN12/RB15
24 PORTB

IR T2CK/RC1
T4CK/RC3
16 16 EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
16 x 16
OSC2/CLKO/RC15
W Reg Array
Decode
PORTC
Instruction
Decode & 16 16
Control EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
Control Signals DSP
to Various Blocks Divide OC4/RD3
Power-up Engine Unit OC5/CN13/RD4
Timer OC6/CN14/RD5
Timing Oscillator OC7/CN15/RD6
OSC1/CLKI OC8/UPDN/CN16/RD7
Generation Start-up Timer
IC1/RD8
POR/BOR ALU<16> IC2/RD9
Reset IC3/RD10
Watchdog 16 16 IC4/RD11
MCLR IC5/RD12
Timer
IC6/CN19/RD13
Low-Voltage IC7/CN20/RD14
VDD, VSS Detect IC8/CN21/RD15
AVDD, AVSS PORTD

PWM1L/RE0
CAN1, Input Output PWM1H/RE1
CAN2 10-bit ADC Capture Compare I2C™ PWM2L/RE2
Module Module
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SPI1, Motor Control UART1, FLTA/INT1/RE8
Timers QEI
SPI2 PWM UART2 FLTB/INT2/RE9
PORTE

C1RX/RF0
C2RX/RG0
C1TX/RF1
C2TX/RG1
U1RX/RF2
SCL/RG2
U1TX/RF3
SDA/RG3
SCK2/CN8/RG6 U2RX/CN17/RF4
SDI2/CN9/RG7 U2TX/CN18/RF5
SDO2/CN10/RG8 EMUC3/SCK1/INT0/RF6
SDI1/RF7
SS2/CN11/RG9
EMUD3/SDO1/RF8
PORTG PORTF

DS70150D-page 10 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 1-2: dsPIC30F6015 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16 16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table Y Data
Data Access X Data
24 Control Block 8 16 RAM RAM
(4 Kbytes) (4 Kbytes)
Address Address
24 Latch Latch AN0/VREF+/CN2/RB0
16 16 16 AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
24 X RAGU
Y AGU AN3/INDX/CN5/RB3
PCU PCH PCL X WAGU
AN4/QEA/IC7/CN6/RB4
Program Counter
AN5/QEB/IC8/CN7/RB5
Address Latch Stack Loop
Control Control PGC/EMUC/AN6/OCFA/RB6
Program Memory Logic Logic PGD/EMUD/AN7/RB7
(144 Kbytes) AN8/RB8
AN9/RB9
Data EEPROM
AN10/RB10
(4 Kbytes) Effective Address
AN11/RB11
Data Latch 16 AN12/RB12
AN13/RB13
AN14/RB14
ROM Latch 16 AN15/OCFB/CN12/RB15
24 PORTB

IR
EMUD1/SOSCI/T4CK/CN1/RC13
16 16 EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode & 16 16
Control

Control Signals EMUC2/OC1/RD0

DSP Divide EMUD2/OC2/RD1
to Various Blocks Power-up Engine Unit OC3/RD2
Timer OC4/RD3
OSC1/CLKI Timing Oscillator OC5/IC5/CN13/RD4
Generation Start-up Timer OC6/IC6/CN14/RD5
ALU<16> OC7/CN15/RD6
POR/BOR OC8/UPDN/CN16/RD7
Reset IC1/FLTA/INT1/RD8
Watchdog 16 16 IC2/FLTB/INT2/RD9
MCLR
Timer IC3/INT3/RD10
Low-Voltage IC4/INT4/RD11
VDD, VSS Detect
AVDD, AVSS PORTD

Input Output PWM1L/RE0

CAN1 10-bit ADC Capture Compare I2C™ PWM1H/RE1
Module Module PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
SPI1, Motor Control UART1, PWM4H/RE7
Timers QEI
SPI2 PWM UART2
PORTE

SCL/RG2 C1RX/RF0
SDA/RG3 C1TX/RF1
SCK2/CN8/RG6 U1RX/SDI1/RF2
SDI2/CN9/RG7 EMUD3/U1TX/SDO1/RF3
SDO2/CN10/RG8 U2RX/CN17/RF4
SS2/CN11/RG9 U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6

PORTG PORTF

© 2008 Microchip Technology Inc. DS70150D-page 11

dsPIC30F6010A/6015
Table 1-1 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.

TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS

Pin Buffer
Pin Name Description
Type Type
AN0-AN15 I Analog Analog input channels. AN0 and AN1 are also used for device programming
data and clock inputs, respectively.
AVDD P P Positive supply for analog module. This pin must be connected at all times.
AVSS P P Ground reference for analog module.
CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO O — Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak
pull-ups on all inputs.
C1RX I ST CAN1 bus receive pin.
C1TX O — CAN1 bus transmit pin.
C2RX I ST CAN2 bus receive pin.
C2TX O — CAN2 bus transmit pin.
EMUD I/O ST ICD Primary Communication Channel data input/output pin.
EMUC I/O ST ICD Primary Communication Channel clock input/output pin.
EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin.
EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin.
EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin.
EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin.
EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin.
EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin.
IC1-IC8 I ST Capture inputs 1 through 8.
INDX I ST Quadrature Encoder Index Pulse input.
QEA I ST Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
QEB I ST Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
UPDN O CMOS Position Up/Down Counter Direction State.
INT0 I ST External interrupt 0.
INT1 I ST External interrupt 1.
INT2 I ST External interrupt 2.
INT3 I ST External interrupt 3.
INT4 I ST External interrupt 4.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

DS70150D-page 12 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED)
Pin Buffer
Pin Name Description
Type Type
FLTA I ST PWM Fault A input.
FLTB I ST PWM Fault B input.
PWM1L O — PWM 1 Low output.
PWM1H O — PWM 1 High output.
PWM2L O — PWM 2 Low output.
PWM2H O — PWM 2 High output.
PWM3L O — PWM 3 Low output.
PWM3H O — PWM 3 High output.
PWM4L O — PWM 4 Low output.
PWM4H O — PWM 4 High output.
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA I ST Compare Fault A input (for Compare channels 1, 2, 3 and 4).
OCFB I ST Compare Fault B input (for Compare channels 5, 6, 7 and 8).
OC1-OC8 O — Compare outputs 1 through 8.
OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PGD I/O ST In-Circuit Serial Programming™ data input/output pin.
PGC I ST In-Circuit Serial Programming clock input pin.
RA9-RA10 I/O ST PORTA is a bidirectional I/O port.
RA14-RA15 I/O ST
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC1 I/O ST PORTC is a bidirectional I/O port.
RC3 I/O ST
RC13-RC15 I/O ST
RD0-RD15 I/O ST PORTD is a bidirectional I/O port.
RE0-RE9 I/O ST PORTE is a bidirectional I/O port.
RF0-RF8 I/O ST PORTF is a bidirectional I/O port.
RG0-RG3 I/O ST PORTG is a bidirectional I/O port.
RG6-RG9 I/O ST
SCK1 I/O ST Synchronous serial clock input/output for SPI #1.
SDI1 I ST SPI #1 Data In.
SDO1 O — SPI #1 Data Out.
SS1 I ST SPI #1 Slave Synchronization.
SCK2 I/O ST Synchronous serial clock input/output for SPI #2.
SDI2 I ST SPI #2 Data In.
SDO2 O — SPI #2 Data Out.
SS2 I ST SPI #2 Slave Synchronization.
SCL I/O ST Synchronous serial clock input/output for I2C™.
SDA I/O ST Synchronous serial data input/output for I2C.
SOSCO O — 32 kHz low-power oscillator crystal output.
SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
T1CK I ST Timer1 external clock input.
T2CK I ST Timer2 external clock input.
T4CK I ST Timer4 external clock input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

© 2008 Microchip Technology Inc. DS70150D-page 13

dsPIC30F6010A/6015
TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED)
Pin Buffer
Pin Name Description
Type Type
U1RX I ST UART1 Receive.
U1TX O — UART1 Transmit.
U1ARX I ST UART1 Alternate Receive.
U1ATX O — UART1 Alternate Transmit.
U2RX I ST UART2 Receive.
U2TX O — UART2 Transmit.
VDD P — Positive supply for logic and I/O pins.
VSS P — Ground reference for logic and I/O pins.
VREF+ I Analog Analog Voltage Reference (High) input.
VREF- I Analog Analog Voltage Reference (Low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power

DS70150D-page 14 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
2.0 CPU ARCHITECTURE • Linear indirect access of 32K word pages within
program space is also possible using any working
OVERVIEW register, via table read and write instructions. Table
Note: This data sheet summarizes features of read and write instructions can be used to access
this group of dsPIC30F devices and is not all 24 bits of an instruction word.
intended to be a complete reference Overhead-free circular buffers (Modulo Addressing) are
source. For more information on the supported in both X and Y address spaces. This is
peripherals, register descriptions and primarily intended to remove the loop overhead for DSP
general device functionality, refer to the algorithms.
“dsPIC30F Family Reference Manual”
The X AGU also supports Bit-Reversed Addressing on
(DS70046). For more information on the
destination Effective Addresses, to greatly simplify input
device instruction set and programming,
or output data reordering for radix-2 FFT algorithms.
refer to the “dsPIC30F/33F Programmers
Refer to Section 4.0 “Address Generator Units” for
Reference Manual” (DS70157).
details on Modulo and Bit-Reversed Addressing.
This chapter summarizes the CPU and peripheral
The core supports Inherent (no operand), Relative,
functions of the dsPIC30F6010A/6015.
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
2.1 Core Overview modes. Instructions are associated with predefined
The core has a 24-bit instruction word. The Program addressing modes, depending upon their functional
Counter (PC) is 23 bits wide with the Least Significant requirements.
bit (LSb) always clear (see Section 3.1 “Program For most instructions, the core is capable of executing
Address Space”), and the Most Significant bit (MSb) a data (or program data) memory read, a working reg-
is ignored during normal program execution, except for ister (data) read, a data memory write and a program
certain specialized instructions. Thus, the PC can (instruction) memory read per instruction cycle. As a
address up to 4M instruction words of user program result, 3-operand instructions are supported, allowing
space. An instruction prefetch mechanism is used to C = A + B operations to be executed in a single cycle.
help maintain throughput. Program loop constructs, A DSP engine has been included to significantly
free from loop count management overhead, are enhance the core arithmetic capability and throughput.
supported using the DO and REPEAT instructions, both It features a high-speed 17-bit by 17-bit multiplier, a
of which are interruptible at any point. 40-bit ALU, two 40-bit saturating accumulators and a
The working register array consists of 16x16-bit 40-bit bidirectional barrel shifter. Data in the accumulator
registers, each of which can act as data, address or or any working register can be shifted up to 16 bits right
offset registers. One working register (W15) operates or 16 bits left in a single cycle. The DSP instructions
as a Software Stack Pointer for interrupts and calls. operate seamlessly with all other instructions and have
The data space is 64 Kbytes (32K words) and is split into been designed for optimal real-time performance. The
two blocks, referred to as X and Y data memory. Each MAC class of instructions can concurrently fetch two data
block has its own independent Address Generation Unit operands from memory, while multiplying two W
(AGU). Most instructions operate solely through the X registers. To enable this concurrent fetching of data
memory AGU, which provides the appearance of a operands, the data space has been split for these
single unified data space. The Multiply-Accumulate instructions and linear for all others. This has been
(MAC) class of dual source DSP instructions operate achieved in a transparent and flexible manner, by
through both the X and Y AGUs, splitting the data dedicating certain working registers to each address
address space into two parts (see Section 3.2 “Data space for the MAC class of instructions.
Address Space”). The X and Y data space boundary is The core does not support a multi-stage instruction
device-specific and cannot be altered by the user. Each pipeline. However, a single stage instruction prefetch
data word consists of 2 bytes, and most instructions can mechanism is used, which accesses and partially
address data either as words or bytes. decodes instructions a cycle ahead of execution, in order
There are two methods of accessing data stored in to maximize available execution time. Most instructions
program memory: execute in a single cycle, with certain exceptions.

• The upper 32 Kbytes of data space memory can be The core features a vectored exception processing
mapped into the lower half (user space) of program structure for traps and interrupts, with 62 independent
space at any 16K program word boundary, defined by vectors. The exceptions consist of up to 8 traps (of which
the 8-bit Program Space Visibility Page (PSVPAG) 4 are reserved) and 54 interrupts. Each interrupt is
register. This lets any instruction access program prioritized based on a user-assigned priority between 1
space as if it were data space, with a limitation that the and 7 (1 being the lowest priority and 7 being the highest)
access requires an additional cycle. Moreover, only in conjunction with a predetermined ‘natural order’.
the lower 16 bits of each instruction word can be Traps have fixed priorities, ranging from 8 to 15.
accessed using this method.

© 2008 Microchip Technology Inc. DS70150D-page 15

dsPIC30F6010A/6015
2.2 Programmer’s Model 2.2.1 SOFTWARE STACK POINTER/
FRAME POINTER
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through The dsPIC® DSC devices contain a software stack.
W15), 2x40-bit accumulators (AccA and AccB), W15 is the dedicated Software Stack Pointer (SP), and
STATUS register (SR), Data Table Page register will be automatically modified by exception processing
(TBLPAG), Program Space Visibility Page register and subroutine calls and returns. However, W15 can be
(PSVPAG), DO and REPEAT registers (DOSTART, referenced by any instruction in the same manner as all
DOEND, DCOUNT and RCOUNT), and Program other W registers. This simplifies the reading, writing
Counter (PC). The working registers can act as data, and manipulation of the Stack Pointer (e.g., creating
address or offset registers. All registers are memory stack frames).
mapped. W0 acts as the W register for file register Note: In order to protect against misaligned
addressing. stack accesses, W15<0> is always clear.
Some of these registers have a shadow register W15 is initialized to 0x0800 during a Reset. The user
associated with each of them, as shown in Figure 2-1. may reprogram the SP during initialization to any
The shadow register is used as a temporary holding location within data space.
register and can transfer its contents to or from its host
register upon the occurrence of an event. None of the W14 has been dedicated as a Stack Frame Pointer as
shadow registers are accessible directly. The following defined by the LNK and ULNK instructions. However,
rules apply for transfer of registers into and out of W14 can be referenced by any instruction in the same
shadows. manner as all other W registers.

• PUSH.S and POP.S 2.2.2 STATUS REGISTER

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred. The dsPIC DSC core has a 16-bit STATUS register
(SR), the LSB of which is referred to as the SR Low
• DO instruction
Byte (SRL) and the MSB as the SR High Byte (SRH).
DOSTART, DOEND, DCOUNT shadows are
See Figure 2-1 for SR layout.
pushed on loop start and popped on loop end.
SRL contains all the MCU ALU operation status flags
When a byte operation is performed on a working
(including the Z bit), as well as the CPU Interrupt
register, only the Least Significant Byte of the target
Priority Level Status bits, IPL<2:0>, and the Repeat
register is affected. However, a benefit of memory
Active Status bit, RA. During exception processing,
mapped working registers is that both the Least and
SRL is concatenated with the MSB of the PC to form a
Most Significant Bytes can be manipulated through
complete word value which is then stacked.
byte-wide data memory space accesses.
The upper byte of the SR register contains the DSP
adder/subtractor Status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.

DS70150D-page 16 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 2-1: dsPIC30F6010A/6015 PROGRAMMER’S MODEL

D15 D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer

SPLIM Stack Pointer Limit Register

AD39 AD31 AD15 AD0

DSP AccA
Accumulators AccB

PC22 PC0
0 Program Counter

7 0
TABPAG
TBLPAG Data Table Page Address

7 0
PSVPAG Program Space Visibility Page Address

15 0
RCOUNT REPEAT Loop Counter

15 0
DCOUNT DO Loop Counter

22 0
DOSTART DO Loop Start Address

22
DOEND DO Loop End Address

15 0
CORCON Core Configuration Register

OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register

SRH SRL

© 2008 Microchip Technology Inc. DS70150D-page 17

dsPIC30F6010A/6015
2.3 Divide Support The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
The dsPIC DSC devices feature a 16/16-bit signed series of discrete divide instructions) will not function
fractional divide operation, as well as 32/16-bit and correctly because the instruction flow depends on
16/16-bit signed and unsigned integer divide RCOUNT. The divide instruction does not automatically
operations, in the form of single instruction iterative set up the RCOUNT value, and it must, therefore, be
divides. The following instructions and data sizes are explicitly and correctly specified in the REPEAT
supported: instruction, as shown in Table 2-1 (REPEAT will execute
• DIVF – 16/16 signed fractional divide the target instruction {operand value + 1} times). The
• DIV.sd – 32/16 signed divide REPEAT loop count must be set up for 18 iterations of
• DIV.ud – 32/16 unsigned divide the DIV/DIVF instruction. Thus, a complete divide
• DIV.s – 16/16 signed divide operation requires 19 cycles.
• DIV.u – 16/16 unsigned divide
Note: The divide flow is interruptible. However,
the user needs to save the context as
appropriate.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function
DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1
DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.s Signed divide: Wm/Wn → W0; Rem → W1
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1

2.4 DSP Engine A block diagram of the DSP engine is shown in

Figure 2-2.
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit TABLE 2-2: DSP INSTRUCTION
adder/subtractor (with two target accumulators, round SUMMARY
and saturation logic).
Instruction Algebraic Operation
The dsPIC30F devices have a single instruction flow
CLR A=0
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between ED A = (x – y)2
the DSP and MCU instructions. For example, the EDAC A = A + (x – y)2
instruction set has both DSP and MCU multiply MAC A = A + (x * y)
instructions which use the same hardware multiplier.
MOVSAC No change in A
The DSP engine also has the capability to perform
MPY A=x*y
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD, MPY.N A=–x*y
SUB and NEG. MSC A=A–x*y
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
• Fractional or Integer DSP Multiply (IF).
• Signed or Unsigned DSP Multiply (US).
• Conventional or Convergent Rounding (RND).
• Automatic Saturation On/Off for AccA (SATA).
• Automatic Saturation On/Off for AccB (SATB).
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW).
• Accumulator Saturation mode Selection
(ACCSAT).
Note: For CORCON layout, see Table 3-3.

DS70150D-page 18 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder

Negate

40
40 40

Barrel
16
Shifter

X Data Bus
40

Sign-Extend
Y Data Bus

32 16
Zero Backfill
32
33

17-bit
Multiplier/Scaler

16 16

To/From W Array

© 2008 Microchip Technology Inc. DS70150D-page 19

dsPIC30F6010A/6015
2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtractor, Overflow and
The 17x17-bit multiplier is capable of signed or Saturation
unsigned operations and can multiplex its output using The adder/subtractor is a 40-bit adder with an optional
a scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement
integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the
into the 17th bit of the multiplier input value. Signed carry/borrow input is active-high and the other input is
operands are sign-extended into the 17th bit of the true data (not complemented), whereas in the case of
multiplier input value. The output of the 17x17-bit subtraction, the carry/borrow input is active-low and the
multiplier/scaler is a 33-bit value, which is other input is complemented. The adder/subtractor
sign-extended to 40 bits. Integer data is inherently generates Overflow Status bits, SA/SB and OA/OB,
represented as a signed two’s complement value, which are latched and reflected in the STATUS register.
where the MSB is defined as a sign bit. Generally
• Overflow from bit 39: this is a catastrophic
speaking, the range of an N-bit two’s complement
overflow in which the sign of the accumulator is
integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
destroyed.
range is -32768 (0x8000) to 32767 (0x7FFF), including
0. For a 32-bit integer, the data range is -2,147,483,648 • Overflow into guard bits 32 through 39: this is a
(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF). recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s The adder has an additional saturation block which
complement fraction, where the MSB is defined as a controls accumulator data saturation, if selected. It
sign bit and the radix point is implied to lie just after the uses the result of the adder, the Overflow Status bits
sign bit (QX format). The range of an N-bit two’s described above, and the SATA/B (CORCON<7:6>)
complement fraction with this implied radix point is -1.0 and ACCSAT (CORCON<4>) mode control bits to
to (1-21-N). For a 16-bit fraction, the Q15 data range is determine when and to what value to saturate.
-1.0 (0x8000) to 0.999969482 (0x7FFF), including 0 Six STATUS register bits have been provided to
and has a precision of 3.01518x10-5. In Fractional support saturation and overflow. They are:
mode, a 16x16 multiply operation generates a 1.31 1. OA:
product, which has a precision of 4.65661x10-10. AccA overflowed into guard bits
The same multiplier is used to support the MCU 2. OB:
multiply instructions, which include integer 16-bit AccB overflowed into guard bits
signed, unsigned and mixed sign multiplies. 3. SA:
The MUL instruction may be directed to use byte or AccA saturated (bit 31 overflow and saturation)
word-sized operands. Byte operands will direct a 16-bit or
result, and word operands will direct a 32-bit result to AccA overflowed into guard bits and saturated
the specified register(s) in the W array. (bit 39 overflow and saturation)
4. SB:
2.4.2 DATA ACCUMULATORS AND AccB saturated (bit 31 overflow and saturation)
ADDER/SUBTRACTOR or
The data accumulator consists of a 40-bit AccB overflowed into guard bits and saturated
adder/subtractor with automatic sign extension logic. It (bit 39 overflow and saturation)
can select one of two accumulators (A or B) as its 5. OAB:
pre-accumulation source and post-accumulation Logical OR of OA and OB
destination. For the ADD and LAC instructions, the data 6. SAB:
to be accumulated or loaded can be optionally scaled Logical OR of SA and SB
via the barrel shifter, prior to accumulation.
The OA and OB bits are modified each time data passes
through the adder/subtractor. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic
warning trap when set and the corresponding overflow
trap flag enable bit (OVATE, OVBTE) in the INTCON1
register (refer to Section 5.0 “Interrupts”) is set. This
allows the user to take immediate action, for example, to
correct system gain.

DS70150D-page 20 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
The SA and SB bits are modified each time data passes 2.4.2.2 Accumulator ‘Write-Back’
through the adder/subtractor, but can only be cleared by
The MAC class of instructions (with the exception of
the user. When set, they indicate that the accumulator
MPY, MPY.N, ED and EDAC) can optionally write a
has overflowed its maximum range (bit 31 for 32-bit
rounded version of the high word (bits 31 through 16)
saturation, or bit 39 for 40-bit saturation) and will be
of the accumulator that is not targeted by the instruction
saturated if saturation is enabled. When saturation is not
into data space memory. The write is performed across
enabled, SA and SB default to bit 39 overflow and thus
the X bus into combined X and Y address space. The
indicate that a catastrophic overflow has occurred. If the
following addressing modes are supported:
COVTE bit in the INTCON1 register is set, SA and SB
bits will generate an arithmetic warning trap when 1. W13, Register Direct:
saturation is disabled. The rounded contents of the non-target
accumulator are written into W13 as a 1.15
The Overflow and Saturation Status bits can optionally
fraction.
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA 2. [W13]+ = 2, Register Indirect with Post-Increment:
and SB (in bit SAB). This allows programmers to check The rounded contents of the non-target
one bit in the STATUS register to determine if either accumulator are written into the address pointed
accumulator has overflowed, or one bit to determine if to by W13 as a 1.15 fraction. W13 is then
either accumulator has saturated. This would be useful incremented by 2 (for a word write).
for complex number arithmetic which typically uses
2.4.2.3 Round Logic
both the accumulators.
The round logic is a combinational block, which
The device supports three Saturation and Overflow
performs a conventional (biased) or convergent
modes.
(unbiased) round function during an accumulator write
1. Bit 39 Overflow and Saturation: (store). The Round mode is determined by the state of
When bit 39 overflow and saturation occurs, the the RND bit in the CORCON register. It generates a
saturation logic loads the maximally positive 9.31 16-bit, 1.15 data value which is passed to the data
(0x7FFFFFFFFF) or maximally negative 9.31 space write saturation logic. If rounding is not indicated
value (0x8000000000) into the target by the instruction, a truncated 1.15 data value is stored
accumulator. The SA or SB bit is set and and the least significant word is simply discarded.
remains set until cleared by the user. This is
Conventional rounding takes bit 15 of the accumulator,
referred to as ‘super saturation’ and provides
zero-extends it and adds it to the ACCxH word (bits 16
protection against erroneous data or unexpected
through 31 of the accumulator). If the ACCxL word (bits
algorithm problems (e.g., gain calculations).
0 through 15 of the accumulator) is between 0x8000
2. Bit 31 Overflow and Saturation: and 0xFFFF (0x8000 included), ACCxH is
When bit 31 overflow and saturation occurs, the incremented. If ACCxL is between 0x0000 and 0x7FFF,
saturation logic then loads the maximally ACCxH is left unchanged. A consequence of this
positive 1.31 value (0x007FFFFFFF) or algorithm is that over a succession of random rounding
maximally negative 1.31 value (0x0080000000) operations, the value will tend to be biased slightly
into the target accumulator. The SA or SB bit is positive.
set and remains set until cleared by the user.
When this Saturation mode is in effect, the guard Convergent (or unbiased) rounding operates in the
bits are not used so the OA, OB or OAB bits are same manner as conventional rounding, except when
never set. ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
3. Bit 39 Catastrophic Overflow
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
The bit 39 Overflow Status bit from the adder is
modified. Assuming that bit 16 is effectively random in
used to set the SA or SB bit, which remain set
nature, this scheme will remove any rounding bias that
until cleared by the user. No saturation operation
may accumulate.
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in The SAC and SAC.R instructions store either a
the INTCON1 register is set, a catastrophic truncated (SAC) or rounded (SAC.R) version of the
overflow can initiate a trap exception. contents of the target accumulator to data memory, via
the X bus (subject to data saturation, see
Section 2.4.2.4 “Data Space Write Saturation”).
Note that for the MAC class of instructions, the
accumulator write-back operation will function in the
same manner, addressing combined MCU (X and Y)
data space though the X bus. For this class of
instructions, the data is always subject to rounding.

© 2008 Microchip Technology Inc. DS70150D-page 21

dsPIC30F6010A/6015
2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER
In addition to adder/subtractor saturation, writes to data The barrel shifter is capable of performing up to 16-bit
space may also be saturated, but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts
contents of the source accumulator. The data space in a single cycle. The source can be either of the two
write saturation logic block accepts a 16-bit, 1.15 DSP accumulators or the X bus (to support multi-bit
fractional value from the round logic block as its input, shifts of register or memory data).
together with overflow status from the original source The shifter requires a signed binary value to determine
(accumulator) and the 16-bit round adder. These are both the magnitude (number of bits) and direction of the
combined and used to select the appropriate 1.15 shift operation. A positive value will shift the operand
fractional value as output to write to data space right. A negative value will shift the operand left. A
memory. value of ‘0’ will not modify the operand.
If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a
(after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result
adjusted accordingly. For input data greater than for MCU shift operations. Data from the X bus is
0x007FFF, data written to memory is forced to the presented to the barrel shifter between bit positions 16
maximum positive 1.15 value, 0x7FFF. For input data to 31 for right shifts, and bit positions 0 to 15 for left
less than 0xFF8000, data written to memory is forced shifts.
to the maximum negative 1.15 value, 0x8000. The MSb
of the source (bit 39) is used to determine the sign of
the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.

DS70150D-page 22 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
3.0 MEMORY ORGANIZATION FIGURE 3-1: PROGRAM SPACE
MEMORY MAP FOR
Note: This data sheet summarizes features of dsPIC30F6010A/6015
this group of dsPIC30F devices and is not
intended to be a complete reference Reset – GOTO Instruction 000000
source. For more information on the CPU, Reset – Target Address 000002
000004
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the Vector Tables
Interrupt Vector Table
device instruction set and programming,
refer to the “dsPIC30F/33F Programmers
Reference Manual” (DS70157).

3.1 Program Address Space

00007E
Reserved 000080
The program address space is 4M instruction words. It

User Memory
Alternate Vector Table 000084
is addressable by the 23-bit PC, table instruction 0000FE

Space
Effective Address (EA), or data space EA, when User Flash 000100
Program Memory
program space is mapped into data space, as defined (48K instructions)
by Table 3-1. Note that the program space address is 017FFE
incremented by two between successive program 018000
Reserved
words, in order to provide compatibility with data space (Read ‘0’s)
addressing. 7FEFFE
7FF000
User program space access is restricted to the lower Data EEPROM
4M instruction word address range (0x000000 to (4 Kbytes)
0x7FFFFE), for all accesses other than TBLRD/TBLWT, 7FFFFE
800000
which use TBLPAG<7> to determine user or
configuration space access. In Table 3-1, read/write
instructions, bit 23 allows access to the device ID, the
user ID and the Configuration bits. Otherwise, bit 23 is
always clear.

Reserved
Configuration Memory

8005BE
Space

8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
F7FFFE
Device Configuration F80000
Registers F8000E
F80010

Reserved

FEFFFE
DEVID (2) FF0000
FFFFFE

© 2008 Microchip Technology Inc. DS70150D-page 23

dsPIC30F6010A/6015
TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
TBLRD/TBLWT User TBLPAG<7:0> Data EA <15:0>
(TBLPAG<7> = 0)
TBLRD/TBLWT Configuration TBLPAG<7:0> Data EA <15:0>
(TBLPAG<7> = 1)
Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0>

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits
Using
Program 0 Program Counter 0
Counter

Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits

EA

Using 1/0 TBLPAG Reg

Table
Instruction
8 bits 16 bits

User/ Byte
Configuration 24-bit EA
Space Select
Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

DS70150D-page 24 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
3.1.1 DATA ACCESS FROM PROGRAM A set of table instructions are provided to move byte or
MEMORY USING TABLE word-sized data to and from program space.
INSTRUCTIONS 1. TBLRDL: Table Read Low
This architecture fetches 24-bit wide program memory. Word: Read the least significant word of the
Consequently, instructions are always aligned. program address;
However, as the architecture is modified Harvard, data P<15:0> maps to D<15:0>.
can also be present in program space. Byte: Read one of the Least Significant Bytes of
the program address;
There are two methods by which program space can P<7:0> maps to the destination byte when byte
be accessed; via special table instructions, or through select = 0;
the remapping of a 16K word program space page into P<15:8> maps to the destination byte when byte
the upper half of data space (see Section 3.1.2 “Data select = 1.
Access From Program Memory Using Program
2. TBLWTL: Table Write Low (refer to Section 6.0
Space Visibility”). The TBLRDL and TBLWTL
“Flash Program Memory” for details on Flash
instructions offer a direct method of reading or writing
Programming).
the least significant word of any address within
program space, without going through data space. The 3. TBLRDH: Table Read High
TBLRDH and TBLWTH instructions are the only method Word: Read the most significant word of the
whereby the upper 8 bits of a program space word can program address;
be accessed as data. P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
The PC is incremented by two for each successive Byte: Read one of the Most Significant Bytes of
24-bit program word. This allows program memory the program address;
addresses to directly map to data space addresses. P<23:16> maps to the destination byte when
Program memory can thus be regarded as two 16-bit byte select = 0;
word-wide address spaces, residing side by side, each The destination byte will always be = 0 when
with the same address range. TBLRDL and TBLWTL byte select = 1.
access the space which contains the lsw, and TBLRDH
4. TBLWTH: Table Write High (refer to Section 6.0
and TBLWTH access the space which contains the
“Flash Program Memory” for details on Flash
MSB.
Programming).
Figure 3-2 shows how the EA is created for table
operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000

TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
TBLRDL.B (Wn<0> = 1)
(Read as ‘0’).

© 2008 Microchip Technology Inc. DS70150D-page 25

dsPIC30F6010A/6015
FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)

TBLRDH.W

PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000

TBLRDH.B (Wn<0> = 0)

Program Memory
‘Phantom’ Byte
(Read as ‘0’) TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each
MEMORY USING PROGRAM SPACE program memory word, the Least Significant 15 bits of
VISIBILITY data space addresses directly map to the Least
Significant 15 bits in the corresponding program space
The upper 32 Kbytes of data space may optionally be addresses. The remaining bits are provided by the
mapped into any 16K word program space page. This Program Space Visibility Page register, PSVPAG<7:0>,
provides transparent access of stored constant data as shown in Figure 3-5.
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the MSb of the data space EA is set and program For instructions that use PSV which are executed
space visibility is enabled, by setting the PSV bit in the outside a REPEAT loop:
Core Control register (CORCON). The functions of • The following instructions will require one
CORCON are discussed in Section 2.4 “DSP instruction cycle in addition to the specified
Engine”. execution time:
Data accesses to this area add an additional cycle to - MAC class of instructions with data operand
the instruction being executed, since two program prefetch
memory fetches are required. - MOV instructions
Note that the upper half of addressable data space is - MOV.D instructions
always part of the X data space. Therefore, when a • All other instructions will require two instruction
DSP operation uses program space mapping to access cycles in addition to the specified execution time
this memory region, Y data space should typically of the instruction.
contain state (variable) data for DSP operations,
whereas X data space should typically contain For instructions that use PSV which are executed
coefficient (constant) data. inside a REPEAT loop:
Although each data space address, 0x8000 and higher, • The following instances will require two instruction
maps directly into a corresponding program memory cycles in addition to the specified execution time
address (see Figure 3-5), only the lower 16 bits of the of the instruction:
24-bit program word are used to contain the data. The - Execution in the first iteration
upper 8 bits should be programmed to force an illegal - Execution in the last iteration
instruction to maintain machine robustness. Refer - Execution prior to exiting the loop due to an
to the “dsPIC30F/33F Programmers Reference interrupt
Manual” (DS70157) for details on instruction encoding.
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.

DS70150D-page 26 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space Program Space

0x0000 0x000100

15 PSVPAG(1)
EA<15> = 0 0x00
8

Data 16
Space 0x8000
EA 15 23 15 0
Address
EA<15> = 1 0x001200
15 Concatenation 23

Upper half of Data

Space is mapped
into Program Space
0xFFFF 0x017FFE

BSET CORCON,#2 ; PSV bit set

MOV #0x00, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x9200, W0 ; Access program memory location
; using a data space access Data Read

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).

3.2 Data Address Space When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
The core has two data spaces. The data spaces can be 64 Kbyte data address space (including all Y
considered either separate (for some DSP addresses). When executing one of the MAC class of
instructions), or as one unified linear address range (for instructions, the X block consists of the 64 Kbyte data
MCU instructions). The data spaces are accessed address space excluding the Y address block (for data
using two Address Generation Units (AGUs) and reads only). In other words, all other instructions regard
separate data paths. the entire data memory as one composite address
space. The MAC class instructions extract the Y
3.2.1 DATA SPACE MEMORY MAP address space from data space and address it using
The data space memory is split into two blocks, X and EAs sourced from W10 and W11. The remaining X data
Y data space. A key element of this architecture is that space is addressed using W8 and W9. Both address
Y space is a subset of X space, and is fully contained spaces are concurrently accessed only with the MAC
within X space. In order to provide an apparent Linear class instructions.
Addressing space, X and Y spaces have contiguous A data space memory map is shown in Figure 3-6.
addresses.
Figure 3-7 shows a graphical summary of how X and Y
data spaces are accessed for MCU and DSP
instructions.

© 2008 Microchip Technology Inc. DS70150D-page 27

dsPIC30F6010A/6015
FIGURE 3-6: dsPIC30F6010A/6015 DATA SPACE MEMORY MAP

Most Significant Byte Least Significant Byte

Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
8 Kbyte
Near
X Data RAM (X)
Data
Space
8 Kbyte 0x17FF 0x17FE
SRAM Space 0x1801 0x1800
0x1FFF 0x1FFE
Y Data RAM (Y)

0x27FF 0x27FE
0x2801 0x2800

0x8001 0x8000

X Data
Unimplemented (X)

Optionally
Mapped
into Program
Memory

0xFFFF 0xFFFE

DS70150D-page 28 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE SFR SPACE

X SPACE
UNUSED

(Y SPACE) Y SPACE UNUSED

X SPACE

X SPACE
UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only

MAC Class Ops (Write)

Indirect EA using any W Indirect EA using W10, W11 Indirect EA using W8, W9

© 2008 Microchip Technology Inc. DS70150D-page 29

dsPIC30F6010A/6015
3.2.2 DATA SPACES 3.2.3 DATA SPACE WIDTH
The X data space is used by all instructions and The core data width is 16 bits. All internal registers are
supports all addressing modes. There are separate organized as 16-bit wide words. Data space memory is
read and write data buses. The X read data bus is the organized in byte addressable, 16-bit wide blocks.
return data path for all instructions that view data space
as combined X and Y address space. It is also the X 3.2.4 DATA ALIGNMENT
address space data path for the dual operand read To help maintain backward compatibility with
instructions (MAC class). The X write data bus is the PIC® MCU devices and improve data space memory
only write path to data space for all instructions. usage efficiency, the dsPIC30F instruction set supports
The X data space also supports Modulo Addressing for both word and byte operations. Data is aligned in data
all instructions, subject to addressing mode memory and registers as words, but all data space EAs
restrictions. Bit-Reversed Addressing is only supported resolve to bytes. Data byte reads will read the complete
for writes to X data space. word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
The Y data space is used in concert with the X data
placed onto the LSB of the X data path (no byte
space by the MAC class of instructions (CLR, ED,
accesses are possible from the Y data path as the MAC
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
class of instruction can only fetch words). That is, data
provide two concurrent data read paths. No writes
memory and registers are organized as two parallel
occur across the Y bus. This class of instructions
byte wide entities with shared (word) address decode,
dedicates two W register pointers, W10 and W11, to
but separate write lines. Data byte writes only write to
always address Y data space, independent of X data
the corresponding side of the array or register which
space, whereas W8 and W9 always address X data
matches the byte address.
space. Note that during accumulator write-back, the
data address space is considered a combination of X As a consequence of this byte accessibility, all Effective
and Y data spaces, so the write occurs across the X Address calculations (including those generated by the
bus. Consequently, the write can be to any address in DSP operations, which are restricted to word-sized
the entire data space. data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
The Y data space can only be used for the data
Post-Modified Register Indirect Addressing mode,
prefetch operation associated with the MAC class of
[Ws++], will result in a value of Ws + 1 for byte
instructions. It also supports Modulo Addressing for
operations and Ws + 2 for word operations.
automated circular buffers. Of course, all other
instructions can access the Y data address space All word accesses must be aligned to an even address.
through the X data path, as part of the composite linear Misaligned word data fetches are not supported, so
space. care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
The boundary between the X and Y data spaces is
a misaligned read or write be attempted, an address
defined as shown in Figure 3-6 and is not user
error trap will be generated. If the error occurred on a
programmable. Should an EA point to data outside its
read, the instruction underway is completed, whereas if
own assigned address space, or to a location outside
it occurred on a write, the instruction will be executed
physical memory, an all-zero word/byte will be
but the write will not occur. In either case, a trap will
returned. For example, although Y address space is
then be executed, allowing the system and/or user to
visible by all non-MAC instructions using any
examine the machine state prior to execution of the
addressing mode, an attempt by a MAC instruction to
address Fault.
fetch data from that space, using W8 or W9 (X space
pointers), will return 0x0000.
FIGURE 3-8: DATA ALIGNMENT
TABLE 3-2: EFFECT OF INVALID MSB LSB
MEMORY ACCESSES 15 87 0
0001 Byte 1 Byte 0 0000
Attempted Operation Data Returned
EA = an unimplemented address 0x0000 0003 Byte 3 Byte 2 0002
W8 or W9 used to access Y data 0x0000 Byte 5 Byte 4 0004
0005
space in a MAC instruction
W10 or W11 used to access X 0x0000
data space in a MAC instruction

All Effective Addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.

DS70150D-page 30 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
All byte loads into any W register are loaded into the Similarly, a Stack Pointer underflow (stack error) trap is
LSB. The MSB is not modified. generated when the Stack Pointer address is found to
A sign-extend (SE) instruction is provided to allow be less than 0x0800, thus preventing the stack from
users to translate 8-bit signed data to 16-bit signed interfering with the Special Function Register (SFR)
values. Alternatively, for 16-bit unsigned data, users space.
can clear the MSB of any W register by executing a A write to the SPLIM register should not be immediately
zero-extend (ZE) instruction on the appropriate followed by an indirect read operation using W15.
address.
Although most instructions are capable of operating on FIGURE 3-9: CALL STACK FRAME
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate 0x0000 15 0
only on words.

Stack Grows Towards

3.2.5 NEAR DATA SPACE

Higher Address
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is PC<15:0> W15 (before CALL)
directly addressable via a 13-bit absolute address field
000000000 PC<22:16>
within all memory direct instructions. The remaining X
<Free Word> W15 (after CALL)
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which POP: [--W15]
PUSH: [W15++]
support memory direct addressing with a 16-bit
address field.

3.2.6 SOFTWARE STACK 3.2.7 DATA RAM PROTECTION FEATURE

The dsPIC DSC device contains a software stack. W15 The dsPIC30F6010A/6015 devices support Data RAM
is used as the Stack Pointer. protection features which enable segments of RAM to
be protected when used in conjunction with Boot and
The Stack Pointer always points to the first available
Secure Code Segment Security. BSRAM (Secure RAM
free word and grows from lower addresses towards
segment for BS) is accessible only from the Boot
higher addresses. It pre-decrements for stack pops and
Segment Flash code when enabled. SSRAM (Secure
post-increments for stack pushes, as shown in
RAM segment for RAM) is accessible only from the
Figure 3-9. Note that for a PC push during any CALL
Secure Segment Flash code when enabled.
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear. See Table 3-3 for an overview of the BSRAM and
SSRAM SFRs.
Note: A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
There is a Stack Pointer Limit register (SPLIM)
associated with the Stack Pointer. SPLIM is
uninitialized at Reset. As is the case for the Stack
Pointer, SPLIM<0> is forced to ‘0’, because all stack
operations must be word-aligned. Whenever an
Effective Address (EA) is generated using W15 as a
source or destination pointer, the address thus
generated is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal and a push operation is performed, a
stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for
example, if it is desirable to cause a stack error trap
when the stack grows beyond address 0x2000 in RAM,
initialize the SPLIM with the value, 0x1FFE.

© 2008 Microchip Technology Inc. DS70150D-page 31

 TABLE 3-3: CORE REGISTER MAP(1)
DS70150D-page 32

dsPIC30F6010A/6015
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)

W0 0000 W0 / WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000
TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000
© 2008 Microchip Technology Inc.

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
 TABLE 3-3: CORE REGISTER MAP(1) (CONTINUED)
© 2008 Microchip Technology Inc.

Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000
BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 0000 0000 0000
SSRAM 0752 — — — — — — — — — — — — — IW_SSR IR_SSR RL_SSR 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 33
dsPIC30F6010A/6015
NOTES:

DS70150D-page 34 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
Note: This data sheet summarizes features of
(f) to directly address data present in the first
this group of dsPIC30F devices and is not
8192 bytes of data memory (near data space). Most file
intended to be a complete reference
register instructions employ a working register W0,
source. For more information on the CPU,
which is denoted as WREG in these instructions. The
peripherals, register descriptions and
destination is typically either the same file register, or
general device functionality, refer to the
WREG (with the exception of the MUL instruction),
“dsPIC30F Family Reference Manual”
which writes the result to a register or register pair. The
(DS70046). For more information on the
MOV instruction allows additional flexibility and can
device instruction set and programming,
access the entire data space during file register
refer to the “dsPIC30F/33F Programmers
operation.
Reference Manual” (DS70157).
The dsPIC DSC core contains two independent 4.1.2 MCU INSTRUCTIONS
Address Generator Units (AGU): the X AGU and Y The three-operand MCU instructions are of the form:
AGU. The Y AGU supports word-sized data reads for
Operand 3 = Operand 1 <function> Operand 2
the DSP MAC class of instructions only. The dsPIC DSC
AGUs support three types of data addressing: where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
• Linear Addressing
referred to as Wb. Operand 2 can be a W register,
• Modulo (Circular) Addressing fetched from data memory, or a 5-bit literal. The result
• Bit-Reversed Addressing location can be either a W register or an address
Linear and Modulo Data Addressing modes can be location. The following addressing modes are
applied to data space or program space. Bit-Reversed supported by MCU instructions:
Addressing mode is only applicable to data space • Register Direct
addresses. • Register Indirect
• Register Indirect Post-Modified
4.1 Instruction Addressing Modes
• Register Indirect Pre-Modified
The addressing modes in Table 4-1 form the basis of • 5-bit or 10-bit Literal
the addressing modes optimized to support the specific
features of individual instructions. The addressing Note: Not all instructions support all the
modes provided in the MAC class of instructions are addressing modes given above. Individual
somewhat different from those in the other instruction instructions may support different subsets
types. of these addressing modes.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

© 2008 Microchip Technology Inc. DS70150D-page 35

dsPIC30F6010A/6015
4.1.3 MOVE AND ACCUMULATOR In summary, the following addressing modes are
INSTRUCTIONS supported by the MAC class of instructions:
Move instructions and the DSP Accumulator class of • Register Indirect
instructions provide a greater degree of addressing • Register Indirect Post-Modified by 2
flexibility than other instructions. In addition to the • Register Indirect Post-Modified by 4
addressing modes supported by most MCU • Register Indirect Post-Modified by 6
instructions, Move and Accumulator instructions also
• Register Indirect with Register Offset (Indexed)
support Register Indirect with Register Offset Address-
ing mode, also referred to as Register Indexed mode.
4.1.5 OTHER INSTRUCTIONS
Note: For the MOV instructions, the addressing Besides the various addressing modes outlined above,
mode specified in the instruction can differ some instructions use literal constants of various sizes.
for the source and destination EA. For example, BRA (branch) instructions use 16-bit
However, the 4-bit Wb (Register Offset) signed literals to specify the branch destination directly,
field is shared between both source and whereas the DISI instruction uses a 14-bit unsigned
destination (but typically only used by literal field. In some instructions, such as ADD Acc, the
one). source of an operand or result is implied by the opcode
In summary, the following addressing modes are itself. Certain operations, such as NOP, do not have any
supported by Move and Accumulator instructions: operands.
• Register Direct
• Register Indirect
4.2 Modulo Addressing
• Register Indirect Post-Modified Modulo Addressing is a method of providing an
• Register Indirect Pre-Modified automated means to support circular data buffers using
• Register Indirect with Register Offset (Indexed) hardware. The objective is to remove the need for
software to perform data address boundary checks
• Register Indirect with Literal Offset
when executing tightly looped code, as is typical in
• 8-bit Literal many DSP algorithms.
• 16-bit Literal
Modulo Addressing can operate in either data or
Note: Not all instructions support all the address- program space (since the data pointer mechanism is
ing modes given above. Individual essentially the same for both). One circular buffer can be
instructions may support different subsets supported in each of the X (which also provides the
of these addressing modes. pointers into program space) and Y data spaces. Modulo
Addressing can operate on any W register pointer.
4.1.4 MAC INSTRUCTIONS However, it is not advisable to use W14 or W15 for
The dual source operand DSP instructions (CLR, ED, Modulo Addressing, since these two registers are used
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also as the Stack Frame Pointer and Stack Pointer,
referred to as MAC instructions, utilize a simplified set of respectively.
addressing modes to allow the user to effectively In general, any particular circular buffer can only be
manipulate the data pointers through Register Indirect configured to operate in one direction, as there are
tables. certain restrictions on the buffer start address (for
The two source operand prefetch registers must be a incrementing buffers) or end address (for decrementing
member of the set {W8, W9, W10, W11}. For data reads, buffers) based upon the direction of the buffer.
W8 and W9 will always be directed to the X RAGU and The only exception to the usage restrictions is for
W10 and W11 will always be directed to the Y AGU. The buffers which have a power-of-2 length. As these
Effective Addresses generated (before and after buffers satisfy the start and end address criteria, they
modification) must, therefore, be valid addresses within may operate in a Bidirectional mode, (i.e., address
X data space for W8 and W9 and Y data space for W10 boundary checks will be performed on both the lower
and W11. and upper address boundaries).
Note: Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).

DS70150D-page 36 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
4.2.1 START AND END ADDRESS 4.2.2 W ADDRESS REGISTER
The Modulo Addressing scheme requires that a SELECTION
starting and an ending address be specified and loaded The Modulo and Bit-Reversed Addressing Control
into the 16-bit Modulo Buffer Address registers: register, MODCON<15:0>, contains enable flags, as
XMODSRT, XMODEND, YMODSRT and YMODEND well as a W register field to specify the W Address
(see Table 3-3). registers. The XWM and YWM fields select which
registers will operate with Modulo Addressing. If
Note: Y space Modulo Addressing EA
XWM = 15, X RAGU and X WAGU Modulo Addressing
calculations assume word-sized data (LSb
are disabled. Similarly, if YWM = 15, Y AGU Modulo
of every EA is always clear).
Addressing is disabled.
The length of a circular buffer is not directly specified. It
The X Address Space Pointer W register (XWM) to
is determined by the difference between the
which Modulo Addressing is to be applied, is stored in
corresponding start and end addresses. The maximum
MODCON<3:0> (see Table 3-3). Modulo Addressing is
possible length of the circular buffer is 32K words
enabled for X data space when XWM is set to any value
(64 Kbytes).
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Byte
Address MOV #0x1100,W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
0x1100 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value

0x1163

Start Addr = 0x1100

End Addr = 0x1163
Length = 0x0032 words

© 2008 Microchip Technology Inc. DS70150D-page 37

dsPIC30F6010A/6015
4.2.3 MODULO ADDRESSING If the length of a Bit-Reversed buffer is M = 2N bytes,
APPLICABILITY then the last ‘N’ bits of the data buffer start address
must be zeros.
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier or
register. It is important to realize that the address ‘pivot point’ which is typically a constant. In the case of
boundaries check for addresses less than or greater an FFT computation, its value is equal to half of the FFT
than the upper (for incrementing buffers) and lower (for data buffer size.
decrementing buffers) boundary addresses (not just Note: All Bit-Reversed EA calculations assume
equal to). Address changes may, therefore, jump word-sized data (LSb of every EA is
beyond boundaries and still be adjusted correctly. always clear). The XB value is scaled
Note: The modulo corrected Effective Address is accordingly to generate compatible (byte)
written back to the register only when addresses.
Pre-Modify or Post-Modify Addressing When enabled, Bit-Reversed Addressing will only be
mode is used to compute the Effective executed for Register Indirect with Pre-Increment or
Address. When an address offset Post-Increment Addressing and word-sized data writes.
(e.g., [W7+W2]) is used, Modulo Address It will not function for any other addressing mode or for
correction is performed, but the contents byte-sized data, and normal addresses will be generated
of the register remains unchanged. instead. When Bit-Reversed Addressing is active, the W
Address Pointer will always be added to the address
4.3 Bit-Reversed Addressing modifier (XB) and the offset associated with the Register
Indirect Addressing mode will be ignored. In addition, as
Bit-Reversed Addressing is intended to simplify data word-sized data is a requirement, the LSb of the EA is
re-ordering for radix-2 FFT algorithms. It is supported ignored (and always clear).
by the X AGU for data writes only.
Note: Modulo Addressing and Bit-Reversed
The modifier, which may be a constant value or register
Addressing should not be enabled
contents, is regarded as having its bit order reversed.
together. In the event that the user
The address source and destination are kept in normal
attempts to do this, Bit-Reversed
order. Thus, the only operand requiring reversal is the
Addressing will assume priority when
modifier.
active for the X WAGU, and X WAGU
4.3.1 BIT-REVERSED ADDRESSING Modulo Addressing will be disabled.
However, Modulo Addressing will continue
IMPLEMENTATION
to function in the X RAGU.
Bit-Reversed Addressing is enabled when:
If Bit-Reversed Addressing has already been enabled
1. BWM (W register selection) in the MODCON by setting the BREN (XBREV<15>) bit, then a write to
register is any value other than 15 (the stack can the XBREV register should not be immediately followed
not be accessed using Bit-Reversed Addressing) by an indirect read operation using the W register that
and has been designated as the Bit-Reversed Pointer.
2. the BREN bit is set in the XBREV register and
3. the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0

Bit-Reversed Address

Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer

DS70150D-page 38 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value
4096 0x0800
2048 0x0400
1024 0x0200
512 0x0100
256 0x0080
128 0x0040
64 0x0020
32 0x0010
16 0x0008
8 0x0004
4 0x0002
2 0x0001

© 2008 Microchip Technology Inc. DS70150D-page 39

dsPIC30F6010A/6015
NOTES:

DS70150D-page 40 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
5.0 INTERRUPTS use of the alternate vector table.
• INTTREG<15:0>
Note: This data sheet summarizes features of The associated interrupt vector number and the
this group of dsPIC30F devices and is not new CPU interrupt priority level are latched into
intended to be a complete reference Vector number (VECNUM<5:0>) and Interrupt
source. For more information on the CPU, level ILR<3:0> bit fields in the INTTREG register.
peripherals, register descriptions and The new interrupt priority level is the priority of the
general device functionality, refer to the pending interrupt.
“dsPIC30F Family Reference Manual”
Note: Interrupt flag bits get set when an interrupt
(DS70046). For more information on the
condition occurs, regardless of the state of
device instruction set and programming,
its corresponding enable bit. User
refer to the “dsPIC30F/33F Programmers
software should ensure the appropriate
Reference Manual” (DS70157).
interrupt flag bits are clear prior to
The dsPIC30F6010A/6015 has 44 interrupt sources enabling an interrupt.
and four processor exceptions (traps), which must be All interrupt sources can be user assigned to one of
arbitrated based on a priority scheme. seven priority levels, 1 through 7, via the IPCx
The CPU is responsible for reading the Interrupt registers. Each interrupt source is associated with an
Vector Table (IVT) and transferring the address interrupt vector, as shown in Table 5-1. Levels 7 and 1
contained in the interrupt vector to the program represent the highest and lowest maskable priorities,
counter. The interrupt vector is transferred from the respectively.
program data bus into the program counter, via a
24-bit wide multiplexer on the input of the program Note: Assigning a priority level of 0 to an
counter. interrupt source is equivalent to disabling
that interrupt.
The Interrupt Vector Table (IVT) and Alternate
Interrupt Vector Table (AIVT) are placed near the If the NSTDIS bit (INTCON1<15>) is set, nesting of
beginning of program memory (0x000004). The IVT interrupts is prevented. Thus, if an interrupt is currently
and AIVT are shown in Figure 5-1. being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
The interrupt controller is responsible for
than the one currently being serviced.
pre-processing the interrupts and processor
exceptions, prior to their being presented to the Note: The IPL bits become read-only whenever
processor core. The peripheral interrupts and traps are the NSTDIS bit has been set to ‘1’.
enabled, prioritized and controlled using centralized
Certain interrupts have specialized control bits for
Special Function Registers:
features like edge or level triggered interrupts,
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0> interrupt-on-change, etc. Control of these features
All Interrupt Request Flags are maintained in remains within the peripheral module which generates
these three registers. The flags are set by their the interrupt.
respective peripherals or external signals, and
they are cleared via software. The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
certain number of instructions, during which the DISI bit
All Interrupt Enable Control bits are maintained in
(INTCON2<14>) remains set.
these three registers. These control bits are used
to individually enable interrupts from the When an interrupt is serviced, the PC is loaded with the
peripherals or external signals. address stored in the vector location in program
• IPC0<15:0>... IPC11<7:0> memory that corresponds to the interrupt. There are 63
The user assignable priority level associated with different vectors within the IVT (refer to Figure 5-2).
each of these 44 interrupts is held centrally in These vectors are contained in locations 0x000004
these twelve registers. through 0x0000FE of program memory (refer to
• IPL<3:0> Figure 5-2). These locations contain 24-bit addresses,
The current CPU priority level is explicitly stored and in order to preserve robustness, an address error
in the IPL bits. IPL<3> is present in the CORCON trap will take place should the PC attempt to fetch any
register, whereas IPL<2:0> are present in the of these words during normal execution. This prevents
STATUS register (SR) in the processor core. execution of random data as a result of accidentally
• INTCON1<15:0>, INTCON2<15:0> decrementing a PC into vector space, accidentally
Global interrupt control functions are derived from mapping a data space address into vector space, or the
these two registers. INTCON1 contains the PC rolling over to 0x000000 after reaching the end of
control and status flags for the processor implemented program memory space. Execution of a
exceptions. The INTCON2 register controls the GOTO instruction to this vector space will also generate
external interrupt request signal behavior and the an address error trap.

© 2008 Microchip Technology Inc. DS70150D-page 41

dsPIC30F6010A/6015
5.1 Interrupt Priority TABLE 5-1: INTERRUPT VECTOR TABLE
The user-assignable Interrupt Priority (IP<2:0>) bits INT Vector
Interrupt Source
for each individual interrupt source are located in the Number Number
Least Significant 3 bits of each nibble within the IPCx Highest Natural Order Priority
register(s). Bit 3 of each nibble is not used and is read 0 8 INT0 – External Interrupt 0
as a ‘0’. These bits define the priority level assigned 1 9 IC1 – Input Capture 1
to a particular interrupt by the user.
2 10 OC1 – Output Compare 1
Note: The user-assignable priority levels start at 3 11 T1 – Timer1
0, as the lowest priority and level 7, as the 4 12 IC2 – Input Capture 2
highest priority. 5 13 OC2 – Output Compare 2
Since more than one interrupt request source may be 6 14 T2 – Timer2
assigned to a specific user-assigned priority level, a 7 15 T3 – Timer3
means is provided to assign priority within a given level.
8 16 SPI1
This method is called “Natural Order Priority”.
9 17 U1RX – UART1 Receiver
Natural Order Priority is determined by the position of 10 18 U1TX – UART1 Transmitter
an interrupt in the vector table, and only affects
11 19 ADC – ADC Convert Done
interrupt operation when multiple interrupts with the
12 20 NVM - NVM Write Complete
same user-assigned priority become pending at the
same time. 13 21 SI2C – I2C™ Slave Interrupt
14 22 MI2C – I2C Master Interrupt
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their associated 15 23 Input Change Interrupt
vector numbers. 16 24 INT1 – External Interrupt 1
17 25 IC7 – Input Capture 7
Note 1: The Natural Order Priority scheme has 0
18 26 IC8 – Input Capture 8
as the highest priority and 53 as the
lowest priority. 19 27 OC3 – Output Compare 3
20 28 OC4 – Output Compare 4
2: The Natural Order Priority number is the
21 29 T4 – Timer4
same as the INT number.
22 30 T5 – Timer5
The ability for the user to assign every interrupt to one
23 31 INT2 – External Interrupt 2
of seven priority levels means that the user can assign
24 32 U2RX – UART2 Receiver
a very high overall priority level to an interrupt with a
low natural order priority. 25 33 U2TX – UART2 Transmitter
26 34 SPI2
27 35 C1 – Combined IRQ for CAN1
28 36 IC3 – Input Capture 3
29 37 IC4 – Input Capture 4
30 38 IC5 – Input Capture 5
31 39 IC6 – Input Capture 6
32 40 OC5 – Output Compare 5
33 41 OC6 – Output Compare 6
34 42 OC7 – Output Compare 7
35 43 OC8 – Output Compare 8
36 44 INT3 – External Interrupt 3
37 45 INT4 - External Interrupt 4
38 46 C2 – Combined IRQ for CAN2
39 47 PWM – PWM Period Match
40 48 QEI – QEI Interrupt
41 49 Reserved
42 50 Reserved
43 51 FLTA – PWM Fault A
44 52 FLTB – PWM Fault B
45-53 53-61 Reserved
Lowest Natural Order Priority

DS70150D-page 42 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
5.2 Reset Sequence 5.3 Traps
A Reset is not a true exception because the interrupt Traps can be considered as non-maskable interrupts
controller is not involved in the Reset process. The indicating a software or hardware error, which adhere
processor initializes its registers in response to a Reset to a predefined priority, as shown in Figure 5-1. They
which forces the PC to zero. The processor then begins are intended to provide the user a means to correct
program execution at location 0x000000. A GOTO erroneous operation during debug and when operating
instruction is stored in the first program memory within the application.
location, immediately followed by the address target for
Note: If the user does not intend to take
the GOTO instruction. The processor executes the GOTO
corrective action in the event of a trap
to the specified address and then begins operation at
error condition, these vectors must be
the specified target (start) address.
loaded with the address of a default
5.2.1 RESET SOURCES handler that simply contains the RESET
instruction. If, on the other hand, one of
There are six sources of error which will cause a device the vectors containing an invalid address
Reset. is called, an address error trap is
• Watchdog Time-out: generated.
The watchdog has timed out, indicating that the Note that many of these trap conditions can only be
processor is no longer executing the correct flow detected when they occur. Consequently, the
of code. questionable instruction is allowed to complete prior to
• Uninitialized W Register Trap: trap exception processing. If the user chooses to
An attempt to use an uninitialized W register as recover from the error, the result of the erroneous
an Address Pointer will cause a Reset. action that caused the trap may have to be corrected.
• Illegal Instruction Trap: There are 8 fixed priority levels for traps: Level 8
Attempted execution of any unused opcodes will through Level 15, which means that IPL3 is always set
result in an illegal instruction trap. Note that a during processing of a trap.
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed If the user is not currently executing a trap, and he sets
prior to execution due to a flow change. the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
5.3.1 TRAP SOURCES
device has been detected which may result in
malfunction. The following traps are provided with increasing prior-
• Trap Lockout: ity. However, since all traps can be nested, priority has
Occurrence of multiple trap conditions little effect.
simultaneously will cause a Reset.
Math Error Trap:
The math error trap executes under the following four
circumstances:
• Should an attempt be made to divide by zero, the
divide operation will be aborted on a cycle bound-
ary and the trap taken.
• If enabled, a math error trap will be taken when an
arithmetic operation on either Accumulator A or B
causes an overflow from bit 31 and the Accumula-
tor Guard bits are not utilized.
• If enabled, a math error trap will be taken when an
arithmetic operation on either Accumulator A or B
causes a catastrophic overflow from bit 39 and all
saturation is disabled.
• If the shift amount specified in a shift instruction is
greater than the maximum allowed shift amount, a
trap will occur.

© 2008 Microchip Technology Inc. DS70150D-page 43

dsPIC30F6010A/6015
Address Error Trap: 5.3.2 HARD AND SOFT TRAPS
This trap is initiated when any of the following It is possible that multiple traps can become active
circumstances occurs: within the same cycle (e.g., a misaligned word stack
• A misaligned data word access is attempted. write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
• A data fetch from our unimplemented data
which may require the user to check if other traps are
memory location is attempted.
pending in order to completely correct the Fault.
• A data access of an unimplemented program
memory location is attempted. ‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
• An instruction fetch from vector space is
falls into this category of traps.
attempted.
‘Hard’ traps include exceptions of priority level 12
Note: In the MAC class of instructions, wherein
through level 15, inclusive. The address error (level
the data space is split into X and Y data
12), stack error (level 13) and oscillator error (level 14)
space, unimplemented X space includes
traps fall into this category.
all of Y space, and unimplemented Y
space includes all of X space. Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
4. Execution of a “BRA #literal” instruction or a
lower priority hard trap occurs while a higher priority
“GOTO #literal” instruction, where literal
trap is pending, Acknowledged, or is being processed,
is an unimplemented program memory address.
a hard trap conflict will occur.
5. Executing instructions after modifying the PC to
point to unimplemented program memory The device is automatically reset in a hard trap conflict
addresses. The PC may be modified by loading condition. The TRAPR Status bit (RCON<15>) is set
a value into the stack and executing a RETURN when the Reset occurs, so that the condition may be
instruction. detected in software.

Stack Error Trap: FIGURE 5-1: TRAP VECTORS

This trap is initiated under the following conditions:
Reset – GOTO Instruction 0x000000
1. The Stack Pointer is loaded with a value which Reset – GOTO Address 0x000002
is greater than the (user programmable) limit Reserved 0x000004
Oscillator Fail Trap Vector
value written into the SPLIM register (stack Address Error Trap Vector
Stack Error Trap Vector
overflow).
Decreasing

Math Error Trap Vector

Priority

2. The Stack Pointer is loaded with a value which IVT Reserved Vector
Reserved Vector
is less than 0x0800 (simple stack underflow). Reserved Vector
Interrupt 0 Vector 0x000014
Interrupt 1 Vector
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
Interrupt 52 Vector
operation becomes reliant on an internal RC backup. Interrupt 53 Vector 0x00007E
Reserved 0x000080
Reserved 0x000082
Reserved 0x000084
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
AIVT Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector 0x000094
Interrupt 1 Vector

Interrupt 52 Vector
Interrupt 53 Vector 0x0000FE

DS70150D-page 44 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
5.4 Interrupt Sequence 5.5 Alternate Vector Table
All interrupt event flags are sampled in the beginning of In program memory, the Interrupt Vector Table (IVT) is
each instruction cycle by the IFSx registers. A pending followed by the Alternate Interrupt Vector Table (AIVT),
Interrupt Request (IRQ) is indicated by the flag bit as shown in Figure 5-1. Access to the Alternate Vector
being equal to a ‘1’ in an IFSx register. The IRQ will Table is provided by the ALTIVT bit in the INTCON2
cause an interrupt to occur if the corresponding bit in register. If the ALTIVT bit is set, all interrupt and excep-
the Interrupt Enable (IECx) register is set. For the tion processes will use the alternate vectors instead of
remainder of the instruction cycle, the priorities of all the default vectors. The alternate vectors are organized
pending interrupt requests are evaluated. in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
If there is a pending IRQ with a priority level greater
a means to switch between an application and a
than the current processor priority level in the IPL bits,
support environment, without requiring the interrupt
the processor will be interrupted.
vectors to be reprogrammed. This feature also enables
The processor then stacks the current program counter switching between applications for evaluation of
and the low byte of the processor STATUS register different software algorithms at run time.
(SRL), as shown in Figure 5-2. The low byte of the
If the AIVT is not required, the program memory
STATUS register contains the processor priority level at
allocated to the AIVT may be used for other purposes.
the time prior to the beginning of the interrupt cycle.
AIVT is not a protected section and may be freely
The processor then loads the priority level for this inter-
programmed by the user.
rupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
5.6 Fast Context Saving
Interrupt Service Routine.
A context saving option is available using shadow
FIGURE 5-2: INTERRUPT STACK registers. Shadow registers are provided for the DC, N,
FRAME OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
0x0000 15 0 registers are accessible using the PUSH.S and POP.S
instructions only.
Stack Grows Towards

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current
Higher Address

value of the aforementioned registers into their

respective shadow registers.
PC<15:0> W15 (before CALL)
SRL IPL3 PC<22:16> If an ISR of a certain priority uses the PUSH.S and
<Free Word> W15 (after CALL) POP.S instructions for fast context saving, then a
higher priority ISR should not include the same
POP : [--W15] instructions. Users must save the key registers in
PUSH : [W15++]
software during a lower priority interrupt, if the higher
priority ISR uses fast context saving.
Note 1: The user can always lower the priority level
5.7 External Interrupt Requests
by writing a new value into SR. The Interrupt
Service Routine must clear the interrupt flag The interrupt controller supports five external interrupt
bits in the IFSx register before lowering the request signals, INT0-INT4. These inputs are edge
processor interrupt priority in order to avoid sensitive; they require a low-to-high or a high-to-low
recursive interrupts. transition to generate an interrupt request. The
2: The IPL3 bit (CORCON<3>) is always clear INTCON2 register has five bits, INT0EP-INT4EP, that
when interrupts are being processed. It is select the polarity of the edge detection circuitry.
set only during execution of traps.
The RETFIE (Return from Interrupt) instruction will 5.8 Wake-up from Sleep and Idle
unstack the program counter and STATUS registers to The interrupt controller may be used to wake-up the
return the processor to its state prior to the interrupt processor from either Sleep or Idle modes, if Sleep or
sequence. Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.

© 2008 Microchip Technology Inc. DS70150D-page 45

 TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6010A(1)
DS70150D-page 46

dsPIC30F6010A/6015
SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — FLTBIF FLTAIF — — QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — FLTBIE FLTAIE — — QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100
IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100
IPC9 00A6 — PWMIP<2:0> — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0> 0100 0100 0100 0100
IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0000
IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100
INTTREG 00B0 — — — — ILR<3:0> — — VECNUM<5:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6015(1)
© 2008 Microchip Technology Inc.

SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — FLTBIF FLTAIF — — QEIIF PWMIF — INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — FLTBIE FLTAIE — — QEIIE PWMIE — INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100
IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100
IPC9 00A6 — PWMIP<2:0> — — — — — INT41IP<2:0> — INT3IP<2:0> 0100 0000 0100 0100
IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0000

dsPIC30F6010A/6015
IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100
INTTREG 00B0 — — — — ILR<3:0> — — VECNUM<5:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70150D-page 47
dsPIC30F6010A/6015
NOTES:

DS70150D-page 48 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
6.0 FLASH PROGRAM MEMORY 6.2 Run-Time Self-Programming
(RTSP)
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not RTSP is accomplished using TBLRD (table read) and
intended to be a complete reference TBLWT (table write) instructions.
source. For more information on the CPU, With RTSP, the user may erase program memory,
peripherals, register descriptions and 32 instructions (96 bytes) at a time and can write
general device functionality, refer to the program memory data, 32 instructions (96 bytes) at a
“dsPIC30F Family Reference Manual” time.
(DS70046). For more information on the
device instruction set and programming,
6.3 Table Instruction Operation Summary
refer to the “dsPIC30F/33F Programmers
Reference Manual” (DS70157). The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
The dsPIC30F family of devices contains internal
TBLRDL and TBLWTL can access program memory in
program Flash memory for executing user code. There
Word or Byte mode.
are two methods by which the user can program this
memory: The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
1. In-Circuit Serial Programming™ (ICSP™)
and TBLWTH can access program memory in Word or
2. Run-Time Self-Programming (RTSP) Byte mode.
A 24-bit program memory address is formed using
6.1 In-Circuit Serial Programming
bits<7:0> of the TBLPAG register and the Effective
(ICSP) Address (EA) from a W register specified in the table
dsPIC30F devices can be serially programmed while in instruction, as shown in Figure 6-1.
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.

FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS

24 bits
Using
Program 0 Program Counter 0
Counter

NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits

Working Reg EA

Using 1/0 TBLPAG Reg

Table
Instruction 8 bits 16 bits

Byte
User/Configuration Select
Space Select 24-bit EA

© 2008 Microchip Technology Inc. DS70150D-page 49

dsPIC30F6010A/6015
6.4 RTSP Operation 6.5 RTSP Control Registers
The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program
into rows and panels. Each row consists of 32 instruc- Flash memory are:
tions, or 96 bytes. Each panel consists of 128 rows, or • NVMCON
4K x 24 instructions. RTSP allows the user to erase one • NVMADR
row (32 instructions) at a time and to program • NVMADRU
32 instructions at one time. • NVMKEY
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to 6.5.1 NVMCON REGISTER
the actual programming operation, the write data must The NVMCON register controls which blocks are to be
be loaded into the panel write latches. The data to be erased, which memory type is to be programmed and
programmed into the panel is loaded in sequential start of the programming cycle.
order into the write latches; instruction 0, instruction 1,
etc. The addresses loaded must always be from a 32 6.5.2 NVMADR REGISTER
address boundary.
The NVMADR register is used to hold the lower two
The basic sequence for RTSP programming is to set up bytes of the Effective Address. The NVMADR register
a Table Pointer, then do a series of TBLWT instructions captures the EA<15:0> of the last table instruction that
to load the write latches. Programming is performed by has been executed and selects the row to write.
setting the special bits in the NVMCON register. 32
TBLWTL and 32 TBLWTH instructions are required to 6.5.3 NVMADRU REGISTER
load the 32 instructions.
The NVMADRU register is used to hold the upper byte
All of the table write operations are single-word writes of the Effective Address. The NVMADRU register
(2 instruction cycles), because only the table latches captures the EA<23:16> of the last table instruction
are written. that has been executed.
After the latches are written, a programming operation
needs to be initiated to program the data. 6.5.4 NVMKEY REGISTER
The Flash program memory is readable, writable and NVMKEY is a write-only register that is used for write
erasable during normal operation over the entire VDD protection. To start a programming or an erase
range. sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note: The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.

DS70150D-page 50 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
6.6 Programming Operations 4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
A complete programming sequence is necessary for latches.
programming or erasing the internal Flash in RTSP
5. Program 32 instruction words into program
mode. A programming operation is nominally 2 msec in
Flash.
duration and the processor stalls (waits) until the
operation is finished. Setting the WR bit a) Set up NVMCON register for multi-word,
(NVMCON<15>) starts the operation, and the WR bit is program Flash, program, and set WREN
automatically cleared when the operation is finished. bit.
b) Write ‘0x55’ to NVMKEY.
6.6.1 PROGRAMMING ALGORITHM FOR c) Write ‘0xAA’ to NVMKEY.
PROGRAM FLASH d) Set the WR bit. This will begin program
The user can erase or program one row of program cycle.
Flash memory at a time. The general process is: e) CPU will stall for duration of the program
1. Read one row of program Flash (32 instruction cycle.
words) and store into data RAM as a data f) The WR bit is cleared by the hardware
“image”. when program cycle ends.
2. Update the data image with the desired new 6. Repeat steps 1 through 5 as needed to program
data. desired amount of program Flash memory.
3. Erase program Flash row.
6.6.2 ERASING A ROW OF PROGRAM
a) Set up NVMCON register for multi-word,
MEMORY
program Flash, erase, and set WREN bit.
b) Write address of row to be erased into Example 6-1 shows a code sequence that can be used
NVMADRU/NVMDR. to erase a row (32 instructions) of program memory.
c) Write ‘0x55’ to NVMKEY.
d) Write ‘0xAA’ to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.

EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV #0x4041,W0 ;
MOV W0,NVMCON ; Init NVMCON SFR
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR),W0 ;
MOV W0,NVMADRU ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer
MOV W0, NVMADR ; Intialize NVMADR SFR
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

© 2008 Microchip Technology Inc. DS70150D-page 51

dsPIC30F6010A/6015
6.6.3 LOADING WRITE LATCHES
Example 6-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches.
32 TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the Table Pointer.

EXAMPLE 6-2: LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000,W0 ;
MOV W0,TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000,W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0,W2 ;
MOV #HIGH_BYTE_0,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1,W2 ;
MOV #HIGH_BYTE_1,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2,W2 ;
MOV #HIGH_BYTE_2,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
; 31st_program_word
MOV #LOW_WORD_31,W2 ;
MOV #HIGH_BYTE_31,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

6.6.4 INITIATING THE PROGRAMMING

SEQUENCE
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.

EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

DS70150D-page 52 © 2008 Microchip Technology Inc.

 TABLE 6-1: NVM REGISTER MAP(1)
© 2008 Microchip Technology Inc.

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 53
dsPIC30F6010A/6015
NOTES:

DS70150D-page 54 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
7.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is
Note: This data sheet summarizes features of responsible for waiting for the appropriate duration of
this group of dsPIC30F devices and is not time before initiating another data EEPROM write/
intended to be a complete reference erase operation. Attempting to read the data EEPROM
source. For more information on the CPU, while a programming or erase operation is in progress
peripherals, register descriptions and results in unspecified data.
general device functionality, refer to the Control bit WR initiates write operations, similar to
“dsPIC30F Family Reference Manual” program Flash writes. This bit cannot be cleared, only
(DS70046). For more information on the set, in software. This bit is cleared in hardware at the
device instruction set and programming, completion of the write operation. The inability to clear
refer to the “dsPIC30F/33F Programmers the WR bit in software prevents the accidental or
Reference Manual” (DS70157). premature termination of a write operation.
The data EEPROM memory is readable and writable The WREN bit, when set, will allow a write operation.
during normal operation over the entire VDD range. The On power-up, the WREN bit is clear. The WRERR bit is
data EEPROM memory is directly mapped in the set when a write operation is interrupted by a MCLR
program memory address space. Reset, or a WDT Time-out Reset, during normal
The four SFRs used to read and write the program operation. In these situations, following Reset, the user
Flash memory are used to access data EEPROM can check the WRERR bit and rewrite the location. The
memory, as well. As described in Section 4.0 address register NVMADR remains unchanged.
“Address Generator Units”, these registers are: Note: Interrupt flag bit NVMIF in the IFS0
• NVMCON register is set when write is complete. It
• NVMADR must be cleared in software.
• NVMADRU
• NVMKEY 7.1 Reading the Data EEPROM
The EEPROM data memory allows read and write of
A TBLRD instruction reads a word at the current
single words and 16-word blocks. When interfacing to
program word address. This example uses W0 as a
data memory, NVMADR, in conjunction with the
pointer to data EEPROM. The result is placed in
NVMADRU register, is used to address the EEPROM
register W4, as shown in Example 7-1.
location being accessed. TBLRDL and TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F6010 device has 8 Kbytes (4K words) of EXAMPLE 7-1: DATA EEPROM READ
data EEPROM, with an address range from 0x7FF000 MOV #LOW_ADDR_WORD,W0 ; Init Pointer
to 0x7FFFFE. MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
A word write operation should be preceded by an erase TBLRDL [ W0 ], W4 ; read data EEPROM
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.

© 2008 Microchip Technology Inc. DS70150D-page 55

dsPIC30F6010A/6015
7.2 Erasing Data EEPROM
7.2.1 ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially
point to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM and
set the WR and WREN bits in the NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-2.

EXAMPLE 7-2: DATA EEPROM BLOCK ERASE

; Select data EEPROM block, WR, WREN bits
MOV #4045,W0
MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

7.2.2 ERASING A WORD OF DATA

EEPROM
The NVMADRU and NVMADR registers must point to
the block. Select a block of data Flash and set the WR
and WREN bits in the NVMCON register. Setting the
WR bit initiates the erase, as shown in Example 7-3.

EXAMPLE 7-3: DATA EEPROM WORD ERASE

; Select data EEPROM word, WR, WREN bits
MOV #4044,W0
MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

DS70150D-page 56 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
7.3 Writing to the Data EEPROM The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly
sequence must be followed: recommended that interrupts be disabled during this
1. Erase data EEPROM word. code segment.
a) Select word, data EEPROM, erase and set Additionally, the WREN bit in NVMCON must be set to
WREN bit in NVMCON register. enable writes. This mechanism prevents accidental
b) Write address of word to be erased into writes to data EEPROM, due to unexpected code
NVMADRU/NVMADR. execution. The WREN bit should be kept clear at all
c) Enable NVM interrupt (optional). times, except when updating the EEPROM. The
WREN bit is not cleared by hardware.
d) Write ‘0x55’ to NVMKEY.
e) Write ‘0xAA’ to NVMKEY. After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
f) Set the WR bit. This will begin erase cycle.
bit will be inhibited from being set unless the WREN bit
g) Either poll NVMIF bit or wait for NVMIF is set. The WREN bit must be set on a previous
interrupt. instruction. Both WR and WREN cannot be set with the
h) The WR bit is cleared when the erase cycle same instruction.
ends.
At the completion of the write cycle, the WR bit is
2. Write data word into data EEPROM write cleared in hardware and the Nonvolatile Memory Write
latches. Complete Interrupt Flag bit (NVMIF) is set. The user
3. Program 1 data word into data EEPROM. may either enable this interrupt, or poll this bit. NVMIF
a) Select word, data EEPROM, program and must be cleared by software.
set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional). 7.3.1 WRITING A WORD OF DATA
c) Write ‘0x55’ to NVMKEY. EEPROM
d) Write ‘0xAA’ to NVMKEY. Once the user has erased the word to be programmed,
e) Set the WR bit. This will begin program then a table write instruction is used to write one write
cycle. latch, as shown in Example 7-4.
f) Either poll NVMIF bit or wait for NVM
interrupt.
g) The WR bit is cleared when the write cycle
ends.

EXAMPLE 7-4: DATA EEPROM WORD WRITE

; Point to data memory
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #LOW(WORD),W2 ; Get data
TBLWTL W2,[ W0] ; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV #0x4004,W0
MOV W0,NVMCON

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

© 2008 Microchip Technology Inc. DS70150D-page 57

dsPIC30F6010A/6015
7.3.2 WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5: DATA EEPROM BLOCK WRITE
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #data1,W2 ; Get 1st data
TBLWTL W2,[ W0]++ ; write data
MOV #data2,W2 ; Get 2nd data
TBLWTL W2,[ W0]++ ; write data
MOV #data3,W2 ; Get 3rd data
TBLWTL W2,[ W0]++ ; write data
MOV #data4,W2 ; Get 4th data
TBLWTL W2,[ W0]++ ; write data
MOV #data5,W2 ; Get 5th data
TBLWTL W2,[ W0]++ ; write data
MOV #data6,W2 ; Get 6th data
TBLWTL W2,[ W0]++ ; write data
MOV #data7,W2 ; Get 7th data
TBLWTL W2,[ W0]++ ; write data
MOV #data8,W2 ; Get 8th data
TBLWTL W2,[ W0]++ ; write data
MOV #data9,W2 ; Get 9th data
TBLWTL W2,[ W0]++ ; write data
MOV #data10,W2 ; Get 10th data
TBLWTL W2,[ W0]++ ; write data
MOV #data11,W2 ; Get 11th data
TBLWTL W2,[ W0]++ ; write data
MOV #data12,W2 ; Get 12th data
TBLWTL W2,[ W0]++ ; write data
MOV #data13,W2 ; Get 13th data
TBLWTL W2,[ W0]++ ; write data
MOV #data14,W2 ; Get 14th data
TBLWTL W2,[ W0]++ ; write data
MOV #data15,W2 ; Get 15th data
TBLWTL W2,[ W0]++ ; write data
MOV #data16,W2 ; Get 16th data
TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.
MOV #0x400A,W0 ; Select data EEPROM for multi word op
MOV W0,NVMCON ; Operate Key to allow program operation
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start write cycle
NOP
NOP

7.4 Write Verify 7.5 Protection Against Spurious Write

Depending on the application, good programming There are conditions when the device may not want to
practice may dictate that the value written to the write to the data EEPROM memory. To protect against
memory should be verified against the original value. spurious EEPROM writes, various mechanisms have
This should be used in applications where excessive been built-in. On power-up, the WREN bit is cleared;
writes can stress bits near the specification limit. also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together,
help prevent an accidental write during brown-out,
power glitch or software malfunction.

DS70150D-page 58 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
8.0 I/O PORTS Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
Note: This data sheet summarizes features of port pins, write the latch (LATx).
this group of dsPIC30F devices and is not Any bit and its associated data and control registers
intended to be a complete reference that are not valid for a particular device will be
source. For more information on the CPU, disabled. That means the corresponding LATx and
peripherals, register descriptions and TRISx registers and the port pin will read as zeros.
general device functionality, refer to the
dsPIC30F Family Reference Manual When a pin is shared with another peripheral or
(DS70046). function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
All of the device pins (except VDD, VSS, MCLR and there is no other competing source of outputs. An
OSC1/CLKI) are shared between the peripherals and example is the INT4 pin. Figure 8-1 shows the
the parallel I/O ports. structure for a dedicated port.
All I/O input ports feature Schmitt Trigger inputs for The format of the registers for PORTA are shown in
improved noise immunity. Table 8-1.
The TRISA (Data Direction Control) register controls
8.1 Parallel I/O (PIO) Ports the direction of the RA<7:0> pins, as well as the INTx
When a peripheral is enabled and the peripheral is pins and the VREF pins. The LATA register supplies
actively driving an associated pin, the use of the pin as data to the outputs and is readable/writable. Reading
a general purpose output pin is disabled. The I/O pin the PORTA register yields the state of the input pins,
may be read, but the output driver for the parallel port while writing the PORTA register modifies the contents
bit will be disabled. If a peripheral is enabled, but the of the LATA register.
peripheral is not actively driving a pin, that pin may be A parallel I/O (PIO) port that shares a pin with a
driven by a port. peripheral is, in general, subservient to the peripheral.
All port pins have three registers directly associated The peripheral’s output buffer data and control signals
with the operation of the port pin. The data direction are provided to a pair of multiplexers. The multiplexers
register (TRISx) determines whether the pin is an input select whether the peripheral or the associated port
or an output. If the data direction bit is a ‘1’, then the pin has ownership of the output data and control signals of
is an input. All port pins are defined as inputs after a the I/O pad cell. Figure 8-2 shows how ports are shared
Reset. Reads from the latch (LATx), read the latch. with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 8-1 shows the
formats of the registers for the shared ports, PORTB
through PORTG.

FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module

Read TRIS
I/O Cell

TRIS Latch
Data Bus D Q

WR TRIS CK

Data Latch
D Q I/O Pad

WR LAT+
CK
WR Port

Read LAT

Read Port

© 2008 Microchip Technology Inc. DS70150D-page 59

dsPIC30F6010A/6015
FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Peripheral Module Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O Cell
Peripheral Output Enable 1 Output Enable
Peripheral Output Data 0

PIO Module 1
Output Data
0

Read TRIS

I/O Pad
Data Bus D Q

WR TRIS CK

TRIS Latch

D Q

WR LAT +
WR Port CK

Data Latch

Read LAT
Input Data
Read Port

8.2 Configuring Analog Port Pins 8.2.1 I/O PORT WRITE/READ TIMING
The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port
operation of the A/D port pins. The port pins that are direction change or port write operation and a read
desired as analog inputs must have their correspond- operation of the same port. Typically this instruction
ing TRIS bit set (input). If the TRIS bit is cleared would be a NOP.
(output), the digital output level (VOH or VOL) will be
converted. EXAMPLE 8-1: PORT WRITE/READ
When reading the PORT register, all pins configured as EXAMPLE
analog input channels will read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
Pins configured as digital inputs will not convert an ana- MOV W0, TRISBB ; and PORTB<7:0> as outputs
log input. Analog levels on any pin that is defined as a NOP ; Delay 1 cycle
digital input (including the ANx pins) may cause the BTSS PORTB, #13 ; Next Instruction
input buffer to consume current that exceeds the
device specifications.

DS70150D-page 60 © 2008 Microchip Technology Inc.

 TABLE 8-1: dsPIC30F6010A PORT REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
TRISA 02C0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — — — — — — — — — 1100 0110 0000 0000
PORTA 02C2 RA15 RA14 — — — RA10 RA9 — — — — — — — — — 0000 0000 0000 0000
LATA 02C4 LATA15 LATA14 — — — LATA10 LATA9 — — — — — — — — — 0000 0000 0000 0000
TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — TRISC3 — TRISC1 — 1110 0000 0000 1010
PORTC 02CE RC15 RC14 RC13 — — — — — — — — — RC3 — RC1 — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — LATC3 — LATC1 — 0000 0000 0000 0000
TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000
LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000
TRISE 02D8 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0011 1111 1111
PORTE 02DA — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
LATE 02DC — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000
TRISF 02EE — — — — — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0001 1111 1111
PORTF 02E0 — — — — — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000

dsPIC30F6010A/6015
LATF 02E2 — — — — — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
TRISG 02E4 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 0000 0011 1100 1111
PORTG 02E6 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 0000 0000 0000 0000
LATG 02E8 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70150D-page 61
 TABLE 8-2: dsPIC30F6015 PORT REGISTER MAP(1)
DS70150D-page 62

dsPIC30F6010A/6015
SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
TRISA 02C0 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
PORTA 02C2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
LATA 02C4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000
PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000
TRISD 02D2 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0000 1111 1111 1111
PORTD 02D4 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000
LATD 02D6 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000
TRISE 02D8 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0000 1111 1111
PORTE 02DA — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
LATE 02DC — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000
TRISF 02EE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111
PORTF 02E0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000
LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
TRISG 02E4 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 0000 0011 1100 1100
PORTG 02E6 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — 0000 0000 0000 0000
LATG 02E8 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F6010A/6015
8.3 Input Change Notification Module
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a
change-of-state on selected input pins. This module is
capable of detecting input change-of-states, even in
Sleep mode when the clocks are disabled. There are 22
external signals (CN0 through CN21) for
dsPIC30F6010A and 19 external signals (CN0 through
CN19) for dsPIC30F6015 that may be selected (enabled)
for generating an interrupt request on a change-of-state.
Please refer to the Pin Diagrams for CN pin locations.

TABLE 8-3: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)(1)

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State
Name

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 8-4: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F6010A(1)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 8-5: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F6015(1)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 — — — — — CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 — — — — — CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

© 2008 Microchip Technology Inc. DS70150D-page 63

dsPIC30F6010A/6015
NOTES:

DS70150D-page 64 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
9.0 TIMER1 MODULE These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
Note: This data sheet summarizes features of presents a block diagram of the 16-bit timer module.
this group of dsPIC30F devices and is not 16-bit Timer Mode: In the 16-bit Timer mode, the timer
intended to be a complete reference increments on every instruction cycle up to a match
source. For more information on the CPU, value, preloaded into the period register, PR1, then
peripherals, register descriptions and resets to ‘0’ and continues to count.
general device functionality, refer to the
“dsPIC30F Family Reference Manual” When the CPU goes into the Idle mode, the timer will
(DS70046). stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
This section describes the 16-bit General Purpose the incrementing sequence upon termination of the
(GP) Timer1 module and associated operational CPU Idle mode.
modes.
16-bit Synchronous Counter Mode: In the 16-bit
Note: Timer1 is a Type A timer. Please refer to the Synchronous Counter mode, the timer increments on
specifications for a Type A timer in the rising edge of the applied external clock signal,
Section 24.0 "Electrical Characteristics" which is synchronized with the internal phase clocks.
of this document. The timer counts up to a match value preloaded in PR1,
The following sections provide a detailed description, then resets to 0 and continues.
including setup and control registers along with When the CPU goes into the Idle mode, the timer will
associated block diagrams for the operational modes of stop incrementing, unless the respective TSIDL bit = 0.
the timers. If TSIDL = 1, the timer module logic will resume the
The Timer1 module is a 16-bit timer which can serve as incrementing sequence upon termination of the CPU
the time counter for the Real-Time Clock, or operate as Idle mode.
a free running interval timer/counter. The 16-bit timer 16-bit Asynchronous Counter Mode: In the 16-bit
has the following modes: Asynchronous Counter mode, the timer increments on
• 16-bit Timer every rising edge of the applied external clock signal.
• 16-bit Synchronous Counter The timer counts up to a match value preloaded in PR1,
• 16-bit Asynchronous Counter then resets to ‘0’ and continues.

Further, the following operational characteristics are When the timer is configured for the Asynchronous mode
supported: of operation and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal

© 2008 Microchip Technology Inc. DS70150D-page 65

dsPIC30F6010A/6015
FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)

PR1

Equal
Comparator x 16 TSYNC

1 Sync
(3)
TMR1
Reset
0

0
T1IF
Event Flag 1 Q D TGATE
Q CK
TGATE

TGATE
TCS
TCKPS<1:0>

SOSCO/ TON 2
1X
T1CK

LPOSCEN Gate Prescaler

Sync 01 1, 8, 64, 256

SOSCI
TCY 00

9.1 Timer Gate Operation 9.3 Timer Operation During Sleep

The 16-bit timer can be placed in the Gated Time
Mode
Accumulation mode. This mode allows the internal TCY During CPU Sleep mode, the timer will operate if:
to increment the respective timer when the gate input
• The timer module is enabled (TON = 1) and
signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The • The timer clock source is selected as external
timer must be enabled (TON = 1) and the timer clock (TCS = 1) and
source set to internal (TCS = 0). • The TSYNC bit (T1CON<2>) is asserted to a logic
‘0’, which defines the external clock source as
When the CPU goes into the Idle mode, the timer will
asynchronous
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon When all three conditions are true, the timer will
termination of the CPU Idle mode. continue to count up to the period register and be reset
to 0x0000.
9.2 Timer Prescaler When a match between the timer and the period
register occurs, an interrupt can be generated, if the
The input clock (FOSC/4 or external clock) to the 16-bit
respective timer interrupt enable bit is asserted.
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.

DS70150D-page 66 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
9.4 Timer Interrupt 9.5.1 RTC OSCILLATOR OPERATION
The 16-bit timer has the ability to generate an interrupt When the TON = 1, TCS = 1 and TGATE = 0, the timer
on period match. When the timer count matches the increments on the rising edge of the 32 kHz LP
period register, the T1IF bit is asserted and an interrupt oscillator output signal, up to the value specified in the
will be generated, if enabled. The T1IF bit must be period register, and is then reset to ‘0’.
cleared in software. The Timer Interrupt Flag, T1IF, is The TSYNC bit must be asserted to a logic ‘0’
located in the IFS0 Control register in the interrupt (Asynchronous mode) for correct operation.
controller.
Enabling LPOSCEN (OSCCON<1>) will disable the
When the Gated Time Accumulation mode is enabled, normal Timer and Counter modes and enable a timer
an interrupt will also be generated on the falling edge of carry-out wake-up event.
the gate signal (at the end of the accumulation cycle).
When the CPU enters Sleep mode, the RTC will
Enabling an interrupt is accomplished via the continue to operate, provided the 32 kHz external
respective Timer Interrupt Enable bit, T1IE. The Timer crystal oscillator is active and the control bits have not
Interrupt Enable bit is located in the IEC0 Control been changed. The TSIDL bit should be cleared to ‘0’
register in the interrupt controller. in order for RTC to continue operation in Idle mode.

9.5 Real-Time Clock 9.5.2 RTC INTERRUPTS

When an interrupt event occurs, the respective
Timer1, when operating in Real-Time Clock (RTC)
interrupt flag, T1IF, is asserted and an interrupt will be
mode, provides time-of-day and event time-stamping
generated, if enabled. The T1IF bit must be cleared in
capabilities. Key operational features of the RTC are:
software. The respective Timer Interrupt Flag, T1IF, is
• Operation from 32 kHz LP oscillator located in the IFS0 STATUS register in the interrupt
• 8-bit prescaler controller.
• Low power
Enabling an interrupt is accomplished via the
• Real-Time Clock interrupts
respective Timer Interrupt Enable bit, T1IE. The Timer
These operating modes are determined by setting the Interrupt Enable bit is located in the IEC0 Control
appropriate bit(s) in the T1CON Control register. register in the interrupt controller.

FIGURE 9-2: RECOMMENDED

COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC

C1
SOSCI

32.768 kHz dsPIC30FXXXX

XTAL
SOSCO
C2 R

C1 = C2 = 18 pF; R = 100K

© 2008 Microchip Technology Inc. DS70150D-page 67

 TABLE 9-1: TIMER1 REGISTER MAP(1)
DS70150D-page 68

dsPIC30F6010A/6015
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu

PR1 0102 Period Register 1 1111 1111 1111 1111
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F6010A/6015
10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the least
significant word and Timer3 is the most significant word
Note: This data sheet summarizes features of of the 32-bit timer.
this group of dsPIC30F devices and is not
Note: For 32-bit timer operation, T3CON control
intended to be a complete reference
bits are ignored. Only T2CON control bits
source. For more information on the CPU,
are used for setup and control. Timer2
peripherals, register descriptions and gen-
clock and gate inputs are utilized for the
eral device functionality, refer to the
32-bit timer module, but an interrupt is
“dsPIC30F Family Reference Manual”
generated with the Timer3 Interrupt Flag
(DS70046).
(T3IF) and the interrupt is enabled with the
This section describes the 32-bit General Purpose Timer3 Interrupt Enable bit (T3IE).
(GP) Timer module (Timer2/3) and associated opera- 16-bit Mode: In the 16-bit mode, Timer2 and Timer3
tional modes. Figure 10-1 depicts the simplified block can be configured as two independent 16-bit timers.
diagram of the 32-bit Timer2/3 module. Figure 10-3 Each timer can be set up in either 16-bit Timer mode or
and Figure 10-5 show Timer2/3 configured as two 16-bit Synchronous Counter mode. See Section 9.0
independent 16-bit timers; Timer2 and Timer3, “Timer1 Module”, Timer1 Module, for details on these
respectively. two operating modes.
Note: Timer2 is a Type B timer and Timer3 is a The only functional difference between Timer2 and
Type C timer. Please refer to the appropri- Timer3 is that Timer2 provides synchronization of the
ate timer type in Section 24.0 "Electrical clock prescaler output. This is useful for high frequency
Characteristics" of this document. external clock inputs.
The Timer2/3 module is a 32-bit timer, which can be 32-bit Timer Mode: In the 32-bit Timer mode, the timer
configured as two 16-bit timers, with selectable operat- increments on every instruction cycle up to a match
ing modes. These timers are utilized by other value, preloaded into the combined 32-bit period
peripheral modules such as: register, PR3/PR2, then resets to ‘0’ and continues to
• Input Capture count.
• Output Compare/Simple PWM For synchronous 32-bit reads of the Timer2/Timer3
The following sections provide a detailed description, pair, reading the lsw (TMR2 register) will cause the
including setup and control registers, along with asso- msw to be read and latched into a 16-bit holding
ciated block diagrams for the operational modes of the register, termed TMR3HLD.
timers. For synchronous 32-bit writes, the holding register
The 32-bit timer has the following modes: (TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
• Two independent 16-bit timers (Timer2 and will be transferred and latched into the MSB of the
Timer3) with all 16-bit operating modes (except 32-bit timer (TMR3).
Asynchronous Counter mode)
32-bit Synchronous Counter Mode: In the 32-bit
• Single 32-bit Timer operation
Synchronous Counter mode, the timer increments on
• Single 32-bit Synchronous Counter the rising edge of the applied external clock signal,
Further, the following operational characteristics are which is synchronized with the internal phase clocks.
supported: The timer counts up to a match value preloaded in the
combined 32-bit period register, PR3/PR2, then resets
• ADC Event Trigger
to ‘0’ and continues.
• Timer Gate Operation
When the timer is configured for the Synchronous
• Selectable Prescaler Settings
Counter mode of operation and the CPU goes into the
• Timer Operation during Idle and Sleep modes Idle mode, the timer will stop incrementing, unless the
• Interrupt on a 32-bit Period Register Match TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
These operating modes are determined by setting the module logic will resume the incrementing sequence
appropriate bit(s) in the 16-bit T2CON and T3CON upon termination of the CPU Idle mode.
SFRs.

© 2008 Microchip Technology Inc. DS70150D-page 69

dsPIC30F6010A/6015
FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6010A
Data Bus<15:0>

TMR3HLD
16
16
Write TMR2
Read TMR2

16

Reset
TMR3 TMR2 Sync

MSB LSB
ADC Event Trigger
Comparator x 32
Equal

PR3 PR2

0
T3IF
Event Flag 1 Q D TGATE (T2CON<6>)
Q CK
TGATE
(T2CON<6>)

TGATE
TCS

TCKPS<1:0>
TON 2
T2CK 1x

Prescaler
Gate 1, 8, 64, 256
Sync 01

TCY
00

Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.

DS70150D-page 70 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 10-2: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6015
Data Bus<15:0>

TMR3HLD
16
16
Write TMR2
Read TMR2

16

Reset
TMR3 TMR2 Sync

MSB LSB
ADC Event Trigger
Comparator x 32
Equal

PR3 PR2

0
T3IF
Event Flag 1 Q D TGATE(T2CON<6>)
Q CK
TGATE
(T2CON<6>)

TGATE
TCS
TCKPS<1:0>
TON 2
1x

Prescaler
Gate 1, 8, 64, 256
Sync 01

TCY
00

Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.

© 2008 Microchip Technology Inc. DS70150D-page 71

dsPIC30F6010A/6015
FIGURE 10-3: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR dsPIC30F6010A

PR2

Equal
Comparator x 16

TMR2 Sync
Reset

0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE

TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1x

Gate Prescaler
Sync 01 1, 8, 64, 256

TCY 00

FIGURE 10-4: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR dsPIC30F6015

PR2

Equal
Comparator x 16

TMR2 Sync
Reset

0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS

TCKPS<1:0>
TON 2
1x

Gate Prescaler
Sync 01 1, 8, 64, 256

TCY 00

Note: The dsPIC30F6015 does not have an external pin input to TIMER2. The following modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)

DS70150D-page 72 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 10-5: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER)

PR3

ADC Event Trigger Equal

Comparator x 16

TMR3
Reset

0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE

TGATE
TCS
TCKPS<1:0>
TON 2
Sync 1x

Prescaler
01 1, 8, 64, 256

TCY 00

Note: The dsPIC30F6010A/6015 devices do not have an external pin input to Timer3. These modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)

© 2008 Microchip Technology Inc. DS70150D-page 73

dsPIC30F6010A/6015
10.1 Timer Gate Operation 10.4 Timer Operation During Sleep
The 32-bit timer can be placed in the Gated Time
Mode
Accumulation mode. This mode allows the internal TCY During CPU Sleep mode, the timer will not operate,
to increment the respective timer when the gate input because the internal clocks are disabled.
signal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in 10.5 Timer Interrupt
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be The 32-bit timer module can generate an interrupt on
enabled (TON = 1) and the timer clock source set to period match, or on the falling edge of the external gate
internal (TCS = 0). signal. When the 32-bit timer count matches the
The falling edge of the external signal terminates the respective 32-bit period register, or the falling edge of
count operation, but does not reset the timer. The user the external “gate” signal is detected, the T3IF bit
must reset the timer in order to start counting from zero. (IFS0<7>) is asserted and an interrupt will be
generated if enabled. In this mode, the T3IF interrupt
flag is used as the source of the interrupt. The T3IF bit
10.2 ADC Event Trigger must be cleared in software.
When a match occurs between the 32-bit timer Enabling an interrupt is accomplished via the
(TMR3/TMR2) and the 32-bit combined period register respective Timer Interrupt Enable bit, T3IE (IEC0<7>).
(PR3/PR2), a special ADC trigger event signal is
generated by Timer3.

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler
operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• clearing either of the TON (T2CON<15> or
T3CON<15>) bits to ‘0’
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.

DS70150D-page 74 © 2008 Microchip Technology Inc.

 TABLE 10-1: TIMER2/3 REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu
TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu
PR2 010C Period Register 2 1111 1111 1111 1111
PR3 010E Period Register 3 1111 1111 1111 1111
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 75
dsPIC30F6010A/6015
NOTES:

DS70150D-page 76 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
11.0 TIMER4/5 MODULE Figure 11-2 and Figure 11-3 show Timer4/5 configured
as two independent 16-bit timers, Timer4 and Timer5,
Note: This data sheet summarizes features of respectively.
this group of dsPIC30F devices and is not
Note: Timer4 is a Type B timer and Timer5 is a
intended to be a complete reference
Type C timer. Please refer to the
source. For more information on the CPU,
appropriate timer type in Section 24.0
peripherals, register descriptions and
"Electrical Characteristics" of this
general device functionality, refer to the
document.
“dsPIC30F Family Reference Manual”
(DS70046). The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some
This section describes the second 32-bit General differences, which are listed below:
Purpose (GP) Timer module (Timer4/5) and associated
operational modes. Figure 11-1 depicts the simplified • The Timer4/5 module does not support the ADC
block diagram of the 32-bit Timer4/5 Module. Event Trigger feature

FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM

Data Bus<15:0>

TMR5HLD
16
16
Write TMR4

Read TMR4

16

Reset
TMR5 TMR4 Sync

MSB LSB

Comparator x 32
Equal

PR5 PR4

0
T5IF
Event Flag
1 Q D TGATE(T4CON<6>)
Q CK
TGATE
TGATE

(T4CON<6>)
TCS

TCKPS<1:0>
TON 2
T4CK 1x

Prescaler
Gate 1, 8, 64, 256
0 1
Sync

TCY 00

Note: Timer Configuration bit T45, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All
control bits are respective to the T4CON register.

© 2008 Microchip Technology Inc. DS70150D-page 77

dsPIC30F6010A/6015
FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER)

PR4

Equal
Comparator x 16

TMR4 Sync
Reset

0
T4IF
Event Flag 1 Q D TGATE

Q CK
TGATE

TGATE
TCS
TCKPS<1:0>
TON 2
T4CK 1x

Gate Prescaler
Sync 01 1, 8, 64, 256

TCY 00

FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER)

PR5

ADC Event Trigger Equal

Comparator x 16

TMR5
Reset

0
T5IF
Event Flag 1 Q D TGATE

Q CK
TGATE
TGATE
TCS

TCKPS<1:0>
TON 2
Sync 1x

Prescaler
01 1, 8, 64, 256

TCY 00

Note: The dsPIC30F6010A/6015 devices do not have an external pin input to Timer5. These modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)

DS70150D-page 78 © 2008 Microchip Technology Inc.

 TABLE 11-1: TIMER4/5 REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR4 0114 Timer4 Register uuuu uuuu uuuu uuuu

TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) uuuu uuuu uuuu uuuu
TMR5 0118 Timer5 Register uuuu uuuu uuuu uuuu
PR4 011A Period Register 4 1111 1111 1111 1111
PR5 011C Period Register 5 1111 1111 1111 1111
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 0000 0000 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 79
dsPIC30F6010A/6015
NOTES:

DS70150D-page 80 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
12.0 INPUT CAPTURE MODULE 12.1 Simple Capture Event Mode
Note: This data sheet summarizes features of The simple capture events in the dsPIC30F product
this group of dsPIC30F devices and is not family are:
intended to be a complete reference • Capture every falling edge
source. For more information on the CPU, • Capture every rising edge
peripherals, register descriptions and • Capture every 4th rising edge
general device functionality, refer to the • Capture every 16th rising edge
“dsPIC30F Family Reference Manual” • Capture every rising and falling edge
(DS70046).
These simple Input Capture modes are configured by
This section describes the input capture module and setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
associated operational modes. The features provided by
this module are useful in applications requiring 12.1.1 CAPTURE PRESCALER
frequency (period) and pulse measurement. Figure 12-1 There are four input capture prescaler settings,
depicts a block diagram of the input capture module. specified by bits ICM<2:0> (ICxCON<2:0>). Whenever
Input capture is useful for such modes as: the capture channel is turned off, the prescaler counter
• Frequency/Period/Pulse Measurements will be cleared. In addition, any Reset will clear the
• Additional sources of External Interrupts prescaler counter.

The key operational features of the input capture

module are:
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where
x = 1,2,...,N). The dsPIC30F6010A and dsPIC30F6015
devices have eight capture channels.

FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module T2_CNT T3_CNT

16 16

ICx ICTMR
Pin 1 0
Edge FIFO
Prescaler Clock Detection R/W
1, 4, 16 Synchronizer Logic Logic

3 ICM<2:0> ICxBUF
Mode Select
ICBNE, ICOV

ICI<1:0>
Interrupt
ICxCON Logic

Data Bus Set Flag

ICxIF

Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.

© 2008 Microchip Technology Inc. DS70150D-page 81

dsPIC30F6010A/6015
12.1.2 CAPTURE BUFFER OPERATION 12.2 Input Capture Operation During
Each capture channel has an associated FIFO buffer, Sleep and Idle Modes
which is four 16-bit words deep. There are two status
An input capture event will generate a device wake-up
flags, which provide status on the FIFO buffer:
or interrupt, if enabled, if the device is in CPU Idle or
• ICBNE – Input Capture Buffer Not Empty Sleep mode.
• ICOV – Input Capture Overflow Independent of the timer being enabled, the input
The ICBFNE will be set on the first input capture event capture module will wake-up from the CPU Sleep or Idle
and remain set until all capture events have been read mode when a capture event occurs, if ICM<2:0> = 111
from the FIFO. As each word is read from the FIFO, the and the interrupt enable bit is asserted. The same wake-
remaining words are advanced by one position within up can generate an interrupt, if the conditions for pro-
the buffer. cessing the interrupt have been satisfied. The wake-up
feature is useful as a method of adding extra external pin
In the event that the FIFO is full with four capture
interrupts.
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
12.2.1 INPUT CAPTURE IN CPU SLEEP
ICOV bit will be set to a logic ‘1’. The fifth capture event
MODE
is lost and is not stored in the FIFO. No additional
events will be captured till all four events have been CPU Sleep mode allows input capture module
read from the buffer. operation with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
If a FIFO read is performed after the last read and no
input capture module can only function as an external
new capture event has been received, the read will
interrupt source.
yield indeterminate results.
The capture module must be configured for interrupt
12.1.3 TIMER2 AND TIMER3 SELECTION only on the rising edge (ICM<2:0> = 111), in order for
MODE the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
Each capture channel can select between one of two
are not applicable in this mode.
timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished 12.2.2 INPUT CAPTURE IN CPU IDLE
through SFR bit ICTMR (ICxCON<7>). Timer3 is the MODE
default timer resource available for the input capture
CPU Idle mode allows input capture module operation
module.
with full functionality. In the CPU Idle mode, the Interrupt
12.1.4 HALL SENSOR MODE mode selected by the ICI<1:0> bits is applicable, as well
as the 4:1 and 16:1 capture prescale settings, which are
When the input capture module is set for capture on defined by control bits ICM<2:0>. This mode requires
every edge, rising and falling, ICM<2:0> = 001, the the selected timer to be enabled. Moreover, the ICSIDL
following operations are performed by the input bit must be asserted to a logic ‘0’.
capture logic:
If the input capture module is defined as
• The input capture interrupt flag is set on every ICM<2:0> = 111 in CPU Idle mode, the input capture
edge, rising and falling. pin will serve only as an external interrupt pin.
• The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored, since every capture 12.3 Input Capture Interrupts
generates an interrupt.
• A capture overflow condition is not generated in The input capture channels have the ability to generate
this mode. an interrupt, based upon the selected number of
capture events. The selection number is set by control
bits ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective Capture Channel Interrupt Flag is located in
the corresponding IFSx STATUS register.
Enabling an interrupt is accomplished via the
respective Capture Channel Interrupt Enable (ICxIE)
bit. The Capture Interrupt Enable bit is located in the
corresponding IEC Control register.

DS70150D-page 82 © 2008 Microchip Technology Inc.

 TABLE 12-1: INPUT CAPTURE REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu

IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu

IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu

IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu

IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu

IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu

IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 83
dsPIC30F6010A/6015
NOTES:

DS70150D-page 84 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
13.0 OUTPUT COMPARE MODULE The key operational features of the output compare
module include:
Note: This data sheet summarizes features of • Timer2 and Timer3 Selection mode
this group of dsPIC30F devices and is not
• Simple Output Compare Match mode
intended to be a complete reference
source. For more information on the CPU, • Dual Output Compare Match mode
peripherals, register descriptions and • Simple PWM mode
general device functionality, refer to the • Output Compare during Sleep and Idle modes
“dsPIC30F Family Reference Manual” • Interrupt on Output Compare/PWM Event
(DS70046).
These operating modes are determined by setting the
This section describes the output compare module and appropriate bits in the 16-bit OCxCON SFR (where
associated operational modes. The features provided x = 1,2,3,...,N). The dsPIC30F6010A and
by this module are useful in applications requiring dsPIC30F6015 devices have eight compare channels.
operational modes such as:
OCxRS and OCxR in Figure 13-1 represent the Dual
• Generation of Variable Width Output Pulses Compare registers. In the Dual Compare mode, the
• Power Factor Correction OCxR register is used for the first compare and OCxRS
is used for the second compare.
Figure 13-1 depicts a block diagram of the output
compare module.

FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR Output S Q OCx

Logic R

3 Output Enable

OCM<2:0>
Comparator Mode Select OCFA
(for x = 1, 2, 3 or 4)
OCTSEL
0 1 0 1 or OCFB
(for x = 5, 6, 7 or 8)

From GP Timer Module

TMR2<15:0 TMR3<15:0> T2P2_MATCH T3P3_MATCH

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.

© 2008 Microchip Technology Inc. DS70150D-page 85

dsPIC30F6010A/6015
13.1 Timer2 and Timer3 Selection Mode 13.3.2 CONTINUOUS PULSE MODE
Each output compare channel can select between one For the user to configure the module for the generation
of two 16-bit timers; Timer2 or Timer3. of a continuous stream of output pulses, the following
steps are required:
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource • Determine instruction cycle time TCY.
for the Output Compare module. • Calculate desired pulse value based on TCY.
• Calculate timer to start pulse width from timer start
13.2 Simple Output Compare Match value of 0x0000.
Mode • Write pulse-width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
When control bits OCM<2:0> (OCxCON<2:0>) = 001, Compare registers, respectively.
010 or 011, the selected output compare channel is
• Set Timer Period register to value equal to, or
configured for one of three simple output compare
greater than, value in OCxRS Compare register.
match modes:
• Set OCM<2:0> = 101.
• Compare forces I/O pin low
• Enable timer, TON (TxCON<15>) = 1.
• Compare forces I/O pin high
• Compare toggles I/O pin 13.4 Simple PWM Mode
The OCxR register is used in these modes. The OCxR
When control bits OCM<2:0> (OCxCON<2:0>) = 110
register is loaded with a value and is compared to the
or 111, the selected output compare channel is
selected incrementing timer count. When a compare
configured for the PWM mode of operation. When
occurs, one of these compare match modes occurs. If
configured for the PWM mode of operation, OCxR is
the counter resets to zero before reaching the value in
the main latch (read-only) and OCxRS is the secondary
OCxR, the state of the OCx pin remains unchanged.
latch. This enables glitchless PWM transitions.

13.3 Dual Output Compare Match Mode The user must perform the following steps in order to
configure the output compare module for PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation:
or 101, the selected output compare channel is
1. Set the PWM period by writing to the appropriate
configured for one of two Dual Output Compare modes,
period register.
which are:
2. Set the PWM duty cycle by writing to the OCxRS
• Single Output Pulse mode register.
• Continuous Output Pulse mode 3. Configure the output compare module for PWM
operation.
13.3.1 SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1.
of a single output pulse, the following steps are
required (assuming timer is off): 13.4.1 INPUT PIN FAULT PROTECTION
• Determine instruction cycle time TCY. FOR PWM
• Calculate desired pulse-width value based on When control bits OCM<2:0> (OCxCON<2:0>) = 111,
TCY. the selected output compare channel is again
• Calculate time to start pulse from timer start value configured for the PWM mode of operation, with the
of 0x0000. additional feature of input Fault protection. While in this
• Write pulse-width start and stop times into OCxR mode, if a logic ‘0’ is detected on the OCFA/B pin, the
and OCxRS Compare registers (x denotes respective PWM output pin is placed in the
channel 1, 2, ...,N). high-impedance input state. The OCFLT bit
(OCxCON<4>) indicates whether a Fault condition has
• Set Timer Period register to value equal to, or
occurred. This state will be maintained until both of the
greater than, value in OCxRS Compare register.
following events have occurred:
• Set OCM<2:0> = 100.
• The external Fault condition has been removed.
• Enable timer, TON (TxCON<15>) = 1.
• The PWM mode has been re-enabled by writing
To initiate another single pulse, issue another write to to the appropriate control bits.
set OCM<2:0> = 100.

DS70150D-page 86 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
13.4.2 PWM PERIOD When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
The PWM period is specified by writing to the PRx
the next increment cycle:
register. The PWM period can be calculated using
Equation 13-1. • TMRx is cleared.
• The OCx pin is set.
EQUATION 13-1: PWM PERIOD - Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
PWM Period = [(PRx) + 1] • 4 • TOSC •
(TMRx Prescale Value) - Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
• The PWM duty cycle is latched from OCxRS into
PWM frequency is defined as 1/[PWM period]. OCxR.
• The corresponding timer interrupt flag is set.
See Figure 13-2 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.

FIGURE 13-2: PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3 TMR3 = PR3

T3IF = 1 T3IF = 1
(Interrupt Flag) (Interrupt Flag)
OCxR = OCxRS OCxR = OCxRS
TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR)

13.5 Output Compare Operation During 13.7 Output Compare Interrupts

CPU Sleep Mode The output compare channels have the ability to
When the CPU enters the Sleep mode, all internal generate an interrupt on a compare match, for
clocks are stopped. Therefore, when the CPU enters whichever match mode has been selected.
the Sleep state, the output compare channel will drive For all modes except the PWM mode, when a compare
the pin to the active state that was observed prior to event occurs, the respective interrupt flag (OCxIF) is
entering the CPU Sleep state. asserted and an interrupt will be generated, if enabled.
For example, if the pin was high when the CPU The OCxIF bit is located in the corresponding IFS
entered the Sleep state, the pin will remain high. STATUS register and must be cleared in software. The
Likewise, if the pin was low when the CPU entered the interrupt is enabled via the respective Compare
Sleep state, the pin will remain low. In either case, the Interrupt Enable (OCxIE) bit, located in the
output compare module will resume operation when corresponding IEC Control register.
the device wakes up. For the PWM mode, when an event occurs, the
respective Timer Interrupt Flag (T2IF or T3IF) is
13.6 Output Compare Operation During asserted and an interrupt will be generated, if enabled.
CPU Idle Mode The IF bit is located in the IFS0 STATUS register, and
must be cleared in software. The interrupt is enabled
When the CPU enters the Idle mode, the output via the respective Timer Interrupt Enable bit (T2IE or
compare module can operate with full functionality. T3IE), located in the IEC0 Control register. The output
The output compare channel will operate during the compare interrupt flag is never set during the PWM
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at mode of operation.
logic 0 and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic 0.

© 2008 Microchip Technology Inc. DS70150D-page 87

 TABLE 13-1: OUTPUT COMPARE REGISTER MAP(1)
DS70150D-page 88

dsPIC30F6010A/6015
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC5RS 0198 Output Compare 5 Secondary Register 0000 0000 0000 0000
OC5R 019A Output Compare 5 Main Register 0000 0000 0000 0000
OC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC6RS 019E Output Compare 6 Secondary Register 0000 0000 0000 0000
OC6R 01A0 Output Compare 6 Main Register 0000 0000 0000 0000
OC6CON 01A2 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC7RS 01A4 Output Compare 7 Secondary Register 0000 0000 0000 0000
OC7R 01A6 Output Compare 7 Main Register 0000 0000 0000 0000
OC7CON 01A8 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC8RS 01AA Output Compare 8 Secondary Register 0000 0000 0000 0000
OC8R 01AC Output Compare 8 Main Register 0000 0000 0000 0000
OC8CON 01AE — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F6010A/6015
14.0 QUADRATURE ENCODER The operational features of the QEI include:
INTERFACE (QEI) MODULE • Three input channels for two phase signals and
index pulse
Note: This data sheet summarizes features of • 16-bit up/down position counter
this group of dsPIC30F devices and is not
• Count direction status
intended to be a complete reference
source. For more information on the CPU, • Position Measurement (x2 and x4) mode
peripherals, register descriptions and • Programmable digital noise filters on inputs
general device functionality, refer to the • Alternate 16-bit Timer/Counter mode
“dsPIC30F Family Reference Manual” • Quadrature Encoder Interface interrupts
(DS70046).
These operating modes are determined by setting the
This section describes the Quadrature Encoder Interface appropriate bits, QEIM<2:0> (QEICON<10:8>).
(QEI) module and associated operational modes. The Figure 14-1 depicts the Quadrature Encoder Interface
QEI module provides the interface to incremental block diagram.
encoders for obtaining mechanical position data.

FIGURE 14-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM

TQCKPS<1:0>
Sleep Input TQCS
2
TCY
0
Synchronize
Prescaler
Det 1 1, 8, 64, 256

1
QEIM<2:0>
0

QEIIF
D Q
TQGATE Event
CK Q Flag

16-bit Up/Down Counter

Programmable 2 (POSCNT)
QEA
Digital Filter Quadrature Reset
Encoder
UPDN_SRC Interface Logic
Comparator/
Zero Detect Equal
QEICON<11> 3
0
QEIM<2:0>
1 Mode Select
Max Count Register
(MAXCNT)

Programmable
QEB
Digital Filter

Programmable
INDX
Digital Filter

3
PCDOUT

0 Existing Pin Logic

UPDN
Up/Down
1

© 2008 Microchip Technology Inc. DS70150D-page 89

dsPIC30F6010A/6015
14.1 Quadrature Encoder Interface If the POSRES bit is set to ‘1’, then the position counter
Logic is reset when the index pulse is detected. If the
POSRES bit is set to ‘0’, then the position counter is not
A typical incremental (a.k.a. optical) encoder has three reset when the index pulse is detected. The position
outputs: Phase A, Phase B, and an index pulse. These counter will continue counting up or down, and will be
signals are useful and often required in position and reset on the rollover or underflow condition.
speed control of ACIM and SR motors.
The interrupt is still generated on the detection of the
The two channels, Phase A (QEA) and Phase B (QEB), index pulse and not on the position counter over-
have a unique relationship. If Phase A leads Phase B, flow/underflow.
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction 14.2.3 COUNT DIRECTION STATUS
(of the motor) is deemed negative or reverse. As mentioned in the previous section, the QEI logic
A third channel, termed index pulse, occurs once per generates an UPDN signal, based upon the
revolution and is used as a reference to establish an relationship between Phase A and Phase B. In addition
absolute position. The index pulse coincides with to the output pin, the state of this internal UPDN signal
Phase A and Phase B, both low. is supplied to a SFR bit, UPDN (QEICON<11>) as a
read-only bit. To place the state of this signal on an I/O
14.2 16-bit Up/Down Position Counter pin, the SFR bit, PCDOUT (QEICON<6>), must be 1.
Mode
14.3 Position Measurement Mode
The 16-bit up/down counter counts up or down on
every count pulse, which is generated by the difference There are two measurement modes which are
of the Phase A and Phase B input signals. The counter supported and are termed x2 and x4. These modes are
acts as an integrator, whose count value is proportional selected by the QEIM<2:0> mode select bits located in
to position. The direction of the count is determined by SFR QEICON<10:8>.
the UPDN signal, which is generated by the When control bits QEIM<2:0> = 100 or 101, the x2
Quadrature Encoder Interface logic. Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
14.2.1 POSITION COUNTER ERROR increment rate. Every rising and falling edge of the
CHECKING Phase A signal causes the position counter to be incre-
Position count error checking in the QEI is provided for mented or decremented. The Phase B signal is still
and indicated by the CNTERR bit (QEICON<15>). The utilized for the determination of the counter direction,
error checking only applies when the position counter just as in the x4 mode.
is configured for Reset on the Index Pulse modes Within the x2 Measurement mode, there are two
(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the variations of how the position counter is reset:
contents of the POSCNT register are compared with
1. Position counter reset by detection of index
the values (0xFFFF or MAXCNT + 1, depending on
pulse, QEIM<2:0> = 100.
direction). If these values are detected, an error condi-
tion is generated by setting the CNTERR bit and a QEI 2. Position counter reset by match with MAXCNT,
count error interrupt is generated. The QEI count error QEIM<2:0> = 101.
interrupt can be disabled by setting the CEID bit When control bits QEIM<2:0> = 110 or 111, the x4
(DFLTCON<8>). The position counter continues to Measurement mode is selected and the QEI logic looks
count encoder edges after an error has been detected. at both edges of the Phase A and Phase B input sig-
The POSCNT register continues to count up/down until nals. Every edge of both signals causes the position
a natural rollover/underflow. No interrupt is generated counter to increment or decrement.
for the natural rollover/underflow event. The CNTERR
Within the x4 Measurement mode, there are two
bit is a read/write bit and reset in software by the user.
variations of how the position counter is reset:
14.2.2 POSITION COUNTER RESET 1. Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
The Position Counter Reset Enable bit, POSRES
(QEI<2>), controls whether the position counter is reset 2. Position counter reset by match with MAXCNT,
when the index pulse is detected. This bit is only QEIM<2:0> = 111.
applicable when QEIM<2:0> = 100 or 110. The x4 Measurement mode provides for finer
resolution data (more position counts) for determining
motor position.

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 dsPIC30F6010A/6015
14.4 Programmable Digital Noise In addition, control bit, UDSRC (QEICON<0>),
Filters determines whether the timer count direction state is
based on the logic state, written into the UPDN
The digital noise filter section is responsible for control/Status bit (QEICON<11>), or the QEB pin state.
rejecting noise on the incoming quadrature signals. When UDSRC = 1, the timer count direction is
Schmitt Trigger inputs and a three-clock cycle delay controlled from the QEB pin. Likewise, when
filter combine to reject low level noise and large, short UDSRC = 0, the timer count direction is controlled by
duration noise spikes that typically occur in noise prone the UPDN bit.
applications, such as a motor system.
Note: This Timer does not support the External
The filter ensures that the filtered output signal is not Asynchronous Counter mode of operation.
permitted to change until a stable value has been If using an external clock source, the clock
registered for three consecutive clock cycles. will automatically be synchronized to the
For the QEA, QEB and INDX pins, the clock divide internal instruction cycle.
frequency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from 14.6 QEI Module Operation During CPU
the base instruction cycle TCY. Sleep Mode
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for 14.6.1 QEI OPERATION DURING CPU
all channels is disabled on POR and BOR. SLEEP MODE
The QEI module will be halted during the CPU Sleep
14.5 Alternate 16-bit Timer/Counter mode.
When the QEI module is not configured for the QEI
14.6.2 TIMER OPERATION DURING CPU
mode QEIM<2:0> = 001, the module can be configured
SLEEP MODE
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the During CPU Sleep mode, the timer will not operate,
QEICON SFR register. This timer functions identically because the internal clocks are disabled.
to Timer1. The QEA pin is used as the timer clock input.
When configured as a timer, the POSCNT register 14.7 QEI Module Operation During CPU
serves as the Timer Count register and the MAXCNT Idle Mode
register serves as the Period register. When a
Since the QEI module can function as a Quadrature
Timer/Period register match occur, the QEI interrupt
Encoder Interface, or as a 16-bit timer, the following
flag will be asserted.
section describes operation of the module in both
The only exception between the general purpose modes.
timers and this timer is the added feature of external
up/down input select. When the UPDN pin is asserted 14.7.1 QEI OPERATION DURING CPU IDLE
high, the timer will increment up. When the UPDN pin MODE
is asserted low, the timer will be decremented.
When the CPU is placed in the Idle mode, the QEI
Note: Changing the operational mode (i.e., from module will operate if the QEISIDL bit
QEI to Timer or vice versa), will not affect (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
the Timer/Position Count register contents. executing POR and BOR. For halting the QEI module
The UPDN control/Status bit (QEICON<11>) can be during the CPU Idle mode, QEISIDL should be set to
used to select the count direction state of the Timer ‘1’.
register. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.

© 2008 Microchip Technology Inc. DS70150D-page 91

dsPIC30F6010A/6015
14.7.2 TIMER OPERATION DURING CPU 14.8 Quadrature Encoder Interface
IDLE MODE Interrupts
When the CPU is placed in the Idle mode and the QEI The Quadrature Encoder Interface has the ability to
module is configured in the 16-bit Timer mode, the generate an interrupt on occurrence of the following
16-bit timer will operate if the QEISIDL bit events:
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module • Interrupt on 16-bit up/down position counter
during the CPU Idle mode, QEISIDL should be set rollover/underflow
to ‘1’. • Detection of qualified index pulse, or if CNTERR
bit is set
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been • Timer period match event (overflow/underflow)
entered. • Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 STATUS register.
Enabling an interrupt is accomplished via the
respective enable bit, QEIIE. The QEIIE bit is located in
the IEC2 Control register.

DS70150D-page 92 © 2008 Microchip Technology Inc.

 TABLE 14-1: QEI REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UDSRC 0000 0000 0000 0000
DFLTCON 0124 — — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000 0000 0000 0000
POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000
MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 93
dsPIC30F6010A/6015
NOTES:

DS70150D-page 94 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
15.0 MOTOR CONTROL PWM The PWM module has the following features:
MODULE • 8 PWM I/O pins with 4 duty cycle generators
• Up to 16-bit resolution
Note: This data sheet summarizes features of
• ‘On-the-Fly’ PWM frequency changes
this group of dsPIC30F devices and is not
intended to be a complete reference • Edge and Center-Aligned Output modes
source. For more information on the CPU, • Single Pulse Generation mode
peripherals, register descriptions and • Interrupt support for asymmetrical updates in
general device functionality, refer to the Center-Aligned mode
“dsPIC30F Family Reference Manual” • Output override control for Electrically
(DS70046). Commutative Motor (ECM) operation
This module simplifies the task of generating multiple, • ‘Special Event’ comparator for scheduling other
synchronized Pulse-Width Modulated (PWM) outputs. peripheral events
In particular, the following power and motion control • Fault pins to optionally drive each of the PWM
applications are supported by the PWM module: output pins to a defined state
• Three Phase AC Induction Motor • Duty cycle updates are configurable to be
• Switched Reluctance (SR) Motor immediate or synchronized to the PWM time base
• Brushless DC (BLDC) Motor This module contains 4 duty cycle generators,
• Uninterruptible Power Supply (UPS) numbered 1 through 4. The module has 8 PWM output
pins, numbered PWM1H/PWM1L through
PWM4H/PWM4L. The eight I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
The PWM module allows several modes of operation
which are beneficial for specific power control
applications.

© 2008 Microchip Technology Inc. DS70150D-page 95

dsPIC30F6010A/6015
FIGURE 15-1: PWM MODULE BLOCK DIAGRAM

PWMCON1
PWM Enable and Mode SFRs
PWMCON2

DTCON1 Dead-Time Control SFRs

DTCON2

FLTACON Fault Pin Control SFRs

FLTBCON

PWM Manual
OVDCON
Control SFR

PWM Generator #4

PDC4 Buffer
16-bit Data Bus

PDC4

Comparator Channel 4 Dead-Time PWM4H

Generator and
Override Logic PWM4L

PWM Generator PWM3H

PTMR Channel 3 Dead-Time
#3 Output
Generator and
Override Logic PWM3L
Driver
Comparator
Block
PWM Generator PWM2H
#2 Channel 2 Dead-Time
Generator and
PTPER Override Logic PWM2L

PWM Generator
#1 Channel 1 Dead-Time PWM1H
Generator and
PTPER Buffer Override Logic PWM1L

PTCON FLTA

FLTB

Comparator Special Event

Special Event Trigger
Postscaler
SEVTDIR

SEVTCMP PTDIR

PWM Time Base

Note: Details of PWM Generator #1, #2 and #3 not shown for clarity.

DS70150D-page 96 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
15.1 PWM Time Base 15.1.1 FREE-RUNNING MODE
The PWM time base is provided by a 15-bit timer with In the Free-Running mode, the PWM time base counts
a prescaler and postscaler. The time base is accessible upwards until the value in the Time Base Period
via the PTMR SFR. PTMR<15> is a read-only Status register (PTPER) is matched. The PTMR register is
bit, PTDIR, that indicates the present count direction of reset on the following input clock edge and the time
the PWM time base. If PTDIR is cleared, PTMR is base will continue to count upwards as long as the
counting upwards. If PTDIR is set, PTMR is counting PTEN bit remains set.
downwards. The PWM time base is configured via the When the PWM time base is in the Free-Running mode
PTCON SFR. The time base is enabled/disabled by (PTMOD<1:0> = 00), an interrupt event is generated
setting/clearing the PTEN bit in the PTCON SFR. each time a match with the PTPER register occurs and
PTMR is not cleared when the PTEN bit is cleared in the PTMR register is reset to zero. The postscaler
software. selection bits may be used in this mode of the timer to
The PTPER SFR sets the counting period for PTMR. reduce the frequency of the interrupt events.
The user must write a 15-bit value to PTPER<14:0>.
When the value in PTMR<14:0> matches the value in 15.1.2 SINGLE-SHOT MODE
PTPER<14:0>, the time base will either reset to ‘0’, or In the Single-Shot Counting mode, the PWM time base
reverse the count direction on the next occurring clock begins counting upwards when the PTEN bit is set.
cycle. The action taken depends on the operating When the value in the PTMR register matches the
mode of the time base. PTPER register, the PTMR register will be reset on the
following input clock edge and the PTEN bit will be
Note: If the Period register is set to 0x0000, the
cleared by the hardware to halt the time base.
timer will stop counting, and the interrupt
and the special event trigger will not be When the PWM time base is in the Single-Shot mode
generated, even if the special event value (PTMOD<1:0> = 01), an interrupt event is generated
is also 0x0000. The module will not update when a match with the PTPER register occurs, the
the Period register, if it is already at PTMR register is reset to zero on the following input
0x0000; therefore, the user must disable clock edge, and the PTEN bit is cleared. The postscaler
the module in order to update the Period selection bits have no effect in this mode of the timer.
register.
15.1.3 CONTINUOUS UP/DOWN
The PWM time base can be configured for four different
COUNTING MODES
modes of operation:
In the Continuous Up/Down Counting modes, the PWM
• Free-Running mode
time base counts upwards until the value in the PTPER
• Single-Shot mode register is matched. The timer will begin counting
• Continuous Up/Down Count mode downwards on the following input clock edge. The
• Continuous Up/Down Count mode with interrupts PTDIR bit in the PTMR SFR is read-only and indicates
for double updates the counting direction The PTDIR bit is set when the
timer counts downwards.
These four modes are selected by the PTMOD<1:0>
bits in the PTCON SFR. The Up/Down Counting modes In the Up/Down Counting mode (PTMOD<1:0> = 10),
support center-aligned PWM generation. The an interrupt event is generated each time the value of
Single-Shot mode allows the PWM module to support the PTMR register becomes zero and the PWM time
pulse control of certain Electronically Commutative base begins to count upwards. The postscaler selec-
Motors (ECMs). tion bits may be used in this mode of the timer to reduce
the frequency of the interrupt events.
The interrupt signals generated by the PWM time base
depend on the mode selection bits (PTMOD<1:0>) and
the postscaler bits (PTOPS<3:0>) in the PTCON SFR.

© 2008 Microchip Technology Inc. DS70150D-page 97

dsPIC30F6010A/6015
15.1.4 DOUBLE UPDATE MODE EQUATION 15-1: PWM PERIOD
In the Double Update mode (PTMOD<1:0> = 11), an
TCY • (PTPER + 1)
interrupt event is generated each time the PTMR TPWM =
register is equal to zero, as well as each time a period (PTMR Prescale Value)
match occurs. The postscaler selection bits have no
effect in this mode of the timer. If the PWM time base is configured for one of the
The Double Update mode provides two additional Up/Down Count modes, the PWM period will be given
functions to the user. First, the control loop bandwidth by Equation 15-2.
is doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical EQUATION 15-2: PWM PERIOD FOR
center-aligned PWM waveforms can be generated, UP/DOWN COUNT
which are useful for minimizing output waveform
distortion in certain motor control applications. TCY • 2 • (PTPER + 0.75)
TPWM =
Note: Programming a value of 0x0001 in the (PTMR Prescale Value)
Period register could generate a
continuous interrupt pulse, and hence, The maximum resolution (in bits) for a given device
must be avoided. oscillator and PWM frequency can be determined using
Equation 15-3:
15.1.5 PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4), has prescaler EQUATION 15-3: PWM RESOLUTION
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler log (2 • TPWM/TCY)
counter is cleared when any of the following occurs: Resolution =
log (2)
• a write to the PTMR register
• a write to the PTCON register
• any device Reset 15.3 Edge-Aligned PWM
PTMR is not cleared when PTCON is written. Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
15.1.6 PWM TIME BASE POSTSCALER Single-Shot mode. For edge-aligned PWM outputs, the
The match output of PTMR can optionally be output has a period specified by the value in PTPER
post-scaled through a 4-bit postscaler (which gives a and a duty cycle specified by the appropriate Duty Cycle
1:1 to 1:16 scaling). register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
The postscaler counter is cleared when any of the driven inactive when the value in the Duty Cycle register
following occurs: matches PTMR.
• a write to the PTMR register If the value in a particular Duty Cycle register is zero,
• a write to the PTCON register then the output on the corresponding PWM pin will be
• any device Reset inactive for the entire PWM period. In addition, the
PTMR is not cleared when PTCON is written. output on the PWM pin will be active for the entire
PWM period if the value in the Duty Cycle register is
greater than the value held in the PTPER register.
15.2 PWM Period
PTPER is a 15-bit, double-buffered register that sets the FIGURE 15-2: EDGE-ALIGNED PWM
counting period for the PWM time base. The PTPER New Duty Cycle Latched
buffer is loaded into the PTPER register at these instants:
• Free-Running and Single-Shot modes: When the PTPER
PTMR register is reset to zero after a match with
the PTPER register. PTMR
Value
• Up/Down Counting modes: When the PTMR
register is zero.
The value held in the PTPER buffer is automatically
0
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
Duty Cycle
The PWM period can be determined using
Equation 15-1: Period

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 dsPIC30F6010A/6015
15.4 Center-Aligned PWM 15.5.1 DUTY CYCLE REGISTER BUFFERS
Center-aligned PWM signals are produced by the The four PWM Duty Cycle registers are
module when the PWM time base is configured in an double-buffered to allow glitchless updates of the PWM
Up/Down Counting mode (see Figure 15-3). outputs. For each duty cycle, there is a Duty Cycle
register that is accessible by the user and a second
The PWM compare output is driven to the active state Duty Cycle register that holds the actual compare value
when the value of the Duty Cycle register matches the used in the present PWM period.
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is For edge-aligned PWM output, a new duty cycle value
driven to the inactive state when the PWM time base is will be updated whenever a match with the PTPER
counting upwards (PTDIR = 0) and the value in the register occurs and PTMR is reset. The contents of the
PTMR register matches the duty cycle value. duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is dis-
If the value in a particular Duty Cycle register is zero, abled (PTEN = 0) and the UDIS bit is cleared in
then the output on the corresponding PWM pin will be PWMCON2.
inactive for the entire PWM period. In addition, the
output on the PWM pin will be active for the entire PWM When the PWM time base is in the Up/Down Counting
period if the value in the Duty Cycle register is equal to mode, new duty cycle values are updated when the
the value held in the PTPER register. value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
FIGURE 15-3: CENTER-ALIGNED PWM
Cycle registers when the PWM time base is disabled
Period/2 (PTEN = 0).
PTPER When the PWM time base is in the Up/Down Counting
PTMR
mode with double updates, new duty cycle values are
Value
Duty updated when the value of the PTMR register is zero,
Cycle and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
0 Cycle registers when the PWM time base is disabled
(PTEN = 0).

15.5.2 DUTY CYCLE IMMEDIATE

UPDATES
Period When the Immediate Update Enable bit is set (IUE = 1),
any write to the Duty Cycle registers will update the
new duty cycle value immediately. This feature gives
15.5 PWM Duty Cycle Comparison
the option to the user to allow immediate updates of the
Units active PWM Duty Cycle registers instead of waiting for
There are four 16-bit Special Function Registers the end of the current time base period. System
(PDC1, PDC2, PDC3 and PDC4) used to specify duty stability is improved in closed loop servo applications
cycle values for the PWM module. by reducing the delay between system observation and
the issuance of system corrective commands when
The value in each Duty Cycle register determines the immediate updates are enabled (IUE = 1).
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16-bits wide. The If the PWM output is active at the time the new duty
LSb of a Duty Cycle register determines whether the cycle is written and the new duty cycle is less than the
PWM edge occurs in the beginning. Thus, the PWM current time base value, the PWM pulse width will be
resolution is effectively doubled. shortened. If the PWM output is active at the time the
new duty cycle is written and the new duty cycle is
greater than the current time base value, the PWM
pulse width will be lengthened.
If the PWM output is inactive at the time the new duty
cycle is written and the new duty cycle is greater than
the current time base value, the PWM output will
become active immediately and will remain active for
the new written duty cycle value.

© 2008 Microchip Technology Inc. DS70150D-page 99

dsPIC30F6010A/6015
15.6 Complementary PWM Operation 15.7.2 DEAD-TIME ASSIGNMENT
In the Complementary mode of operation, each pair of The DTCON2 SFR contains control bits that allow the
PWM outputs is obtained by a complementary PWM dead times to be assigned to each of the
signal. A dead time may be optionally inserted during complementary outputs. Table 15-1 summarizes the
device switching, when both outputs are inactive for a function of each dead-time selection control bit.
short period (Refer to Section 15.7 “Dead-Time
Generators”). TABLE 15-1: DEAD-TIME SELECTION BITS
In Complementary mode, the duty cycle comparison Bit Function
units are assigned to the PWM outputs as follows: DTS1A Selects PWM1L/PWM1H active edge dead time.
• PDC1 register controls PWM1H/PWM1L outputs DTS1I Selects PWM1L/PWM1H inactive edge
• PDC2 register controls PWM2H/PWM2L outputs dead time.
• PDC3 register controls PWM3H/PWM3L outputs DTS2A Selects PWM2L/PWM2H active edge dead time.
• PDC4 register controls PWM4H/PWM4L outputs DTS2I Selects PWM2L/PWM2H inactive edge
dead time.
The Complementary mode is selected for each PWM
DTS3A Selects PWM3L/PWM3H active edge dead time.
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to DTS3I Selects PWM3L/PWM3H inactive edge
dead time.
Complementary mode by default upon a device Reset.
DTS4A Selects PWM4L/PWM4H active edge dead time.
DTS4I Selects PWM4L/PWM4H inactive edge
15.7 Dead-Time Generators dead time.
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the 15.7.3 DEAD-TIME RANGES
Complementary Output mode. The PWM outputs use The amount of dead time provided by each dead-time
Push-Pull drive circuits. Due to the inability of the unit is selected by specifying the input clock prescaler
power output devices to switch instantaneously, some value and a 6-bit unsigned value. The amount of dead
amount of time must be provided between the turn off time provided by each unit may be set independently.
event of one PWM output in a complementary pair and
Four input clock prescaler selections have been
the turn on event of the other transistor.
provided to allow a suitable range of dead times, based
The PWM module allows two different dead times to be on the device operating frequency. The clock prescaler
programmed. These two dead times may be used in option may be selected independently for each of the
one of two methods described below to increase user two dead-time values. The dead-time clock prescaler
flexibility: values are selected using the DTAPS<1:0> and
• The PWM output signals can be optimized for DTBPS<1:0> control bits in the DTCON1 SFR. One of
different turn off times in the high side and low four clock prescaler options (TCY, 2 TCY, 4 TCY or 8 TCY)
side transistors in a complementary pair of may be selected for each of the dead-time values.
transistors. The first dead time is inserted After the prescaler values are selected, the dead time
between the turn off event of the lower transistor for each unit is adjusted by loading two 6-bit unsigned
of the complementary pair and the turn on event values into the DTCON1 SFR.
of the upper transistor. The second dead time is
The dead-time unit prescalers are cleared on the
inserted between the turn off event of the upper
following events:
transistor and the turn on event of the lower
transistor. • On a load of the down timer due to a duty cycle
• The two dead times can be assigned to individual comparison edge event.
PWM I/O pin pairs. This Operating mode allows • On a write to the DTCON1 or DTCON2 registers.
the PWM module to drive different transistor/load • On any device Reset.
combinations with each complementary PWM I/O
Note: The user should not modify the DTCON1
pin pair.
or DTCON2 values while the PWM
module is operating (PTEN = 1).
15.7.1 DEAD-TIME GENERATORS
Unexpected results may occur.
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-4, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.

DS70150D-page 100 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 15-4: DEAD-TIME TIMING DIAGRAM

Duty Cycle Generator

PWMxH

PWMxL

Time selected by DTSxA bit (A or B) Time selected by DTSxI bit (A or B)

15.8 Independent PWM Output 15.10 PWM Output Override

An independent PWM Output mode is required for The PWM output override bits allow the user to
driving certain types of loads. A particular PWM output manually drive the PWM I/O pins to specified logic
pair is in the Independent Output mode when the states, independent of the duty cycle comparison units.
corresponding PMOD bit in the PWMCON1 register is All control bits associated with the PWM output
set. No dead-time control is implemented between override function are contained in the OVDCON
adjacent PWM I/O pins when the module is operating register. The upper half of the OVDCON register
in the Independent mode and both I/O pins are allowed contains eight bits, POVDxH<4:1> and POVDxL<4:1>,
to be active simultaneously. that determine which PWM I/O pins will be overridden.
In the Independent mode, each duty cycle generator is The lower half of the OVDCON register contains eight
connected to both of the PWM I/O pins in an output bits, POUTxH<4:1> and POUTxL<4:1>, that determine
pair. By using the associated Duty Cycle register and the state of the PWM I/O pins when a particular output
the appropriate bits in the OVDCON register, the user is overridden via the POVD bits.
may select the following signal output options for each
PWM I/O pin operating in the Independent mode: 15.10.1 COMPLEMENTARY OUTPUT MODE
• I/O pin outputs PWM signal When a PWMxL pin is driven active via the OVDCON
• I/O pin inactive register, the output signal is forced to be the
complement of the corresponding PWMxH pin in the
• I/O pin active
pair. Dead-time insertion is still performed when PWM
channels are overridden manually.
15.9 Single-Pulse PWM Operation
The PWM module produces single pulse outputs when 15.10.2 OVERRIDE SYNCHRONIZATION
the PTCON control bits PTMOD<1:0> = 10. Only If the OSYNC bit in the PWMCON2 register is set, all
edge-aligned outputs may be produced in the output overrides performed via the OVDCON register
Single-Pulse mode. In Single-Pulse mode, the PWM are synchronized to the PWM time base. Synchronous
I/O pin(s) are driven to the active state when the PTEN output overrides occur at the following times:
bit is set. When a match with a Duty Cycle register • Edge-Aligned mode, when PTMR is zero.
occurs, the PWM I/O pin is driven to the inactive state.
• Center-Aligned modes, when PTMR is zero and
When a match with the PTPER register occurs, the
when the value of PTMR matches PTPER.
PTMR register is cleared, all active PWM I/O pins are
driven to the inactive state, the PTEN bit is cleared, and
an interrupt is generated.

© 2008 Microchip Technology Inc. DS70150D-page 101

dsPIC30F6010A/6015
15.11 PWM Output and Polarity Control 15.12.2 FAULT STATES
There are three device Configuration bits associated The FLTACON and FLTBCON Special Function
with the PWM module that provide PWM output pin Registers have eight bits each that determine the state
control: of each PWM I/O pin when it is overridden by a Fault
input. When these bits are cleared, the PWM I/O pin is
• HPOL Configuration bit driven to the inactive state. If the bit is set, the PWM I/O
• LPOL Configuration bit pin will be driven to the active state. The active and
• PWMPIN Configuration bit inactive states are referenced to the polarity defined for
These three bits in the FBORPOR Configuration each PWM I/O pin (HPOL and LPOL polarity control
register (see Section 21.6 “Device Configuration bits).
Registers”) work in conjunction with the four PWM A special case exists when a PWM module I/O pair is
Enable bits (PENxH and PENxL) located in the in the Complementary mode and both pins are
PWMCON1 SFR. The Configuration bits and PWM programmed to be active on a Fault condition. The
Enable bits ensure that the PWM pins are in the correct PWMxH pin always has priority in the Complementary
states after a device Reset occurs. The PWMPIN mode, so that both I/O pins cannot be driven active
configuration fuse allows the PWM module outputs to simultaneously.
be optionally enabled on a device Reset. If
PWMPIN = 0, the PWM outputs will be driven to their 15.12.3 FAULT PIN PRIORITY
inactive states at Reset. If PWMPIN = 1 (default), the
PWM outputs will be tri-stated. The HPOL bit specifies If both Fault input pins have been assigned to control a
the polarity for the PWMxH outputs, whereas the LPOL particular PWM I/O pin, the Fault state programmed for
bit specifies the polarity for the PWMxL outputs. the Fault A input pin will take priority over the Fault B
input pin.
15.11.1 OUTPUT PIN CONTROL
15.12.4 FAULT INPUT MODES
The PENxH and PENxL control bits in the PWMCON1
SFR enable each high PWM output pin and each low Each of the Fault input pins has two modes of
PWM output pin, respectively. If a particular PWM operation:
output pin is not enabled, it is treated as a general • Latched Mode: When the Fault pin is driven low,
purpose I/O pin. the PWM outputs will go to the states defined in
the FLTACON/FLTBCON register. The PWM
15.12 PWM Fault Pins outputs will remain in this state until the Fault pin
is driven high and the corresponding interrupt flag
There are two Fault pins (FLTA and FLTB) associated has been cleared in software. When both of these
with the PWM module. When asserted, these pins can actions have occurred, the PWM outputs will
optionally drive each of the PWM I/O pins to a defined return to normal operation at the beginning of the
state. next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the Fault condition
15.12.1 FAULT PIN ENABLE BITS ends, the PWM module will wait until the Fault pin
The FLTACON and FLTBCON SFRs each have 4 is no longer asserted, to restore the outputs.
control bits that determine whether a particular pair of • Cycle-by-Cycle Mode: When the Fault input pin
PWM I/O pins is to be controlled by the Fault input pin. is driven low, the PWM outputs remain in the
To enable a specific PWM I/O pin pair for Fault defined Fault states for as long as the Fault pin is
overrides, the corresponding bit should be set in the held low. After the Fault pin is driven high, the
FLTACON or FLTBCON register. PWM outputs return to normal operation at the
If all enable bits are cleared in the FLTACON or beginning of the following PWM cycle or
FLTBCON registers, then the corresponding Fault input half-cycle boundary.
pin has no effect on the PWM module and the pin may The Operating mode for each Fault input pin is selected
be used as a general purpose interrupt or I/O pin. using the FLTAM and FLTBM control bits in the
FLTACON and FLTBCON Special Function Registers.
Note: The Fault pin logic can operate
Each of the Fault pins can be controlled manually in
independent of the PWM logic. If all the
software.
enable bits in the FLTACON/FLTBCON
register are cleared, then the Fault pin(s)
could be used as general purpose
interrupt pin(s). Each Fault pin has an
interrupt vector, Interrupt Flag bit and
Interrupt Priority bits associated with it.

DS70150D-page 102 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
15.13 PWM Update Lockout 15.14.1 SPECIAL EVENT TRIGGER
POSTSCALER
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the Time Base The PWM special event trigger has a postscaler that
Period register, PTPER, at a given time. In some allows a 1:1 to 1:16 postscale ratio. The postscaler is
applications, it is important that all buffer registers be configured by writing the SEVOPS<3:0> control bits in
written before the new duty cycle and period values are the PWMCON2 SFR.
loaded for use by the module. The special event output postscaler is cleared on the
The PWM update lockout feature is enabled by setting following events:
the UDIS control bit in the PWMCON2 SFR. The UDIS • Any write to the SEVTCMP register
bit affects all Duty Cycle Buffer registers and the PWM • Any device Reset
time base period buffer, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
15.15 PWM Operation During CPU Sleep
Mode
If the IUE bit is set, any change to the Duty Cycle
registers will be immediately updated regardless of the The Fault A and Fault B input pins have the ability to
UDIS bit state. The PWM Period register updates wake the CPU from Sleep mode. The PWM module
(PTPER) are not affected by the IUE control bit. generates an interrupt if either of the Fault pins is
driven low while in Sleep.
15.14 PWM Special Event Trigger
15.16 PWM Operation During CPU Idle
The PWM module has a special event trigger that
allows A/D conversions to be synchronized to the PWM
Mode
time base. The A/D sampling and conversion time may The PTCON SFR contains a PTSIDL control bit. This
be programmed to occur at any point within the PWM bit determines if the PWM module will continue to
period. The special event trigger allows the user to operate or stop when the device enters Idle mode. If
minimize the delay between the time when A/D PTSIDL = 0, the module will continue to operate. If
conversion results are acquired and the time when the PTSIDL = 1, the module will stop operation as long as
duty cycle value is updated. the CPU remains in Idle mode.
The PWM special event trigger has an SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Counting
mode, an additional control bit is required to specify the
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the
special event trigger will occur on the upward counting
cycle of the PWM time base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time base. The SEVTDIR
control bit has no effect unless the PWM time base is
configured for an Up/Down Counting mode.

© 2008 Microchip Technology Inc. DS70150D-page 103

 TABLE 15-2: 8-OUTPUT PWM REGISTER MAP(1)
DS70150D-page 104

dsPIC30F6010A/6015
SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

PTCON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000
PTMR 01C2 PTDIR PWM Timer Count Value 0000 0000 0000 0000
PTPER 01C4 — PWM Time Base Period Register 0111 1111 1111 1111
SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000
PWMCON1 01C8 — — — — PTMOD4 PTMOD3 PTMOD2 PTMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L 0000 0000 1111 1111
PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC DTBPS<1:0> Dead-Time B Value DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
DTCON2 01CE — — — — — — — — DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000
FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — FAEN4 FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — FBEN4 FBEN3 FBEN2 FBEN1 0000 0000 0000 0000
OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
PDC1 01D6 PWM Duty Cycle 1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle 2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle 3 Register 0000 0000 0000 0000
PDC4 01DC PWM Duty Cycle 4 Register 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F6010A/6015
16.0 SPI MODULE Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
Note: This data sheet summarizes features of is completed, the contents of the shift register
this group of dsPIC30F devices and is not (SPIxSR) is moved to the receive buffer. If any
intended to be a complete reference transmit data has been written to the buffer register,
source. For more information on the CPU, the contents of the transmit buffer are moved to
peripherals, register descriptions and SPIxSR. The received data is thus placed in SPIxBUF
general device functionality, refer to the and the transmit data in SPIxSR is ready for the next
“dsPIC30F Family Reference Manual” transfer.
(DS70046).
Note: Both the transmit buffer (SPIxTXB) and
The Serial Peripheral Interface (SPI) module is a the receive buffer (SPIxRXB) are mapped
synchronous serial interface. It is useful for to the same register address, SPIxBUF.
communicating with other peripheral devices such as
In Master mode, the clock is generated by prescaling
EEPROMs, shift registers, display drivers and A/D
the system clock. Data is transmitted as soon as a
converters, or other microcontrollers. It is compatible
value is written to SPIxBUF. The interrupt is generated
with Motorola’s SPI and SIOP interfaces.
at the middle of the transfer of the last bit.

16.1 Operating Function Description In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the
Each SPI module consists of a 16-bit shift register, interrupt is generated when the last bit is latched. If
SPIxSR (where x = 1 or 2), used for shifting data in SSx control is enabled, then transmission and
and out, and a buffer register, SPIxBUF. A control reception are enabled only when SSx = low. The
register, SPIxCON, configures the module. SDOx output will be disabled in SSx mode with SSx
Additionally, a STATUS register, SPIxSTAT, indicates high.
various status conditions. The clock provided to the module is (FOSC/4). This
The serial interface consists of 4 pins: SDIx (Serial clock is then prescaled by the primary (PPRE<1:0>)
Data Input), SDOx (Serial Data Output), SCKx (Shift and the secondary (SPRE<2:0>) prescale factors. The
Clock Input or Output) and SSx (active-low Slave CKE bit determines whether transmit occurs on
Select). transition from active clock state to Idle clock state, or
In Master mode operation, SCK is a clock output, but vice versa. The CKP bit selects the Idle state (high or
in Slave mode, it is a clock input. low) for the clock.

A series of eight (8) or sixteen (16) clock pulses shifts 16.1.1 WORD AND BYTE
out bits from the SPIxSR to SDOx pin and COMMUNICATION
simultaneously shifts in data from SDIx pin. An
interrupt is generated when the transfer is complete A control bit, MODE16 (SPIxCON<10>), allows the
and the corresponding interrupt flag bit (SPI1IF or module to communicate in either 16-bit or 8-bit mode.
SPI2IF) is set. This interrupt can be disabled through 16-bit operation is identical to 8-bit operation, except
an interrupt enable bit (SPI1IE or SPI2IE). that the number of bits transmitted is 16 instead of 8.

The receive operation is double-buffered. When a The user software must disable the module prior to
complete byte is received, it is transferred from changing the MODE16 bit. The SPI module is reset
SPIxSR to SPIxBUF. when the MODE16 bit is changed by the user.

If the receive buffer is full when new data is being A basic difference between 8-bit and 16-bit operation is
transferred from SPIxSR to SPIxBUF, the module will that the data is transmitted out of bit 7 of the SPIxSR for
set the SPIROV bit, indicating an overflow condition. 8-bit operation, and data is transmitted out of bit 15 of
The transfer of the data from SPIxSR to SPIxBUF will the SPIxSR for 16-bit operation. In both modes, data is
not be completed and the new data will be lost. The shifted into bit 0 of the SPIxSR.
module will not respond to SCL transitions while
16.1.2 SDOx DISABLE
SPIROV is ‘1’, effectively disabling the module until
SPIxBUF is read by user software. A control bit, DISSDO, is provided to the SPIxCON
register to allow the SDOx output to be disabled. This
Note: The user must perform reads of SPIxBUF will allow the SPI module to be connected in an input
if the module is used in a transmit only only configuration. SDO can also be used for general
configuration to avoid a receive overflow purpose I/O.
condition. (SPIROV = 1)

© 2008 Microchip Technology Inc. DS70150D-page 105

dsPIC30F6010A/6015
FIGURE 16-1: SPI BLOCK DIAGRAM

Internal
Data Bus
Read Write

SPIxBUF SPIxBUF

Receive Transmit

SPIxSR
SDIx bit 0

SDOx Shift
clock
SS & FSYNC Clock Edge
Control Select
Control
SSx
Secondary Primary
Prescaler Prescaler FCY
1:1-1:8 1, 4, 16, 64
SCKx

Enable Master Clock

Note: x = 1 or 2.

FIGURE 16-2: SPI MASTER/SLAVE CONNECTION

SPI Master SPI Slave

SDOx SDIy

Serial Input Buffer Serial Input Buffer

(SPIxBUF) (SPIyBUF)

Shift Register SDIx SDOy Shift Register

(SPIxSR) (SPIySR)

MSb LSb MSb LSb

Serial Clock
SCKx SCKy
PROCESSOR 1 PROCESSOR 2

Note: x = 1 or 2, y = 1 or 2.

DS70150D-page 106 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
16.2 Framed SPI Support 16.4 SPI Operation During CPU Sleep
The module supports a basic framed SPI protocol in
Mode
Master or Slave mode. The control bit, FRMEN, During Sleep mode, the SPI module is shut down. If
enables framed SPI support and causes the SSx pin to the CPU enters Sleep mode while an SPI transaction
perform the Frame Synchronization pulse (FSYNC) is in progress, then the transmission and reception is
function. The control bit SPIFSD determines whether aborted.
the SSx pin is an input or an output (i.e., whether the
The transmitter and receiver will stop in Sleep mode.
module receives or generates the Frame
However, register contents are not affected by
Synchronization pulse). The frame pulse is an
entering or exiting Sleep mode.
active-high pulse for a single SPI clock cycle. When
Frame Synchronization is enabled, the data transmis-
sion starts only on the subsequent transmit edge of the 16.5 SPI Operation During CPU Idle
SPI clock. Mode
When the device enters Idle mode, all clock sources
16.3 Slave Select Synchronization remain functional. The SPISIDL bit (SPIxSTAT<13>)
The SSx pin allows a Synchronous Slave mode. The selects if the SPI module will stop or continue on Idle.
SPI must be configured in SPI Slave mode, with SSx If SPISIDL = 0, the module will continue to operate
pin control enabled (SSEN = 1). When the SSx pin is when the CPU enters Idle mode. If SPISIDL = 1, the
low, transmission and reception are enabled, and the module will stop when the CPU enters Idle mode.
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is
re-synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb,
even if SSx had been de-asserted in the middle of a
transmit/receive.

© 2008 Microchip Technology Inc. DS70150D-page 107

 TABLE 16-1: SPI1 REGISTER MAP(1)
DS70150D-page 108

dsPIC30F6010A/6015
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 16-2: SPI2 REGISTER MAP(1)

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SPI2STAT 0226 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000
SPI2CON 0228 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI2BUF 022A Transmit and Receive Buffer 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2008 Microchip Technology Inc.
 dsPIC30F6010A/6015
17.0 I2C™ MODULE 17.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • I2C Slave operation with 7-bit address
intended to be a complete reference • I2C Slave operation with 10-bit address
source. For more information on the CPU, • I2C Master operation with 7 or 10-bit address
peripherals, register descriptions and See the I2C programmer’s model in Figure 17-1.
general device functionality, refer to the
“dsPIC30F Family Reference Manual” 17.1.2 PIN CONFIGURATION IN I2C MODE
(DS70046).
I2C has a 2-pin interface; pin SCL is clock and pin SDA
2 is data.
The Inter-Integrated Circuit™ (I C™) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication 17.1.3 I2C REGISTERS
standard, with a 16-bit interface. I2CCON and I2CSTAT are control and STATUS
This module offers the following key features: registers, respectively. The I2CCON register is
readable and writable. The lower 6 bits of I2CSTAT are
• I2C interface supporting both Master and Slave
read-only. The remaining bits of the I2CSTAT are
operation.
read/write.
• I2C Slave mode supports 7 and 10-bit address.
I2CRSR is the shift register used for shifting data,
• I2C Master mode supports 7 and 10-bit address.
whereas I2CRCV is the buffer register to which data
• I2C port allows bidirectional transfers between bytes are written, or from which data bytes are read.
master and slaves. I2CRCV is the receive buffer, as shown in Figure 16-1.
• Serial clock synchronization for I2C port can be I2CTRN is the transmit register to which bytes are written
used as a handshake mechanism to suspend and during a transmit operation, as shown in Figure 16-2.
resume serial transfer (SCLREL control).
The I2CADD register holds the slave address. A Status
• I2C supports multi-master operation; detects bus bit, ADD10, indicates 10-bit Address mode. The
collision and will arbitrate accordingly. I2CBRG acts as the Baud Rate Generator reload
value.
17.1 Operating Function Description In receive operations, I2CRSR and I2CRCV together
The hardware fully implements all the master and form a double-buffered receiver. When I2CRSR receives
slave functions of the I2C Standard and Fast mode a complete byte, it is transferred to I2CRCV and an
specifications, as well as 7 and 10-bit addressing. interrupt pulse is generated. During transmission, the
I2CTRN is not double-buffered.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus. Note: Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.

FIGURE 17-1: PROGRAMMER’S MODEL

I2CRCV (8 bits)
bit 7 bit 0

I2CTRN (8 bits)
bit 7 bit 0
I2CBRG (9 bits)
bit 8 bit 0
I2CCON (16 bits)
bit 15 bit 0
I2CSTAT (16 bits)
bit 15 bit 0
I2CADD (10 bits)
bit 9 bit 0

© 2008 Microchip Technology Inc. DS70150D-page 109

dsPIC30F6010A/6015
FIGURE 17-2: I2C™ BLOCK DIAGRAM

Internal
Data Bus

I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB

SDA Addr_Match
Match Detect

Write

I2CADD

Read

Start and
Stop bit Detect
Write

I2CSTAT
Start, Restart,
Stop bit Generate
Read
Control Logic

Collision
Detect
Write
I2CCON

Acknowledge
Read
Generation

Clock
Stretching Write

I2CTRN
Shift LSB Read
Clock

Reload
Control Write

BRG Down I2CBRG

Counter Read
FCY

DS70150D-page 110 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
17.2 I2C Module Addresses 17.3.2 SLAVE RECEPTION
The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address
addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set,
interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the
address is received, it is compared to the 7 Least ninth clock.
Significant bits of the I2CADD register.
If the RBF flag is set, indicating that I2CRCV is still
If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then
10-bit address. When an address is received, it will be ACK is not sent; however, the interrupt pulse is
compared with the binary value ‘1 1 1 1 0 A9 A8’ generated. In the case of an overflow, the contents of
(where A9, A8 are two Most Significant bits of the I2CRSR are not loaded into the I2CRCV.
I2CADD). If that value matches, the next address will
be compared with the Least Significant 8 bits of Note: The I2CRCV will be loaded if the I2COV
I2CADD, as specified in the 10-bit addressing protocol. bit = 1 and the RBF flag = 0. In this case,
a read of the I2CRCV was performed, but
TABLE 17-1: 7-BIT I2C™ SLAVE the user did not clear the state of the
ADDRESSES SUPPORTED BY I2COV bit before the next receive
occurred. The Acknowledgement is not
dsPIC30F
sent (ACK = 1) and the I2CRCV is
0x00 General call address or start byte updated.
0x01-0x03 Reserved
0x04-0x07 HS-mode Master codes 17.4 I2C 10-bit Slave Mode Operation
0x04-0x77 Valid 7-bit addresses In 10-bit mode, the basic receive and transmit
0x78-0x7b Valid 10-bit addresses (lower 7 operations are the same as in the 7-bit mode. However,
bits) the criteria for address match is more complex.
0x7c-0x7f Reserved The I2C specification dictates that a slave must be
addressed for a write operation, with two address bytes
17.3 I2C 7-bit Slave Mode Operation following a Start bit.
The A10M bit is a control bit that signifies that the
Once enabled (I2CEN = 1), the slave module will wait
address in I2CADD is a 10-bit address rather than a
for a Start bit to occur (i.e., the I2C module is ‘Idle’).
7-bit address. The address detection protocol for the
Following the detection of a Start bit, 8 bits are shifted
first byte of a message address is identical for 7-bit
into I2CRSR and the address is compared against
and 10-bit messages, but the bits being compared are
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
different.
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the I2CADD holds the entire 10-bit address. Upon receiv-
rising edge of SCL. ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
If an address match occurs, an Acknowledgement will
address) and I2CRSR<2:1> are compared against
be sent, and the Slave Event Interrupt Flag (SI2CIF) is
I2CADD<9:8>. If a match occurs and if R_W = 0, the
set on the falling edge of the ninth (ACK) bit. The
interrupt pulse is sent. The ADD10 bit will be cleared to
address match does not affect the contents of the
indicate a partial address match. If a match fails or
I2CRCV buffer or the RBF bit.
R_W = 1, the ADD10 bit is cleared and the module
17.3.1 SLAVE TRANSMISSION returns to the Idle state.

If the R_W bit received is a ‘1’, then the serial port will The low byte of the address is then received and
go into Transmit mode. It will send ACK on the ninth bit compared with I2CADD<7:0>. If an address match
and then hold SCL to ‘0’ until the CPU responds by occurs, the interrupt pulse is generated and the ADD10
writing to I2CTRN. SCL is released by setting the bit is set, indicating a complete 10-bit address match. If
SCLREL bit, and 8 bits of data are shifted out. Data bits an address match did not occur, the ADD10 bit is
are shifted out on the falling edge of SCL, such that cleared and the module returns to the Idle state.
SDA is valid during SCL high (see timing diagram). The
interrupt pulse is sent on the falling edge of the ninth
clock pulse, regardless of the status of the ACK
received from the master.

© 2008 Microchip Technology Inc. DS70150D-page 111

dsPIC30F6010A/6015
17.4.1 10-BIT MODE SLAVE 17.5.3 CLOCK STRETCHING DURING
TRANSMISSION 7-BIT ADDRESSING (STREN = 1)
Once a slave is addressed in this fashion, with the full When the STREN bit is set in Slave Receive mode,
10-bit address (this state is referred as the SCL line is held low when the buffer register is full.
“PRIOR_ADDR_MATCH”), the master can begin The method for stretching the SCL output is the same
sending data bytes for a slave reception operation. for both 7 and 10-bit addressing modes.
Clock stretching takes place following the ninth clock of
17.4.2 10-BIT MODE SLAVE RECEPTION
the receive sequence. On the falling edge of the ninth
Once addressed, the master can generate a Repeated clock at the end of the ACK sequence, if the RBF bit is
Start, reset the high byte of the address and set the set, the SCLREL bit is automatically cleared, forcing the
R_W bit without generating a Stop bit, thus initiating a SCL output to be held low. The user’s ISR must set the
slave transmit operation. SCLREL bit before reception is allowed to continue. By
holding the SCL line low, the user has time to service
17.5 Automatic Clock Stretch the ISR and read the contents of the I2CRCV before the
master device can initiate another receive sequence.
In the slave modes, the module can synchronize buffer This will prevent buffer overruns from occurring.
reads and write to the master device by clock
stretching. Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
17.5.1 TRANSMIT CLOCK STRETCHING falling edge of the ninth clock, the
Both 10-bit and 7-bit Transmit modes implement clock SCLREL bit will not be cleared and clock
stretching by asserting the SCLREL bit after the falling stretching will not occur.
edge of the ninth clock if the TBF bit is cleared, 2: The SCLREL bit can be set in software,
indicating the buffer is empty. regardless of the state of the RBF bit. The
In Slave Transmit modes, clock stretching is always user should be careful to clear the RBF bit
performed, irrespective of the STREN bit. in the ISR before the next receive
sequence in order to prevent an overflow
Clock synchronization takes place following the ninth
condition.
clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock, and if the 17.5.4 CLOCK STRETCHING DURING
TBF bit is still clear, then the SCLREL bit is
10-BIT ADDRESSING (STREN = 1)
automatically cleared. The SCLREL being cleared to
‘0’ will assert the SCL line low. The user’s ISR must Clock stretching takes place automatically during the
set the SCLREL bit before transmission is allowed to addressing sequence. Because this module has a
continue. By holding the SCL line low, the user has register for the entire address, it is not necessary for
time to service the ISR and load the contents of the the protocol to wait for the address to be updated.
I2CTRN before the master device can initiate another After the address phase is complete, clock stretching
transmit sequence. will occur on each data receive or transmit sequence
Note 1: If the user loads the contents of I2CTRN, as was described earlier.
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not 17.6 Software Controlled Clock
be cleared and clock stretching will not Stretching (STREN = 1)
occur.
When the STREN bit is ‘1’, the SCLREL bit may be
2: The SCLREL bit can be set in software, cleared by software to allow software to control the
regardless of the state of the TBF bit. clock stretching. The logic will synchronize writes to
the SCLREL bit with the SCL clock. Clearing the
17.5.2 RECEIVE CLOCK STRETCHING SCLREL bit will not assert the SCL output until the
The STREN bit in the I2CCON register can be used to module detects a falling edge on the SCL output and
enable clock stretching in Slave Receive mode. When SCL is sampled low. If the SCLREL bit is cleared by
the STREN bit is set, the SCL pin will be held low at the user while the SCL line has been sampled low, the
the end of each data receive sequence. SCL output will be asserted (held low). The SCL out-
put will remain low until the SCLREL bit is set, and all
other devices on the I2C bus have de-asserted SCL.
This ensures that a write to the SCLREL bit will not
violate the minimum high time requirement for SCL.
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.

DS70150D-page 112 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
17.7 Interrupts 17.12 I2C Master Operation
The I2C module generates two interrupt flags, MI2CIF The master device generates all of the serial clock
(I2C Master Interrupt Flag) and SI2CIF (I2C Slave pulses and the Start and Stop conditions. A transfer is
Interrupt Flag). The MI2CIF interrupt flag is activated ended with a Stop condition or with a Repeated Start
on completion of a master message event. The SI2CIF condition. Since the Repeated Start condition is also
interrupt flag is activated on detection of a message the beginning of the next serial transfer, the I2C bus will
directed to the slave. not be released.
In Master Transmitter mode, serial data is output
17.8 Slope Control through SDA, while SCL outputs the serial clock. The
The I2C standard requires slope control on the SDA first byte transmitted contains the slave address of the
and SCL signals for Fast Mode (400 kHz). The control receiving device (7 bits) and the data direction bit. In
bit, DISSLW, enables the user to disable slew rate this case, the data direction bit (R_W) is logic ‘0’. Serial
control, if desired. It is necessary to disable the slew data is transmitted 8 bits at a time. After each byte is
rate control for 1 MHz mode. transmitted, an ACK bit is received. Start and Stop
conditions are output to indicate the beginning and the
17.9 IPMI Support end of a serial transfer.
In Master Receive mode, the first byte transmitted
The control bit, IPMIEN, enables the module to support
contains the slave address of the transmitting device
Intelligent Peripheral Management Interface (IPMI).
(7 bits) and the data direction bit. In this case, the data
When this bit is set, the module accepts and acts upon
direction bit (R_W) is logic ‘1’. Thus, the first byte
all addresses.
transmitted is a 7-bit slave address, followed by a ‘1’ to
indicate receive bit. Serial data is received via SDA,
17.10 General Call Address Support while SCL outputs the serial clock. Serial data is
The general call address can address all devices. When received 8 bits at a time. After each byte is received, an
this address is used, all devices should, in theory, ACK bit is transmitted. Start and Stop conditions
respond with an acknowledgement. indicate the beginning and end of transmission.
The general call address is one of eight addresses 17.12.1 I2C MASTER TRANSMISSION
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R_W = 0. Transmission of a data byte, a 7-bit address, or the sec-
ond half of a 10-bit address is accomplished by simply
The general call address is recognized when the writing a value to I2CTRN register. The user should
General Call Enable (GCEN) bit is set only write to I2CTRN when the module is in a WAIT
(I2CCON<7> = 1). Following a Start bit detection, 8 bits state. This action will set the buffer full flag (TBF) and
are shifted into I2CRSR and the address is compared allow the Baud Rate Generator to begin counting and
with I2CADD, and is also compared with the general start the next transmission. Each bit of address/data
call address which is fixed in hardware. will be shifted out onto the SDA pin after the falling
If a general call address match occurs, the I2CRSR is edge of SCL is asserted. The Transmit Status Flag,
transferred to the I2CRCV after the eighth clock, the TRSTAT (I2CSTAT<14>), indicates that a master
RBF flag is set, and on the falling edge of the ninth bit transmit is in progress.
(ACK bit), the Master Event Interrupt Flag (MI2CIF) is
set. 17.12.2 I2C MASTER RECEPTION
When the interrupt is serviced, the source for the Master mode reception is enabled by programming the
interrupt can be checked by reading the contents of the Receive Enable (RCEN) bit (I2CCON<3>). The I2C
I2CRCV to determine if the address was module must be idle before the RCEN bit is set, other-
device-specific, or a general call address. wise the RCEN bit will be disregarded. The Baud Rate
Generator begins counting, and on each rollover, the
17.11 I2C Master Support state of the SCL pin toggles, and data is shifted in to the
I2CRSR on the rising edge of each clock.
As a Master device, six operations are supported.
• Assert a Start condition on SDA and SCL. 17.12.3 BAUD RATE GENERATOR
• Assert a Restart condition on SDA and SCL. In I2C Master mode, the reload value for the BRG is
• Write to the I2CTRN register initiating located in the I2CBRG register. When the BRG is
transmission of data/address. loaded with this value, the BRG counts down to ‘0’ and
• Generate a Stop condition on SDA and SCL. stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
• Configure the I2C port to receive data.
reloaded when the SCL pin is sampled high.
• Generate an ACK condition at the end of a
received byte of data.

© 2008 Microchip Technology Inc. DS70150D-page 113

dsPIC30F6010A/6015
As per the I2C standard, FSCL may be 100 kHz or The Master will continue to monitor the SDA and SCL
400 kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. be set.
A write to the I2CTRN will start the transmission of data
EQUATION 17-1: SERIAL CLOCK RATE at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
F CY F CY
I2CBRG = ⎛ ------------- – ---------------------------⎞ – 1 In a Multi-Master environment, the interrupt generation
⎝ F SCL 1, 111, 111⎠
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
17.12.4 CLOCK ARBITRATION register, or the bus is Idle and the S and P bits are
Clock arbitration occurs when the master de-asserts cleared.
the SCL pin (SCL allowed to float high) during any
receive, transmit, or Restart/Stop condition. When the 17.13 I2C Module Operation During CPU
SCL pin is allowed to float high, the Baud Rate
Sleep and Idle Modes
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is 17.13.1 I2C OPERATION DURING CPU
sampled high, the Baud Rate Generator is reloaded
SLEEP MODE
with the contents of I2CBRG and begins counting. This
ensures that the SCL high time will always be at least When the device enters Sleep mode, all clock sources
one BRG rollover count in the event that the clock is to the module are shutdown and stay at logic ‘0’. If
held low by an external device. Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
17.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly,
BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the
ARBITRATION reception is aborted.
Multi-Master operation support is achieved by bus 17.13.2 I2C OPERATION DURING CPU IDLE
arbitration. When the master outputs address/data bits MODE
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high For the I2C, the I2CSIDL bit selects if the module will
while another master asserts a ‘0’. When the SCL pin stop on Idle or continue on Idle. If I2CSIDL = 0, the
floats high, data should be stable. If the expected data module will continue operation on assertion of the Idle
on SDA is a ‘1’ and the data sampled on the SDA mode. If I2CSIDL = 1, the module will stop on Idle.
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted, and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service
Routine, if the I2C bus is free (i.e., the P bit is set), the
user can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are
de-asserted, and the respective control bits in the
I2CCON register are cleared to 0. When the user
services the bus collision Interrupt Service Routine,
and if the I2C bus is free, the user can resume
communication by asserting a Start condition.

DS70150D-page 114 © 2008 Microchip Technology Inc.

 TABLE 17-2: I2C™ REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000

I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111
I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000
I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000
I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000
I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 115
dsPIC30F6010A/6015
NOTES:

DS70150D-page 116 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
18.0 UNIVERSAL ASYNCHRONOUS 18.1 UART Module Overview
RECEIVER TRANSMITTER The key features of the UART module are:
(UART) MODULE • Full-duplex, 8 or 9-bit data communication
Note: This data sheet summarizes features of • Even, Odd or No Parity options (for 8-bit data)
this group of dsPIC30F devices and is not • One or two Stop bits
intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit
source. For more information on the CPU, prescaler
peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a
general device functionality, refer to the 30 MHz instruction rate
“dsPIC30F Family Reference Manual”
• 4-word deep transmit data buffer
(DS70046).
• 4-word deep receive data buffer
This section describes the Universal Asynchronous • Parity, Framing and Buffer Overrun error detection
Receiver/Transmitter Communications module.
• Support for Interrupt only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for diagnostic support

FIGURE 18-1: UART TRANSMITTER BLOCK DIAGRAM

Internal Data Bus

Control and Status bits

Write Write

UTX8 UxTXREG Low Byte Transmit Control

– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt

Load TSR
UxTXIF
UTXBRK

Data
Transmit Shift Register (UxTSR)

‘0’ (Start)
UxTX
‘1’ (Stop)

Parity 16X Baud Clock

Parity 16 Divider
Generator from Baud Rate
Generator

Control
Signals

Note: x = 1 or 2.

© 2008 Microchip Technology Inc. DS70150D-page 117

dsPIC30F6010A/6015
FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM

Internal Data Bus 16

Read Write Read Read Write

UxMODE UxSTA

URX8 UxRXREG Low Byte

Receive Buffer Control
– Generate Flags
– Generate Interrupt
– Shift Data Characters

LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control

FERR
PERR
Receive Shift Register Signals
UxRX
0 (UxRSR)

· Start bit Detect

· Parity Check
· Stop bit Detect 16 Divider
· Shift Clock Generation
· Wake Logic

16X Baud Clock from

Baud Rate Generator
UxRXIF

DS70150D-page 118 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
18.2 Enabling and Setting Up UART 18.3 Transmitting Data
18.2.1 ENABLING THE UART 18.3.1 TRANSMITTING IN 8-BIT DATA
The UART module is enabled by setting the UARTEN MODE
bit in the UxMODE register (where x = 1 or 2). Once The following steps must be performed in order to
enabled, the UxTX and UxRX pins are configured as an transmit 8-bit data:
output and an input respectively, overriding the TRIS
1. Set up the UART:
and LAT register bit settings for the corresponding I/O
First, the data length, parity and number of Stop
port pins. The UxTX pin is at logic ‘1’ when no
bits must be selected. Then, the Transmit and
transmission is taking place.
Receive Interrupt Enable and Priority bits are
setup in the UxMODE and UxSTA registers.
18.2.2 DISABLING THE UART
Also, the appropriate baud rate value must be
The UART module is disabled by clearing the written to the UxBRG register.
UARTEN bit in the UxMODE register. This is the 2. Enable the UART by setting the UARTEN bit
default state after any Reset. If the UART is disabled, (UxMODE<15>).
all I/O pins operate as port pins under the control of
3. Set the UTXEN bit (UxSTA<10>), thereby
the LAT and TRIS bits of the corresponding port pins.
enabling a transmission.
Disabling the UART module resets the buffers to
Note: The UTXEN bit must be set after the
empty states. Any data characters in the buffers are
UARTEN bit is set to enable UART
lost, and the baud rate counter is reset.
transmissions.
All error and status flags associated with the UART 4. Write the byte to be transmitted to the lower byte
module are reset when the module is disabled. The of UxTXREG. The value will be transferred to the
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and Transmit Shift Register (UxTSR) immediately
UTXBF bits are cleared, whereas RIDLE and TRMT and the serial bit stream will start shifting out
are set. Other control bits, including ADDEN, during the next rising edge of the baud clock.
URXISEL<1:0>, UTXISEL, as well as the UxMODE Alternatively, the data byte may be written while
and UxBRG registers, are not affected. UTXEN = 0, following which, the user may set
Clearing the UARTEN bit while the UART is active will UTXEN. This will cause the serial bit stream to
abort all pending transmissions and receptions and begin immediately because the baud clock will
reset the module as defined above. Re-enabling the start from a cleared state.
UART will restart the UART in the same configuration. 5. A transmit interrupt will be generated depending
on the value of the interrupt control bit UTXISEL
18.2.3 SETTING UP DATA, PARITY AND (UxSTA<15>).
STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxMODE register are 18.3.2 TRANSMITTING IN 9-BIT DATA
used to select the data length and parity used in the MODE
transmission. The data length may either be 8-bits with The sequence of steps involved in the transmission of
even, odd or no parity, or 9-bits with no parity. 9-bit data is similar to 8-bit transmission, except that a
The STSEL bit determines whether one or two Stop bits 16-bit data word (of which the upper 7 bits are always
will be used during data transmission. clear) must be written to the UxTXREG register.
The default (power-on) setting of the UART is 8 bits, no 18.3.3 TRANSMIT BUFFER (UXTXB)
parity, 1 Stop bit (typically represented as 8, N, 1).
The transmit buffer is 9-bits wide and 4 characters
deep. Including the Transmit Shift Register (UxTSR),
the user effectively has a 5-deep FIFO (First-In, First-
Out) buffer. The UTXBF Status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
If a user attempts to write to a full buffer, the new data
will not be accepted into the FIFO, and no data shift
will occur within the buffer. This enables recovery from
a buffer overrun condition.
The FIFO is reset during any device Reset, but is not
affected when the device enters or wakes up from a
Power-Saving mode.

© 2008 Microchip Technology Inc. DS70150D-page 119

dsPIC30F6010A/6015
18.3.4 TRANSMIT INTERRUPT 18.4.2 RECEIVE BUFFER (UXRXB)
The Transmit Interrupt Flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the
located in the corresponding interrupt flag register. Receive Shift Register (UxRSR), the user effectively
The transmitter generates an edge to set the UxTXIF has a 5-word deep FIFO buffer.
bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive
on UTXISEL control bit: buffer has data available. URXDA = 0 means that the
a) If UTXISEL = 0, an interrupt is generated when buffer is empty. If a user attempts to read an empty
a word is transferred from the transmit buffer to buffer, the old values in the buffer will be read and no
the Transmit Shift Register (UxTSR). This data shift will occur within the FIFO.
means that the transmit buffer has at least one The FIFO is reset during any device Reset. It is not
empty word. affected when the device enters or wakes up from a
b) If UTXISEL = 1, an interrupt is generated when Power-Saving mode.
a word is transferred from the transmit buffer to
the Transmit Shift Register (UxTSR) and the 18.4.3 RECEIVE INTERRUPT
transmit buffer is empty. The Receive Interrupt Flag (U1RXIF or U2RXIF) can
Switching between the two interrupt modes during be read from the corresponding interrupt flag register.
operation is possible and sometimes offers more The interrupt flag is set by an edge generated by the
flexibility. receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
18.3.5 TRANSMIT BREAK URXISEL<1:0> (UxSTA<7:6>) control bits.
Setting the UTXBRK bit (UxSTA<11>) will cause the a) If URXISEL<1:0> = 00 or 01, an interrupt is
UxTX line to be driven to logic ‘0’. The UTXBRK bit generated every time a data word is transferred
overrides all transmission activity. Therefore, the user from the Receive Shift Register (UxRSR) to the
should generally wait for the transmitter to be Idle receive buffer. There may be one or more
before setting UTXBRK. characters in the receive buffer.
To send a Break character, the UTXBRK bit must be b) If URXISEL<1:0> = 10, an interrupt is generated
set by software and must remain set for a minimum of when a word is transferred from the Receive
13 baud clock cycles. The UTXBRK bit is then cleared Shift Register (UxRSR) to the receive buffer,
by software to generate Stop bits. The user must wait which, as a result of the transfer, contains
for a duration of at least one or two baud clock cycles 3 characters.
in order to ensure a valid Stop bit(s) before reloading c) If URXISEL<1:0> = 11, an interrupt is set when
the UxTXB or starting other transmitter activity. a word is transferred from the Receive Shift
Transmission of a Break character does not generate Register (UxRSR) to the receive buffer, which,
a transmit interrupt. as a result of the transfer, contains 4 characters
(i.e., becomes full).
18.4 Receiving Data Switching between the interrupt modes during
operation is possible, though generally not advisable
18.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA during normal operation.
MODE
The following steps must be performed while receiving 18.5 Reception Error Handling
8-bit or 9-bit data:
18.5.1 RECEIVE BUFFER OVERRUN
1. Set up and enable the UART (see Section 18.3
ERROR (OERR BIT)
"Transmitting Data").
2. A receive interrupt will be generated when one The OERR bit (UxSTA<1>) is set if all of the following
or more data words have been received, conditions occur:
depending on the receive interrupt settings a) The receive buffer is full.
specified by the URXISEL bits (UxSTA<7:6>). b) The Receive Shift Register is full, but unable to
3. Read the OERR bit to determine if an overrun transfer the character to the receive buffer.
error has occurred. The OERR bit must be reset c) The Stop bit of the character in the UxRSR is
in software. detected, indicating that the UxRSR needs to
4. Read the received data from UxRXREG. The act transfer the character to the buffer.
of reading UxRXREG will move the next word to Once OERR is set, no further data is shifted in UxRSR
the top of the receive FIFO, and the PERR and (until the OERR bit is cleared in software or a Reset
FERR values will be updated. occurs). The data held in UxRSR and UxRXREG
remains valid.

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 dsPIC30F6010A/6015
18.5.2 FRAMING ERROR (FERR) 18.6 Address Detect Mode
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the ADDEN bit (UxSTA<5>) enables this
instead of a Stop bit. If two Stop bits are selected, both special mode, in which a 9th bit (URX8) value of ‘1’
Stop bits must be ‘1’, otherwise FERR will be set. The identifies the received word as an address rather than
read-only FERR bit is buffered along with the received data. This mode is only applicable for 9-bit data com-
data. It is cleared on any Reset. munication. The URXISEL control bit does not have
any impact on interrupt generation in this mode, since
18.5.3 PARITY ERROR (PERR) an interrupt (if enabled) will be generated every time
The PERR bit (UxSTA<3>) is set if the parity of the the received word has the 9th bit set.
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The 18.7 Loopback Mode
read-only PERR bit is buffered along with the received
data bytes. It is cleared on any Reset. Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
18.5.4 IDLE STATUS pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
When the receiver is active (i.e., between the initial
receive logic. However, the UxTX pin still functions as
detection of the Start bit and the completion of the Stop
in a normal operation.
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the
completion of the Stop bit and detection of the next To select this mode:
Start bit, the RIDLE bit is ‘1’, indicating that the UART a) Configure UART for desired mode of operation.
is Idle.
b) Set LPBACK = 1 to enable Loopback mode.
18.5.5 RECEIVE BREAK c) Enable transmission as defined in Section 18.3
“Transmitting Data”.
The receiver will count and expect a certain number of
bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
18.8 Baud Rate Generator (BRG)
bits. The UART has a 16-bit Baud Rate Generator to allow
If the break is longer than 13 bit times, the reception is maximum flexibility in baud rate generation. The Baud
considered complete after the number of bit times Rate Generator register (UxBRG) is readable and
specified by PDSEL and STSEL. The URXDA bit is writable. The baud rate is computed as follows:
set, FERR is set, zeros are loaded into the receive BRG = 16-bit value held in UxBRG register
FIFO, interrupts are generated, if appropriate, and the (0 through 65535)
RIDLE bit is set.
FCY = Instruction Clock Rate (1/TCY)
When the module receives a long break signal and the
The baud rate is given by Equation 18-1.
receiver has detected the Start bit, the data bits and
the invalid Stop bit (which sets the FERR), the receiver
must wait for a valid Stop bit before looking for the next EQUATION 18-1: BAUD RATE
Start bit. It cannot assume that the break condition on
the line is the next Start bit. Baud Rate = FCY/(16 * (BRG + 1))

Break is regarded as a character containing all ‘0’s,

with the FERR bit set. The Break character is loaded Therefore, maximum baud rate possible is
into the buffer. No further reception can occur until a FCY/16 (if BRG = 0),
Stop bit is received. Note that RIDLE goes high when
and the minimum baud rate possible is
the Stop bit has not been received yet.
FCY/(16 * 65536).
With a full 16-bit Baud Rate Generator, at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.

© 2008 Microchip Technology Inc. DS70150D-page 121

dsPIC30F6010A/6015
18.9 Auto-Baud Support 18.10.2 UART OPERATION DURING CPU
IDLE MODE
To allow the system to determine baud rates of
received characters, the input can be optionally linked For the UART, the USIDL bit selects if the module will
to a selected capture input. To enable this mode, the stop operation when the device enters Idle mode, or
user must program the input capture module to detect whether the module will continue on Idle. If USIDL = 0,
the falling and rising edges of the Start bit. the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
18.10 UART Operation During CPU
Sleep and Idle Modes
18.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is
in progress, then the transmission is aborted. The
UxTX pin is driven to logic ‘1’. Similarly, if entry into
Sleep mode occurs while a reception is in progress,
then the reception is aborted. The UxSTA, UxMODE,
Transmit and Receive registers and buffers, and the
UxBRG register are not affected by Sleep mode.
If the Wake bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select Mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from Sleep. The UARTEN
bit must be set in order to generate a wake-up
interrupt.

DS70150D-page 122 © 2008 Microchip Technology Inc.

 TABLE 18-1: UART1 REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

U1MODE 020C UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 18-2: UART2 REGISTER MAP(1)

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

U2MODE 0216 UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U2TXREG 021A — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
DS70150D-page 123
dsPIC30F6010A/6015
NOTES:

DS70150D-page 124 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
19.0 CAN MODULE • Low-Power Sleep and Idle mode
The CAN bus module consists of a protocol engine,
Note: This data sheet summarizes features of and message buffering/control. The CAN protocol
this group of dsPIC30F devices and is not engine handles all functions for receiving and
intended to be a complete reference transmitting messages on the CAN bus. Messages are
source. For more information on the CPU, transmitted by first loading the appropriate data
peripherals, register descriptions and registers. Status and errors can be checked by reading
general device functionality, refer to the the appropriate registers. Any message detected on
“dsPIC30F Family Reference Manual” the CAN bus is checked for errors and then matched
(DS70046). against filters to see if it should be received and stored
in one of the receive registers.
19.1 Overview
The Controller Area Network (CAN) module is a serial 19.2 Frame Types
interface, useful for communicating with other CAN The CAN module transmits various types of frames,
modules or microcontroller devices. This
which include data messages or remote transmission
interface/protocol was designed to allow communica-
requests initiated by the user as other frames that are
tions within noisy environments. The dsPIC30F6010A
automatically generated for control purposes. The
has two CAN modules. The dsPIC30F6015 has only
following frame types are supported:
one.
• Standard Data Frame
The CAN module is a communication controller
implementing the CAN 2.0 A/B protocol, as defined in A Standard Data Frame is generated by a node when
the BOSCH specification. The module will support the node wishes to transmit data. It includes a 11-bit
CAN 1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B Standard Identifier (SID), but not an 18-bit Extended
Active versions of the protocol. The module Identifier (EID).
implementation is a full CAN system. The CAN • Extended Data Frame
specification is not covered within this data sheet. The
reader may refer to the BOSCH CAN specification for An Extended Data Frame is similar to a Standard Data
further details. Frame, but includes an Extended Identifier as well.
The module features are as follows: • Remote Frame
• Implementation of the CAN protocol CAN 1.2, It is possible for a destination node to request the data
CAN 2.0A and CAN 2.0B from the source. For this purpose, the destination node
• Standard and extended data frames sends a Remote Frame with an identifier that matches
the identifier of the required Data Frame. The
• 0-8 bytes data length
appropriate data source node will then send a Data
• Programmable bit rate up to 1 Mbit/sec Frame as a response to this remote request.
• Support for remote frames
• Error Frame
• Double-buffered receiver with two prioritized
received message storage buffers (each buffer An Error Frame is generated by any node that detects
may contain up to 8 bytes of data) a bus error. An error frame consists of 2 fields: an Error
• 6 full (standard/extended identifier) acceptance Flag field and an Error Delimiter field.
filters, 2 associated with the high priority receive • Overload Frame
buffer, and 4 associated with the low priority
An Overload Frame can be generated by a node as a
receive buffer
result of 2 conditions. First, the node detects a
• 2 full acceptance filter masks, one each associ- dominant bit during lnterframe Space, which is an
ated with the high and low priority receive buffers illegal condition. Second, due to internal conditions, the
• Three transmit buffers with application specified node is not yet able to start reception of the next
prioritization and abort capability (each buffer may message. A node may generate a maximum of 2
contain up to 8 bytes of data) sequential Overload Frames to delay the start of the
• Programmable wake-up functionality with next message.
integrated low-pass filter
• Interframe Space
• Programmable Loopback mode supports self-test
operation Interframe Space separates a proceeding frame (of
whatever type) from a following Data or Remote
• Signaling via interrupt capabilities for all CAN
Frame.
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization

© 2008 Microchip Technology Inc. DS70150D-page 125

dsPIC30F6010A/6015
FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Mask
BUFFERS RXM1

Acceptance Filter
RXF2

Acceptance Mask Acceptance Filter A

TXB0 TXB1 TXB2 c
RXM0 RXF3
A c
c Acceptance Filter Acceptance Filter e
MESSAGE

MESSAGE

MESSAGE
MTXBUFF

MTXBUFF

MTXBUFF
MSGREQ

MSGREQ

MSGREQ
RXF0 RXF4
TXLARB

TXLARB

TXLARB
c p
TXERR

TXERR

TXERR
TXABT

TXABT

TXABT
e t
Acceptance Filter Acceptance Filter
p
RXF1 RXF5
t

R R
X Identifier M Identifier X
Message B A B
Queue 0 B 1
Control
Transmit Byte Sequencer Data Field Data Field

Receive RERRCNT
Error

PROTOCOL Counter
TERRCNT

ENGINE Transmit ErrPas

Error BusOff
Counter

Transmit Shift Receive Shift

Protocol
Finite
CRC Generator CRC Check
State
Machine

Bit
Transmit
Timing Bit Timing
Logic
Logic Generator

CiTX(1) CiRX(1)

Note 1. i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2).

The dsPIC30F6015 has only one CAN module.

DS70150D-page 126 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
19.3 Modes of Operation The module can be programmed to apply a low-pass
filter function to the CiRX input line while the module or
The CAN module can operate in one of several operation the CPU is in Sleep mode. The WAKFIL bit
modes selected by the user. These modes include: (CiCFG2<14>) enables or disables the filter.
• Initialization mode
• Disable mode Note: Typically, if the CAN module is allowed to
• Normal Operation mode transmit in a particular mode of operation
• Listen-Only mode and a transmission is requested
• Loopback mode immediately after the CAN module has
• Error Recognition mode been placed in that mode of operation, the
module waits for 11 consecutive recessive
Modes are requested by setting the REQOP<2:0> bits on the bus before starting
bits (CiCTRL<10:8>). Entry into a mode is transmission. If the user switches to
acknowledged by monitoring the OPMODE<2:0> bits Disable mode within this 11-bit period, then
(CiCTRL<7:5>). The module will not change the mode this transmission is aborted and the
and the OPMODE bits until a change in mode is corresponding TXABT bit is set and
acceptable, generally during bus idle time which is TXREQ bit is cleared.
defined as at least 11 consecutive recessive bits.
19.3.3 NORMAL OPERATION MODE
19.3.1 INITIALIZATION MODE
Normal Operating mode is selected when
In the Initialization mode, the module will not transmit or
REQOP<2:0> = 000. In this mode, the module is
receive. The error counters are cleared and the
activated, the I/O pins will assume the CAN bus
interrupt flags remain unchanged. The programmer will
functions. The module will transmit and receive CAN
have access to Configuration registers that are access
bus messages via the CiTX and CiRX pins.
restricted in other modes. The module will protect the
user from accidentally violating the CAN protocol 19.3.4 LISTEN-ONLY MODE
through programming errors. All registers which control
the configuration of the module can not be modified If the Listen-Only mode is activated, the module on the
while the module is on-line. The CAN module will not CAN bus is passive. The transmitter buffers revert to
be allowed to enter the Configuration mode while a the Port I/O function. The receive pins remain inputs.
transmission is taking place. The Configuration mode For the receiver, no error flags or acknowledge signals
serves as a lock to protect the following registers: are sent. The error counters are deactivated in this
state. The Listen-Only mode can be used for detecting
• All Module Control Registers the baud rate on the CAN bus. To use this, it is
• Baud Rate and Interrupt Configuration Registers necessary that there are at least two further nodes that
• Bus Timing Registers communicate with each other.
• Identifier Acceptance Filter Registers
19.3.5 ERROR RECOGNITION MODE
• Identifier Acceptance Mask Registers
The module can be set to ignore all errors and receive
19.3.2 DISABLE MODE any message. The Error Recognition mode is activated
In Disable mode, the module will not transmit or by setting the RXM<1:0> bits (CiRXnCON<6:5>) to
receive. The module has the ability to set the WAKIF bit ‘11’. In this mode, the data which is in the message
due to bus activity, however any pending interrupts will assembly buffer until the time an error occurred, is
remain and the error counters will retain their value. copied in the receive buffer and can be read via the
CPU interface.
If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the
module will enter the Module Disable mode. If the 19.3.6 LOOPBACK MODE
module is active, the module will wait for 11 recessive
If the Loopback mode is activated, the module will
bits on the CAN bus, detect that condition as an idle
connect the internal transmit signal to the internal
bus, then accept the module disable command. When
receive signal at the module boundary. The transmit
the OPMODE<2:0> bits (CiCTRL<7:5>) = 001, that
and receive pins revert to their Port I/O function.
indicates whether the module successfully went into
Module Disable mode. The I/O pins will revert to normal
I/O function when the module is in the Module Disable
mode.

© 2008 Microchip Technology Inc. DS70150D-page 127

dsPIC30F6010A/6015
19.4 Message Reception 19.4.4 RECEIVE OVERRUN
An overrun condition occurs when the message
19.4.1 RECEIVE BUFFERS assembly buffer has assembled a valid received
The CAN bus module has 3 receive buffers. However, message and the message is accepted through the
one of the receive buffers is always committed to acceptance filters, but the receive buffer associated
monitoring the bus for incoming messages. This buffer with the filter still contains unread data.
is called the Message Assembly Buffer (MAB). So The overrun error flag, RXnOVR (CiINTF<15> or
there are 2 receive buffers visible, RXB0 and RXB1, CiINTF<14>) and the ERRIF bit (CiINTF<5>) will be set
that can essentially instantaneously receive a complete and the message in the MAB will be discarded.
message from the protocol engine.
If the DBEN bit is clear, RXB1 and RXB0 operate inde-
All messages are assembled by the MAB, and are trans- pendently. When this is the case, a message intended
ferred to the RXBn buffers only if the acceptance filter for RXB0 will not be diverted into RXB1 if RXB0
criterion is met. When a message is received, the RXnIF contains an unread message and the RX0OVR bit will
flag (CiINTF<0> or CiINTF<1>) will be set. This bit can be set.
only be set by the module when a message is received.
The bit is cleared by the CPU when it has completed If the DBEN bit is set, the overrun for RXB0 is handled
processing the message in the buffer. If the RXnIE bit differently. If a valid message is received for RXB0 and
(CiINTE<0> or CiINTE<1>) is set, an interrupt will be RXFUL = 1 indicates that RXB0 is full and RXFUL = 0
generated when a message is received. indicates that RXB1 is empty, the message for RXB0
will be loaded into RXB1. An overrun error will not be
RXF0 and RXF1 filters with RXM0 mask are associated generated for RXB0. If a valid message is received for
with RXB0. The filters RXF2, RXF3, RXF4, and RXF5 RXB0 and RXFUL = 1, and RXFUL = 1 indicating that
and the mask RXM1 are associated with RXB1. both RXB0 and RXB1 are full, the message will be lost
and an overrun will be indicated for RXB1.
19.4.2 MESSAGE ACCEPTANCE FILTERS
The message acceptance filters and masks are used to 19.4.5 RECEIVE ERRORS
determine if a message in the message assembly The CAN module will detect the following receive
buffer should be loaded into either of the receive errors:
buffers. Once a valid message has been received into
the message assembly buffer, the identifier fields of the • Cyclic Redundancy Check (CRC) error
message are compared to the filter values. If there is a • Bit Stuffing error
match, that message will be loaded into the appropriate • Invalid message receive error
receive buffer.
The receive error counter is incremented by one in
The acceptance filter looks at incoming messages for case one of these errors occur. The RXWAR bit
the RXIDE bit (CiRXnSID<0>) to determine how to (CiINTF<9>) indicates that the Receive Error Counter
compare the identifiers. If the RXIDE bit is clear, the has reached the CPU warning limit of 96 and an
message is a standard frame, and only filters with the interrupt is generated.
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame, 19.4.6 RECEIVE INTERRUPTS
and only filters with the EXIDE bit set are compared. Receive interrupts can be divided into 3 major groups,
Configuring the RXM<1:0> bits to ‘01’ or ‘10’ can each including various conditions that generate
override the EXIDE bit. interrupts:
19.4.3 MESSAGE ACCEPTANCE FILTER • Receive Interrupt
MASKS A message has been successfully received and loaded
The mask bits essentially determine which bits to apply into one of the receive buffers. This interrupt is
the filter to. If any mask bit is set to a zero, then that bit activated immediately after receiving the End-of-Frame
will automatically be accepted regardless of the filter (EOF) field. Reading the RXnIF flag will indicate which
bit. There are 2 programmable acceptance filter masks receive buffer caused the interrupt.
associated with the receive buffers, one for each buffer. • Wake-up Interrupt
The CAN module has woken up from Disable mode or
the device has woken up from Sleep mode.

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 dsPIC30F6010A/6015
• Receive Error Interrupts Setting TXREQ bit simply flags a message buffer as
A receive error interrupt will be indicated by the ERRIF enqueued for transmission. When the module detects
bit. This bit shows that an error condition occurred. The an available bus, it begins transmitting the message
source of the error can be determined by checking the which has been determined to have the highest priority.
bits in the CAN Interrupt STATUS register, CiINTF. If the transmission completes successfully on the first
• Invalid message received attempt, the TXREQ bit is cleared automatically and an
interrupt is generated if TXIE was set.
If any type of error occurred during reception of the last
message, an error will be indicated by the IVRIF bit. If the message transmission fails, one of the error
condition flags will be set and the TXREQ bit will
• Receiver overrun remain set indicating that the message is still pending
The RXnOVR bit indicates that an overrun condition for transmission. If the message encountered an error
occurred. condition during the transmission attempt, the TXERR
bit will be set and the error condition may cause an
• Receiver warning
interrupt. If the message loses arbitration during the
The RXWAR bit indicates that the Receive Error transmission attempt, the TXLARB bit is set. No
Counter (RERRCNT<7:0>) has reached the Warning interrupt is generated to signal the loss of arbitration.
limit of 96.
• Receiver error passive 19.5.4 ABORTING MESSAGE
TRANSMISSION
The RXEP bit indicates that the Receive Error Counter
has exceeded the Error Passive limit of 127 and the The system can also abort a message by clearing the
module has gone into Error Passive state. TXREQ bit associated with each message buffer.
Setting the ABAT bit (CiCTRL<12>) will request an
19.5 Message Transmission abort of all pending messages. If the message has not
yet started transmission, or if the message started but
19.5.1 TRANSMIT BUFFERS is interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
The CAN module has three transmit buffers. Each of module sets the TXABT bit, and the TXnIF flag is not
the three buffers occupies 14 bytes of data. Eight of the automatically set.
bytes are the maximum 8 bytes of the transmitted
message. Five bytes hold the standard and extended 19.5.5 TRANSMISSION ERRORS
identifiers and other message arbitration information.
The CAN module will detect the following transmission
19.5.2 TRANSMIT MESSAGE PRIORITY errors:

Transmit priority is a prioritization within each node of the • Acknowledge error

pending transmittable messages. There are 4 levels of • Form error
transmit priority. If TXPRI<1:0> (CiTXnCON<1:0>, where • Bit error
n = 0, 1 or 2 represents a particular transmit buffer) for a These transmission errors will not necessarily generate
particular message buffer is set to ‘11’, that buffer has the an interrupt, but are indicated by the transmission error
highest priority. If TXPRI<1:0> for a particular message counter. However, each of these errors will cause the
buffer is set to ‘10’ or ‘01’, that buffer has an intermediate transmission error counter to be incremented by one.
priority. If TXPRI<1:0> for a particular message buffer is Once the value of the error counter exceeds the value
‘00’, that buffer has the lowest priority. of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
19.5.3 TRANSMISSION SEQUENCE
counter exceeds the value of 96, an interrupt is
To initiate transmission of the message, the TXREQ bit generated and the TXWAR bit in the Error Flag register
(CiTXnCON<3>) must be set. The CAN bus module is set.
resolves any timing conflicts between setting of the
TXREQ bit and the Start-of-Frame (SOF), ensuring
that if the priority was changed, it is resolved correctly
before the SOF occurs. When TXREQ is set, the
TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>)
and TXERR (CiTXnCON<4>) flag bits are
automatically cleared.

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dsPIC30F6010A/6015
19.5.6 TRANSMIT INTERRUPTS 19.6 Baud Rate Setting
Transmit interrupts can be divided into 2 major groups, All nodes on any particular CAN bus must have the
each including various conditions that generate same nominal bit rate. In order to set the baud rate, the
interrupts: following parameters have to be initialized:
• Transmit Interrupt • Synchronization jump width
At least one of the three transmit buffers is empty (not • Baud rate prescaler
scheduled) and can be loaded to schedule a message • Phase segments
for transmission. Reading the TXnIF flags will indicate
• Length determination of Phase2 Seg
which transmit buffer is available and caused the
interrupt. • Sample point
• Propagation segment bits
• Transmit Error Interrupts
A transmission error interrupt will be indicated by the 19.6.1 BIT TIMING
ERRIF flag. This flag shows that an error condition
All controllers on the CAN bus must have the same baud
occurred. The source of the error can be determined by
rate and bit length. However, different controllers are not
checking the error flags in the CAN Interrupt STATUS
required to have the same master oscillator clock. At
register, CiINTF. The flags in this register are related to
different clock frequencies of the individual controllers,
receive and transmit errors.
the baud rate has to be adjusted by adjusting the
• Transmitter Warning Interrupt number of time quanta in each segment.
The TXWAR bit indicates that the Transmit Error The Nominal Bit Time can be thought of as being
Counter has reached the CPU warning limit of 96. divided into separate non-overlapping time segments.
• Transmitter Error Passive These segments are shown in Figure 19-2.
The TXEP bit (CiINTF<12>) indicates that the Transmit • Synchronization segment (Sync Seg)
Error Counter has exceeded the Error Passive limit of • Propagation time segment (Prop Seg)
127 and the module has gone to Error Passive state. • Phase segment 1 (Phase1 Seg)
• Bus Off • Phase segment 2 (Phase2 Seg)
The TXBO bit (CiINTF<13>) indicates that the Transmit The time segments and also the nominal bit time are
Error Counter has exceeded 255 and the module has made up of integer units of time called time quanta or
gone to Bus Off state. TQ. By definition, the nominal bit time has a minimum
of 8 TQ and a maximum of 25 TQ. Also, by definition,
the minimum nominal bit time is 1 μsec, corresponding
to a maximum bit rate of 1 MHz.

FIGURE 19-2: CAN BIT TIMING

Input Signal

Prop Phase Phase

Sync Segment Segment 1 Segment 2 Sync

Sample Point

TQ

DS70150D-page 130 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
19.6.2 PRESCALER SETTING 19.6.5 SAMPLE POINT
There is a programmable prescaler, with integral The sample point is the point of time at which the bus
values ranging from 1 to 64, in addition to a fixed level is read and interpreted as the value of that
divide-by-2 for clock generation. The Time Quantum respective bit. The location is at the end of Phase1
(TQ) is a fixed unit of time derived from the oscillator Seg. If the bit timing is slow and contains many TQ, it is
period, and is given by Equation 19-1, where FCAN is possible to specify multiple sampling of the bus line at
FCY (if the CANCKS bit is set or 4 FCY (if CANCKS is the sample point. The level determined by the CAN bus
cleared). then corresponds to the result from the majority deci-
sion of three values. The majority samples are taken at
Note: FCAN must not exceed 30 MHz. If the sample point and twice before with a distance of
CANCKS = 0, then FCY must not exceed TQ/2. The CAN module allows the user to chose
7.5 MHz. between sampling three times at the same point or
once at the same point, by setting or clearing the SAM
EQUATION 19-1: TIME QUANTUM FOR bit (CiCFG2<6>).
CLOCK GENERATION Typically, the sampling of the bit should take place at
about 60-70% through the bit time, depending on the
TQ = 2 ( BRP<5:0> + 1 )/FCAN system parameters.

19.6.6 SYNCHRONIZATION
19.6.3 PROPAGATION SEGMENT
To compensate for phase shifts between the oscillator
This part of the bit time is used to compensate physical frequencies of the different bus stations, each CAN
delay times within the network. These delay times controller must be able to synchronize to the relevant
consist of the signal propagation time on the bus line signal edge of the incoming signal. When an edge in
and the internal delay time of the nodes. The the transmitted data is detected, the logic will compare
Propagation Segment can be programmed from 1 TQ the location of the edge to the expected time
to 8 TQ by setting the PRSEG<2:0> bits (Synchronous Segment). The circuit will then adjust the
(CiCFG2<2:0>). values of Phase1 Seg and Phase2 Seg. There are 2
mechanisms used to synchronize.
19.6.4 PHASE SEGMENTS
The phase segments are used to optimally locate the 19.6.6.1 Hard Synchronization
sampling of the received bit within the transmitted bit Hard synchronization is only done whenever there is a
time. The sampling point is between Phase1 Seg and recessive to dominant edge during bus Idle, indicating
Phase2 Seg. These segments are lengthened or short- the start of a message. After hard synchronization, the
ened by re-synchronization. The end of the Phase1 bit time counters are restarted with the Synchronous
Seg determines the sampling point within a bit period. Segment. Hard synchronization forces the edge which
The segment is programmable from 1 TQ to 8 TQ. has caused the hard synchronization to lie within the
Phase2 Seg provides delay to the next transmitted data synchronization segment of the restarted bit time. If a
transition. The segment is programmable from 1 TQ to hard synchronization is done, there will not be a
8 TQ, or it may be defined to be equal to the greater of resynchronization within that bit time.
Phase1 Seg or the Information Processing Time
(2 TQ). The Phase1 Seg is initialized by setting bits 19.6.6.2 Re-synchronization
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
As a result of re-synchronization, Phase1 Seg may be
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
lengthened or Phase2 Seg may be shortened. The
The following requirement must be fulfilled while setting amount of lengthening or shortening of the phase
the lengths of the Phase Segments: buffer segment has an upper bound known as the
• Propagation Segment + Phase1 Seg > = Phase2 Seg synchronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the
synchronization jump width will be added to Phase1
Seg or subtracted from Phase2 Seg. The
re-synchronization jump width is programmable
between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
• Phase2 Seg > Synchronization Jump Width

© 2008 Microchip Technology Inc. DS70150D-page 131

 TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES(1)
DS70150D-page 132

dsPIC30F6010A/6015
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

C1RXF0SID 0300 — — — Receive Acceptance Filter 0 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF0EIDH 0302 — — — — Receive Acceptance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF1SID 0308 — — — Receive Acceptance Filter 1 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF2SID 0310 — — — Receive Acceptance Filter 2 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF2EIDH 0312 — — — — Receive Acceptance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF3SID 0318 — — — Receive Acceptance Filter 3 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF4SID 0320 — — — Receive Acceptance Filter 4 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF4EIDH 0322 — — — — Receive Acceptance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF5SID 0328 — — — Receive Acceptance Filter 5 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM0SID 0330 — — — Receive Acceptance Mask 0 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM0EIDH 0332 — — — — Receive Acceptance Mask 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM1SID 0338 — — — Receive Acceptance Mask 1 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM1EIDH 033A — — — — Receive Acceptance Mask 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1TX2SID 0340 Transmit Buffer 2 Standard Identifier<10:6> — — — Transmit Buffer 2 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX2EID 0342 Transmit Buffer 2 Extended — — — — Transmit Buffer 2 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
Identifier<17:14>
C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
© 2008 Microchip Technology Inc.

C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C1TX1SID 0350 Transmit Buffer 1 Standard Identifier<10:6> — — — Transmit Buffer 1 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX1EID 0352 Transmit Buffer 1 Extended — — — — Transmit Buffer 1 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
Identifier<17:14>
C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
 TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES(1) (CONTINUED)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C1TX1B2 0358 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1TX1B3 035A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C1TX1B4 035C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1TX1CON 035E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C1TX0SID 0360 Transmit Buffer 0 Standard Identifier<10:6> — — — Transmit Buffer 0 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX0EID 0362 Transmit Buffer 0 Extended — — — — Transmit Buffer 0 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
Identifier<17:14>
C1TX0DLC 0364 Transmit Buffer 0 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX0B1 0366 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1TX0B2 0368 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1TX0B3 036A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1TX0B4 036C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1TX0CON 036E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C1RX1SID 0370 — — — Receive Buffer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX1EID 0372 — — — — Receive Buffer 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RX1DLC 0374 Receive Buffer 1 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX1B1 0376 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C1RX1B2 0378 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1RX1B3 037A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C1RX1B4 037C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1RX1CON 037E — — — — — — — — RXFUL — — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000

dsPIC30F6010A/6015
C1RX0SID 0380 — — — Receive Buffer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX0EID 0382 — — — — Receive Buffer 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RX0DLC 0384 Receive Buffer 0 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 038E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1CTRL 0390 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000
C1CFG1 0392 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
DS70150D-page 133

C1EC 039A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
 TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A(1)
DS70150D-page 134

dsPIC30F6010A/6015
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

C2RXF0SID 03C0 — — — Receive Acceptance Filter 0 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF0EIDH 03C2 — — — — Receive Acceptance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF1SID 03C8 — — — Receive Acceptance Filter 1 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF1EIDH 03CA — — — — Receive Acceptance Filter 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF1EIDL 03CC Receive Acceptance Filter 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF2SID 03D0 — — — Receive Acceptance Filter 2 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF2EIDH 03D2 — — — — Receive Acceptance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF2EIDL 03D4 Receive Acceptance Filter 2 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF3SID 03D8 — — — Receive Acceptance Filter 3 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF3EIDH 03DA — — — — Receive Acceptance Filter 3 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF3EIDL 03DC Receive Acceptance Filter 3 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF4SID 03E0 — — — Receive Acceptance Filter 4 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF4EIDH 03E2 — — — — Receive Acceptance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF4EIDL 03E4 Receive Acceptance Filter 4 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF5SID 03E8 — — — Receive Acceptance Filter 5 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF5EIDH 03EA — — — — Receive Acceptance Filter 5 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXF5EIDL 03EC Receive Acceptance Filter 5 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXM0SID 03F0 — — — Receive Acceptance Mask 0 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u
C2RXM0EIDH 03F2 — — — — Receive Acceptance Mask 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXM0EIDL 03F4 Receive Acceptance Mask 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXM1SID 03F8 — — — Receive Acceptance Mask 1 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u
C2RXM1EIDH 03FA — — — — Receive Acceptance Mask 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RXM1EIDL 03FC Receive Acceptance Mask 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2TX2SID 0400 Transmit Buffer 2 Standard Identifier<10:6> — — — Transmit Buffer 2 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C2TX2EID 0402 Transmit Buffer 2 Extended Identifier<17:14> — — — — Transmit Buffer 2 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
C2TX2DLC 0404 Transmit Buffer 2 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C2TX2B1 0406 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C2TX2B2 0408 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
© 2008 Microchip Technology Inc.

C2TX2B3 040A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C2TX2B4 040C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C2TX2CON 040E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C2TX1SID 0410 Transmit Buffer 1 Standard Identifier<10:6> — — — Transmit Buffer 1 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C2TX1EID 0412 Transmit Buffer 1 Extended Identifier<17:14> — — — — Transmit Buffer 1 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
C2TX1DLC 0414 Transmit Buffer 1 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
 TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A(1) (CONTINUED)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C2TX1B1 0416 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C2TX1B2 0418 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C2TX1B3 041A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C2TX1B4 041C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C2TX1CON 041E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C2TX0SID 0420 Transmit Buffer 0 Standard Identifier<10:6> — — — Transmit Buffer 0 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C2TX0EID 0422 Transmit Buffer 0 Extended Identifier<17:14> — — — — Transmit Buffer 0 Extended Identifier<13:6> uuuu 0000 uuuu uuuu
C2TX0DLC 0424 Transmit Buffer 0 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C2TX0B1 0426 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C2TX0B2 0428 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C2TX0B3 042A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C2TX0B4 042C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C2TX0CON 042E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C2RX1SID 0430 — — — Receive Buffer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C2RX1EID 0432 — — — — Receive Buffer 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RX1DLC 0434 Receive Buffer 1 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C2RX1B1 0436 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C2RX1B2 0438 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C2RX1B3 043A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C2RX1B4 043C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C2RX1CON 043E — — — — — — — — RXFUL — — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000

dsPIC30F6010A/6015
C2RX0SID 0440 — — — Receive Buffer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C2RX0EID 0442 — — — — Receive Buffer 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C2RX0DLC 0444 Receive Buffer 0 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C2RX0B1 0446 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C2RX0B2 0448 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C2RX0B3 044A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C2RX0B4 044C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C2RX0CON 044E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C2CTRL 0450 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000
C2CFG1 0452 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C2CFG2 0454 WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C2INTF 0456 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C2INTE 0458 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
DS70150D-page 135

C2EC 045A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015
NOTES:

DS70150D-page 136 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
20.0 10-BIT HIGH-SPEED The A/D module has six 16-bit registers:
ANALOG-TO-DIGITAL • A/D Control Register 1 (ADCON1)
CONVERTER (ADC) MODULE • A/D Control Register 2 (ADCON2)
• A/D Control Register 3 (ADCON3)
Note: This data sheet summarizes features of • A/D Input Select Register (ADCHS)
this group of dsPIC30F devices and is not
• A/D Port Configuration Register (ADPCFG)
intended to be a complete reference
source. For more information on the CPU, • A/D Input Scan Selection Register (ADCSSL)
peripherals, register descriptions and The ADCON1, ADCON2 and ADCON3 registers
general device functionality, refer to the control the operation of the A/D module. The ADCHS
“dsPIC30F Family Reference Manual” register selects the input channels to be converted. The
(DS70046). ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
The10-bit high-speed Analog-to-Digital Converter
inputs for scanning.
(ADC) allows conversion of an analog input signal to a
10-bit digital number. This module is based on a Note: The SSRC<2:0>, ASAM, SIMSAM,
Successive Approximation Register (SAR) SMPI<3:0>, BUFM and ALTS bits, as well
architecture, and provides a maximum sampling rate of as the ADCON3 and ADCSSL registers,
1 Msps. The A/D module has 16 analog inputs which must not be written to while ADON = 1.
are multiplexed into four sample and hold amplifiers. This would lead to indeterminate results.
The output of the sample and hold is the input into the
The block diagram of the A/D module is shown in
converter, which generates the result. The analog
Figure 20-1.
reference voltages are software selectable to either the
device supply voltage (AVDD/AVSS) or the voltage level
on the (VREF+/VREF-) pin. The A/D converter has a
unique feature of being able to operate while the device
is in Sleep mode.

© 2008 Microchip Technology Inc. DS70150D-page 137

dsPIC30F6010A/6015
FIGURE 20-1: 10-BIT HIGH-SPEED A/D FUNCTIONAL BLOCK DIAGRAM
AVDD
VREF+(1)
AVSS
VREF-(2)

AN0 AN0
AN3 +
S/H CH1 ADC
AN6 -
AN9

AN1 10-bit Result Conversion Logic

AN1
AN4 +
S/H CH2

Format
Data
AN7 -
AN10 16-word, 10-bit
Dual Port
Buffer

Bus Interface
AN2 AN2
AN5 +
S/H CH3
AN8 - CH1,CH2,
AN11 CH3,CH0 Sample/Sequence
sample Control

AN0
AN1 input
AN2 switches Input MUX
AN3 AN3 Control

AN4 AN4

AN5 AN5

AN6 AN6

AN7 AN7

AN8 AN8

AN9 AN9

AN10 AN10

AN11 AN11

AN12 AN12

AN13 AN13

AN14 AN14

AN15 AN15 +
S/H CH0
AN1 -

Note 1: VREF+ is multiplexed with AN0 in the dsPIC30F6015 variant.

2: VREF- is multiplexed with AN1 in the dsPIC30F6015 variant.

DS70150D-page 138 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
20.1 A/D Result Buffer The CHPS bits selects how many channels are
sampled. This can vary from 1, 2 or 4 channels. If
The module contains a 16-word dual port, read-only CHPS selects 1 channel, the CH0 channel will be
buffer, called ADCBUF0...ADCBUFF, to buffer the A/D sampled at the sample clock and converted. The result
results. The RAM is 10-bits wide, but is read into different is stored in the buffer. If CHPS selects 2 channels, the
format 16-bit words. The contents of the sixteen A/D CH0 and CH1 channels will be sampled and converted.
Conversion Result Buffer registers, ADCBUF0 through If CHPS selects 4 channels, the CH0, CH1, CH2 and
ADCBUFF, cannot be written by user software. CH3 channels will be sampled and converted.
The SMPI bits select the number of
20.2 Conversion Operation acquisition/conversion sequences that would be
After the A/D module has been configured, the sample performed before an interrupt occurs. This can vary
acquisition is started by setting the SAMP bit. Various from 1 sample per interrupt to 16 samples per interrupt.
sources, such as a programmable bit, timer time-outs and The user cannot program a combination of CHPS and
external events, will terminate acquisition and start a SMPI bits that specifies more than 16 conversions per
conversion. When the A/D conversion is complete, the interrupt, or 8 conversions per interrupt, depending on
result is loaded into ADCBUF0...ADCBUFF, and the A/D the BUFM bit. The BUFM bit, when set, will split the
Interrupt Flag ADIF and the DONE bit are set after the 16-word results buffer (ADCBUF0...ADCBUFF) into
number of samples specified by the SMPI bit. two 8-word groups. Writing to the 8-word buffers will be
The following steps should be followed for doing an alternated on each interrupt event. Use of the BUFM bit
A/D conversion: will depend on how much time is available for moving
data out of the buffers after the interrupt, as determined
1. Configure the A/D module:
by the application.
-Configure analog pins, voltage reference
and digital I/O If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
-Select A/D input channels
the BUFM bit can be ‘0’ and up to 16 conversions may
-Select A/D conversion clock be done per interrupt. The processor will have one
-Select A/D conversion trigger sample and conversion time to move the sixteen
-Turn on A/D module conversions.
2. Configure A/D interrupt (if required): If the processor cannot unload the buffer within the
-Clear ADIF bit acquisition and conversion time, the BUFM bit should be
-Select A/D interrupt priority ‘1’. For example, if SMPI<3:0> (ADCON2<5:2> = 0111),
then eight conversions will be loaded into 1/2 of the
3. Start sampling.
buffer, following which an interrupt occurs. The next eight
4. Wait the required acquisition time. conversions will be loaded into the other 1/2 of the buffer.
5. Trigger acquisition end, start conversion The processor will have the entire time between
6. Wait for A/D conversion to complete, by either: interrupts to move the eight conversions.
-Waiting for the A/D interrupt The ALTS bit can be used to alternate the inputs
7. Read A/D result buffer, clear ADIF if required. selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
20.3 Selecting the Conversion MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
Sequence selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000, on the first sample/convert
Several groups of control bits select the sequence in sequence, the MUX A inputs are selected, and on the
which the A/D connects inputs to the sample/hold next acquire/convert sequence, the MUX B inputs are
channels, converts channels, writes the buffer memory, selected.
and generates interrupts. The sequence is controlled The CSCNA bit (ADCON2<10>) will allow the CH0
by the sampling clocks. channel inputs to be alternately scanned across a
The SIMSAM bit controls the acquire/convert selected number of analog inputs for the MUX A group.
sequence for multiple channels. If the SIMSAM bit is The inputs are selected by the ADCSSL register. If a
‘0’, the two or four selected channels are acquired and particular bit in the ADCSSL register is ‘1’, the
converted sequentially, with two or four sample clocks. corresponding input is selected. The inputs are always
If the SIMSAM bit is ‘1’, two or four selected channels scanned from lower to higher numbered inputs, starting
are acquired simultaneously, with one sample clock. after each interrupt. If the number of inputs selected is
The channels are then converted sequentially. greater than the number of samples taken per interrupt,
Obviously, if there is only 1 channel selected, the the higher numbered inputs are unused.
SIMSAM bit is not applicable.

© 2008 Microchip Technology Inc. DS70150D-page 139

dsPIC30F6010A/6015
20.4 Programming the Start of 20.6 Selecting the A/D Conversion
Conversion Trigger Clock
The conversion trigger will terminate acquisition and The A/D conversion requires 12 TAD. The source of the
start the requested conversions. A/D conversion clock is software selected using a 6-bit
The SSRC<2:0> bits select the source of the counter. There are 64 possible options for TAD.
conversion trigger.
EQUATION 20-1: A/D CONVERSION CLOCK
The SSRC bits provide for up to five alternate sources
of conversion trigger. TAD = TCY * (0.5 * (ADCS<5:0> + 1))
When SSRC<2:0> = 000, the conversion trigger is TAD
ADCS<5:0> = 2 –1
under software control. Clearing the SAMP bit will TCY
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con- The internal RC oscillator is selected by setting the
version trigger is under A/D clock control. The SAMC ADRC bit.
bits select the number of A/D clocks between the start For correct A/D conversions, the A/D conversion clock
of acquisition and the start of conversion. This provides (TAD) must be selected to ensure a minimum TAD time
the fastest conversion rates on multiple channels. of 83.33 nsec (for VDD = 5V). Refer to Section 24.0
SAMC must always be at least one clock cycle. "Electrical Characteristics" for minimum TAD under
Other trigger sources can come from timer modules, other operating conditions.
motor control PWM module, or external interrupts. Example 20-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
Note: To operate the A/D at the maximum
of 30 MIPS.
specified conversion speed, the
Auto-Convert Trigger option should be
selected (SSRC = 111) and the EXAMPLE 20-1: A/D CONVERSION CLOCK
Auto-Sample Time bits should be set to 1 CALCULATION
TAD (SAMC = 00001). This configuration
will give a total conversion period (sample + TAD = 84 nsec
convert) of 13 TAD. TCY = 33 nsec (30 MIPS)
The use of any other conversion trigger TAD
will result in additional TAD cycles to ADCS<5:0> = 2 –1
TCY
synchronize the external event to the A/D. 84 nsec
=2• –1
33 nsec
20.5 Aborting a Conversion = 4.09
Clearing the ADON bit during a conversion will abort Therefore,
the current conversion and stop the sampling Set ADCS<5:0> = 9
sequencing. The ADCBUF will not be updated with the
partially completed A/D conversion sample. That is, the TCY
Actual TAD = (ADCS<5:0> + 1)
ADCBUF will continue to contain the value of the last 2
completed conversion (or the last value written to the 33 nsec
= (9 + 1)
ADCBUF register). 2
If the clearing of the ADON bit coincides with an = 99 nsec
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multichannel group conversion sequence.

DS70150D-page 140 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
20.7 A/D Conversion Speeds
The dsPIC30F 10-bit A/D converter specifications
permit a maximum 1 Msps sampling rate. Table 20-1
summarizes the conversion speeds for the dsPIC30F
10-bit A/D converter and the required operating
conditions.

TABLE 20-1: 10-BIT A/D CONVERSION RATE PARAMETERS

dsPIC30F 10-bit A/D Converter Conversion Rates

TAD Sampling
A/D Speed RS Max VDD Temperature A/D Channels Configuration
Minimum Time Min
Up to 83.33 ns 12 TAD 500Ω 4.5V to 5.5V -40°C to +85°C VREF- VREF+
1 Msps(1)
CH1, CH2 or CH3
ANx
S/H

ADC
CH0
S/H

Up to 95.24 ns 2 TAD 500Ω 4.5V to 5.5V -40°C to +85°C

750 ksps(1)
VREF- VREF+

CHX
ANx
S/H ADC

Up to 138.89 ns 12 TAD 500Ω 3.0V to 5.5V -40°C to +125°C VREF- VREF+

600 ksps(1)
CH1, CH2 or CH3
ANx
S/H

ADC
CH0
S/H

Up to 153.85 ns 1 TAD 5.0 kΩ 4.5V to 5.5V -40°C to +125°C

500 ksps VREF- VREF+
or or
AVSS AVDD

ANx CHX
S/H ADC

ANx or VREF-

Up to 256.41 ns 1 TAD 5.0 kΩ 3.0V to 5.5V -40°C to +125°C

300 ksps VREF- VREF+
or or
AVSS AVDD

ANx CHX
S/H ADC

ANx or VREF-

Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 20-2 for recommended
circuit.

© 2008 Microchip Technology Inc. DS70150D-page 141

dsPIC30F6010A/6015
The configuration guidelines give the required setup The following figure depicts the recommended circuit
values for the conversion speeds above 500 ksps, for the conversion rates above 500 ksps.
since they require external VREF pins usage and there
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.

FIGURE 20-2: A/D CONVERTER VOLTAGE REFERENCE SCHEMATIC

VDD

VDD
VSS
VDD VDD VDD

C8 C7 C6
1 μF 0.1 μF 0.01 μF

dsPIC30F6010A VSS
VDD VSS
VDD VDD
VDD VDD VDD VDD

C5 C4 C3
1 μF 0.1 μF 0.01 μF
VDD
VREF-

AVDD
AVSS
VREF
+

R2
VDD
VSS

10

R1 VDD
C2 C1 10
0.1 μF 0.01 μF VDD

20.7.1 1 Msps CONFIGURATION 20.7.1.2 Multiple Analog Inputs

GUIDELINE The A/D converter can also be used to sample multiple
The configuration for 1 Msps operation is dependent on analog inputs using multiple sample and hold channels.
whether a single input pin is to be sampled or whether In this case, the total 1 Msps conversion rate is divided
multiple pins will be sampled. among the different input signals. For example, four
inputs can be sampled at a rate of 250 ksps for each
20.7.1.1 Single Analog Input signal or two inputs could be sampled at a rate of
For conversions at 1 Msps for a single analog input, at 500 ksps for each signal. Sequential sampling must be
least two sample and hold channels must be enabled. used in this configuration to allow adequate sampling
The analog input multiplexer must be configured so time on each input.
that the same input pin is connected to both sample
and hold channels. The A/D converts the value held on
one S/H channel, while the second S/H channel
acquires a new input sample.

DS70150D-page 142 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
20.7.1.3 1 Msps Configuration Items 20.7.3 600 ksps CONFIGURATION
The following configuration items are required to GUIDELINE
achieve a 1 Msps conversion rate. The configuration for 600 ksps operation is dependent
• Comply with conditions provided in Table 20-2 on whether a single input pin is to be sampled or
whether multiple pins will be sampled.
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 20-2
20.7.3.1 Single Analog Input
• Set SSRC<2:0> = 111 in the ADCON1 register to
enable the auto-convert option When performing conversions at 600 ksps for a single
analog input, at least two sample and hold channels
• Enable automatic sampling by setting the ASAM
must be enabled. The analog input multiplexer must be
control bit in the ADCON1 register
configured so that the same input pin is connected to
• Enable sequential sampling by clearing the both sample and hold channels. The A/D converts the
SIMSAM bit in the ADCON1 register value held on one S/H channel, while the second S/H
• Enable at least two sample and hold channels by channel acquires a new input sample.
writing the CHPS<1:0> control bits in the
ADCON2 register 20.7.3.2 Multiple Analog Input
• Write the SMPI<3:0> control bits in the ADCON2 The A/D converter can also be used to sample multiple
register for the desired number of conversions analog inputs using multiple sample and hold channels.
between interrupts. At a minimum, set In this case, the total 600 ksps conversion rate is
SMPI<3:0> = 0001 since at least two sample and divided among the different input signals. For example,
hold channels should be enabled four inputs can be sampled at a rate of 150 ksps for
• Configure the A/D clock period to be: each signal or two inputs can be sampled at a rate of
1 300 ksps for each signal. Sequential sampling must be
= 83.33 ns used in this configuration to allow adequate sampling
12 x 1,000,000
time on each input.
by writing to the ADCS<5:0> control bits in the
ADCON3 register 20.7.3.3 600 ksps Configuration Items
• Configure the sampling time to be 2 TAD by The following configuration items are required to
writing: SAMC<4:0> = 00010 achieve a 600 ksps conversion rate.
• Select at least two channels per analog input pin • Comply with conditions provided in Table 20-2
by writing to the ADCHS register
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 20-2
20.7.2 750 ksps CONFIGURATION
GUIDELINE • Set SSRC<2:0> = 111 in the ADCON1 register to
enable the auto-convert option
The following configuration items are required to
• Enable automatic sampling by setting the ASAM
achieve a 750 ksps conversion rate. This configuration
control bit in the ADCON1 register
assumes that a single analog input is to be sampled.
• Enable sequential sampling by clearing the
• Comply with conditions provided in Table 20-2 SIMSAM bit in the ADCON1 register
• Connect external VREF+ and VREF- pins following • Enable at least two sample and hold channels by
the recommended circuit shown in Figure 20-2 writing the CHPS<1:0> control bits in the
• Set SSRC<2:0> = 111 in the ADCON1 register to ADCON2 register
enable the auto-convert option • Write the SMPI<3:0> control bits in the ADCON2
• Enable automatic sampling by setting the ASAM register for the desired number of conversions
control bit in the ADCON1 register between interrupts. At a minimum, set
• Enable one sample and hold channel by setting SMPI<3:0> = 0001 since at least two sample and
CHPS<1:0> = 00 in the ADCON2 register hold channels should be enabled
• Write the SMPI<3:0> control bits in the ADCON2 • Configure the A/D clock period to be:
register for the desired number of conversions 1
= 138.89 ns
between interrupts 12 x 600,000
• Configure the A/D clock period to be:
1 by writing to the ADCS<5:0> control bits in the
= 95.24 ns ADCON3 register
(12 + 2) X 750,000
• Configure the sampling time to be 2 TAD by
by writing to the ADCS<5:0> control bits in the writing: SAMC<4:0> = 00010
ADCON3 register • Select at least two channels per analog input pin
• Configure the sampling time to be 2 TAD by by writing to the ADCHS register
writing: SAMC<4:0> = 00010

© 2008 Microchip Technology Inc. DS70150D-page 143

dsPIC30F6010A/6015
20.8 A/D Acquisition Requirements The user must allow at least 1 TAD period of sampling
time, TSAMP, between conversions to allow each
The analog input model of the 10-bit A/D converter is sample to be acquired. This sample time may be
shown in Figure 20-3. The total sampling time for the controlled manually in software by setting/clearing the
A/D is a function of the internal amplifier settling time, SAMP bit, or it may be automatically controlled by the
device VDD and the holding capacitor charge time. A/D converter. In an automatic configuration, the user
For the A/D converter to meet its specified accuracy, the must allow enough time between conversion triggers
charge holding capacitor (CHOLD) must be allowed to so that the minimum sample time can be satisfied.
fully charge to the voltage level on the analog input pin. Refer to Section 24.0 “Electrical Characteristics” for
The analog output source impedance (RS), the TAD and sample time requirements.
interconnect impedance (RIC), and the internal sampling
switch (RSS) impedance combine to directly affect the
time required to charge the capacitor CHOLD. The
combined impedance must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D converter, the
maximum recommended source impedance, RS, is 5 kΩ
for conversion rates up to 500 ksps and a maximum of
500Ω for conversion rates up to 1 Msps. After the analog
input channel is selected (changed), this sampling
function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.

FIGURE 20-3: A/D CONVERTER ANALOG INPUT MODEL

VDD RIC ≤ 250Ω Sampling RSS ≤ 3 kΩ

Switch
VT = 0.6V
Rs ANx RSS

CHOLD
VA CPIN I leakage = DAC capacitance
VT = 0.6V ± 500 nA = 4.4 pF

VSS

Legend: CPIN = input capacitance

VT = threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC = interconnect resistance
RSS = sampling switch resistance
CHOLD = sample/hold capacitance (from DAC)

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.

DS70150D-page 144 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
20.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the A/D
The module has 3 internal power modes. When the module will then be turned off, although the ADON bit
ADON bit is ‘1’, the module is in Active mode; it is fully will remain set.
powered and functional. When ADON is ‘0’, the module
is in Off mode. The digital and analog portions of the 20.10.2 A/D OPERATION DURING CPU IDLE
circuit are disabled for maximum current savings. In MODE
order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize. The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will continue
operation on assertion of Idle mode. If ADSIDL = 1, the
20.10 A/D Operation During CPU Sleep module will stop on Idle.
and Idle Modes
20.10.1 A/D OPERATION DURING CPU
20.11 Effects of a Reset
SLEEP MODE A device Reset forces all registers to their Reset state.
When the device enters Sleep mode, all clock sources This forces the A/D module to be turned off, and any
to the module are shutdown and stay at logic ‘0’. conversion and acquisition sequence is aborted. The
values that are in the ADCBUF registers are not
If Sleep occurs in the middle of a conversion, the modified. The A/D Result register will contain unknown
conversion is aborted. The converter will not continue data after a Power-on Reset.
with a partially completed conversion on exit from
Sleep mode.
20.12 Output Formats
Register contents are not affected by the device
entering or leaving Sleep mode. The A/D result is 10 bits wide. The data buffer RAM is
also 10 bits wide. The 10-bit data can be read in one of
The A/D module can operate during Sleep mode if the four different formats. The FORM<1:0> bits select the
A/D clock source is set to RC (ADRC = 1). When the format. Each of the output formats translates to a 16-bit
RC clock source is selected, the A/D module waits one result on the data bus.
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed, which Write data will always be in right justified (integer)
eliminates all digital switching noise from the format.
conversion. When the conversion is complete, the
DONE bit will be set and the result loaded into the
ADCBUF register.

FIGURE 20-4: A/D OUTPUT DATA FORMATS

RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0

Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0

Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

© 2008 Microchip Technology Inc. DS70150D-page 145

dsPIC30F6010A/6015
20.13 Configuring Analog Port Pins 20.14 Connection Considerations
The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD
operation of the A/D port pins. The port pins that are protection. This requires that the analog input be
desired as analog inputs must have their between VDD and VSS. If the input voltage exceeds this
corresponding TRIS bit set (input). If the TRIS bit is range by greater than 0.3V (either direction), one of the
cleared (output), the digital output level (VOH or VOL) diodes becomes forward biased and it may damage the
will be converted. device if the input current specification is exceeded.
The A/D operation is independent of the state of the An external RC filter is sometimes added for
CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. anti-aliasing of the input signal. The R component
When reading the PORT register, all pins configured as should be selected to ensure that the sampling time
analog input channels will read as cleared. requirements are satisfied. Any external components
connected (via high-impedance) to an analog input pin
Pins configured as digital inputs will not convert an (capacitor, Zener diode, etc.) should have very little
analog input. Analog levels on any pin that is defined as leakage current at the pin.
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.

DS70150D-page 146 © 2008 Microchip Technology Inc.

 TABLE 20-2: ADC REGISTER MAP(1)
© 2008 Microchip Technology Inc.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

ADCBUF0 0280 — — — — — — ADC Data Buffer 0 0000 00uu uuuu uuuu

ADCBUF1 0282 — — — — — — ADC Data Buffer 1 0000 00uu uuuu uuuu
ADCBUF2 0284 — — — — — — ADC Data Buffer 2 0000 00uu uuuu uuuu
ADCBUF3 0286 — — — — — — ADC Data Buffer 3 0000 00uu uuuu uuuu
ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu
ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu
ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu
ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu
ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu
ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu
ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu
ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu
ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu
ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu
ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu
ADCBUFF 029E — — — — — — ADC Data Buffer 15 0000 00uu uuuu uuuu
ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000

dsPIC30F6010A/6015
ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70150D-page 147
dsPIC30F6010A/6015
NOTES:

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21.0 SYSTEM INTEGRATION 21.1 Oscillator System Overview
Note: This data sheet summarizes features of The dsPIC30F oscillator system has the following
this group of dsPIC30F devices and is not modules and features:
intended to be a complete reference • Various external and internal oscillator options as
source. For more information on the CPU, clock sources
peripherals, register descriptions and • An on-chip PLL to boost internal operating
general device functionality, refer to the frequency
“dsPIC30F Family Reference Manual”
• A clock switching mechanism between various
(DS70046). For more information on the
clock sources
device instruction set and programming,
refer to the “dsPIC30F/33F Programmers • Programmable clock postscaler for system power
Reference Manual” (DS70157). savings
• A Fail-Safe Clock Monitor (FSCM) that detects
There are several features intended to maximize clock failure and takes fail-safe measures
system reliability, minimize cost through elimination of
• Clock Control register (OSCCON)
external components, provide power-saving operating
modes and offer code protection: • Configuration bits for main oscillator selection

• Oscillator Selection Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).
• Reset
Thereafter, the clock source can be changed between
- Power-on Reset (POR) permissible clock sources. The OSCCON register
- Power-up Timer (PWRT) controls the clock switching and reflects system clock
- Oscillator Start-up Timer (OST) related Status bits.
- Programmable Brown-out Reset (BOR) Table 21-1 provides a summary of the dsPIC30F
• Watchdog Timer (WDT) oscillator operating modes. A simplified diagram of the
• Power-Saving modes (Sleep and Idle) oscillator system is shown in Figure 21-1.
• Code Protection
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
dsPIC30F devices have a Watchdog Timer, which is
permanently enabled via the Configuration bits or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a delay
on power-up only, designed to keep the part in Reset
while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active, but the CPU is shut-off. The RC oscillator
option saves system cost, while the LP crystal option
saves power.

© 2008 Microchip Technology Inc. DS70150D-page 149

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TABLE 21-1: OSCILLATOR OPERATING MODES
Oscillator Mode Description

XTL 200 kHz-4 MHz crystal on OSC1:OSC2

XT 4 MHz-10 MHz crystal on OSC1:OSC2
XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled
XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled
XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1)
LP 32 kHz crystal on SOSCO:SOSCI(2)
HS 10 MHz-25 MHz crystal.
HS/2 w/PLL 4x 10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled(3)
HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled(3)
HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled(1)
HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled(4)
HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled(4)
HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled(1)(4)
EC External clock input (0-40 MHz)
ECIO External clock input (0-40 MHz), OSC2 pin is I/O
EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled
EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled
EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1)
ERC External RC oscillator, OSC2 pin is FOSC/4 output(5)
ERCIO External RC oscillator, OSC2 pin is I/O(5)
FRC 7.37 MHz internal RC oscillator
FRC w/PLL 4x 7.37 MHz internal RC oscillator, 4x PLL enabled
FRC w/PLL 8x 7.37 MHz internal RC oscillator, 8x PLL enabled
FRC w/PLL 16x 7.37 MHz internal RC oscillator, 16x PLL enabled
LPRC 512 kHz internal RC oscillator
Note 1: Any higher will violate device operating frequency range.
2: LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1.
3: Any higher will violate PLL input range.
4: Any lower will violate PLL input range.
5: Requires external R and C. Frequency operation up to 4 MHz.

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FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

Oscillator Configuration bits

PWRSAV Instruction

Wake-up Request

FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<2:0>
Primary Osc

TUN<5:0> NOSC<2:0>
6
Primary
Oscillator OSWEN
Stability Detector

Internal Fast RC
Oscillator (FRC)

Oscillator
POR Done Start-up
Clock
Timer
Switching
Programmable
Secondary Osc and Control Clock Divider System
Block
Clock
SOSCO
Secondary 2
32 kHz LP
Oscillator
SOSCI Oscillator
Stability Detector POST<1:0>

Internal Low- LPRC

Power RC
Oscillator (LPRC)

CF
Fail-Safe Clock
FCKSM<1:0> Monitor (FSCM)
2 Oscillator Trap

to Timer1

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21.2 Oscillator Configurations
21.2.1 INITIAL CLOCK SOURCE
SELECTION
While coming out of Power-on Reset or Brown-out
Reset, the device selects its clock source based on:
a) FOS<2:0> Configuration bits that select one of
four oscillator groups,
b) and FPR<4:0> Configuration bits that select one
of 16 oscillator choices within the primary group.
The selection is as shown in Table 21-2.

TABLE 21-2: .CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator
Oscillator Mode FOS<2:0> FPR<4:0> OSC2 Function
Source
ECIO w/PLL 4x PLL 1 1 1 0 1 1 0 1 I/O
ECIO w/PLL 8x PLL 1 1 1 0 1 1 1 0 I/O
ECIO w/PLL 16x PLL 1 1 1 0 1 1 1 1 I/O
FRC w/PLL 4x PLL 1 1 1 0 0 0 0 1 I/O
FRC w/PLL 8x PLL 1 1 1 0 1 0 1 0 I/O
FRC w/PLL 16x PLL 1 1 1 0 0 0 1 1 I/O
XT w/PLL 4x PLL 1 1 1 0 0 1 0 1 OSC2
XT w/PLL 8x PLL 1 1 1 0 0 1 1 0 OSC2
XT w/PLL 16x PLL 1 1 1 0 0 1 1 1 OSC2
HS/2 w/PLL 4x PLL 1 1 1 1 0 0 0 1 OSC2
HS/2 w/PLL 8x PLL 1 1 1 1 0 0 1 0 OSC2
HS/2 w/PLL 16x PLL 1 1 1 1 0 0 1 1 OSC2
HS/3 w/PLL 4x PLL 1 1 1 1 0 1 0 1 OSC2
HS/3 w/PLL 8x PLL 1 1 1 1 0 1 1 0 OSC2
HS/3 w/PLL 16x PLL 1 1 1 1 0 1 1 1 OSC2
ECIO External 0 1 1 0 1 1 0 0 I/O
XT External 0 1 1 0 0 1 0 0 OSC2
HS External 0 1 1 0 0 0 1 0 OSC2
EC External 0 1 1 0 1 0 1 1 CLKO
ERC External 0 1 1 0 1 0 0 1 CLKO
ERCIO External 0 1 1 0 1 0 0 0 I/O
XTL External 0 1 1 0 0 0 0 0 OSC2
LP Secondary 0 0 0 x x x x x (Note 1, 2)
FRC Internal FRC 0 0 1 x x x x x (Note 1, 2)
LPRC Internal LPRC 0 1 0 x x x x x (Note 1, 2)
Note 1: The OC2 pin is usable as general-purpose I/O pin functionality only, depending on the Primary Oscillator
mode selection (FPR<4:0>).
2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is
selected at all times.

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21.2.2 OSCILLATOR START-UP TIMER 21.2.5 FAST RC OSCILLATOR (FRC)
(OST) The FRC oscillator is a fast (7.37 MHz nominal) internal
In order to ensure that a crystal oscillator (or ceramic RC oscillator. This oscillator is intended to provide
resonator) has started and stabilized, an Oscillator reasonable device operating speeds without the use of
Start-up Timer is included. It is a simple 10-bit counter an external crystal, ceramic resonator or RC network.
that counts 1024 TOSC cycles before releasing the The FRC oscillator can be used with the PLL to obtain
oscillator clock to the rest of the system. The time-out higher clock frequencies.
period is designated as TOST. The TOST time is involved The dsPIC30F operates from the FRC oscillator
every time the oscillator has to restart (i.e., on POR, whenever the current oscillator selection control bits in
BOR and wake-up from Sleep). The Oscillator Start-up the OSCCON register (OSCCON<14:12>) are set to
Timer is applied to the LP, XT, XTL and HS Oscillator ‘001’.
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator. The 6-bit field specified by TUN<5:0> (OSCTUN<5:0>)
allows the user to tune the internal fast RC oscillator
21.2.3 LP OSCILLATOR CONTROL (nominal 7.37 MHz). The user can tune the FRC
oscillator within a range of +12.6% (930 kHz) and -13%
Enabling the LP oscillator is controlled with two (960 kHz) in steps of 0.4% around the
elements: factory-calibrated setting, see Table 20-4.
• The current oscillator group bits COSC<2:0> If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are
• The LPOSCEN bit (OSCCON register) set to ‘00101’, ‘00110’ or ‘00111’, then a PLL
The LP oscillator is ON (even during Sleep mode) if multiplier of 4, 8 or 16 (respectively) is applied.
LPOSCEN = 1. The LP oscillator is the device clock if:
Note: When a 16x PLL is used, the FRC
• COSC<2:0> = 000 (LP selected as main oscillator) oscillator must not be tuned to a frequency
and greater than 7.5 MHz.
• LPOSCEN = 1
Keeping the LP oscillator ON at all times allows for a TABLE 21-4: FRC TUNING
fast switch to the 32 kHz system clock for lower power TUN<5:0>
FRC Frequency
operation. Returning to the faster main oscillator will Bits
still require a start-up time. 01 1111 +12.6%
01 1110 +12.2%
21.2.4 PHASE LOCKED LOOP (PLL)
01 1101 +11.8%
The PLL multiplies the clock which is generated by the ... ...
primary oscillator. The PLL is selectable to have either
00 0100 +1.6%
gains of x4, x8 and x16. Input and output frequency
ranges are summarized in Table 21-3. 00 0011 +1.2%
00 0010 +0.8%
TABLE 21-3: PLL FREQUENCY RANGE 00 0001 +0.4%
PLL 00 0000 Center Frequency (oscillator is
Fin Fout running at calibrated frequency)
Multiplier
4 MHz-10 MHz x4 16 MHz-40 MHz 11 1111 -0.4%
11 1110 -0.8%
4 MHz-10 MHz x8 32 MHz-80 MHz
11 1101 -1.2%
4 MHz-7.5 MHz x16 64 MHz-120 MHz
11 1100 -1.6%
The PLL features a lock output, which is asserted when ... ...
the PLL enters a phase locked state. Should the loop
10 0011 -11.8%
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the 10 0010 -12.2%
read-only LOCK bit in the OSCCON register. 10 0001 -12.6%
10 0000 -13.0%

© 2008 Microchip Technology Inc. DS70150D-page 153

dsPIC30F6010A/6015
21.2.6 LOW-POWER RC OSCILLATOR the FSCM will initiate a clock failure trap, and the
(LPRC) COSC<2:0> bits are loaded with FRC oscillator
selection. This will effectively shut-off the original
The LPRC oscillator is a component of the Watchdog
oscillator that was trying to start.
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for The user may detect this situation and restart the
the Power-up Timer (PWRT) circuit, WDT and clock oscillator in the clock fail trap ISR.
monitor circuits. It may also be used to provide a low Upon a clock failure detection, the FSCM module will
frequency clock source option for applications where initiate a clock switch to the FRC oscillator as follows:
power consumption is critical, and timing accuracy is
1. The COSC bits (OSCCON<14:12>) are loaded
not required.
with the FRC oscillator selection value.
The LPRC oscillator is always enabled at a Power-on 2. CF bit is set (OSCCON<3>).
Reset, because it is the clock source for the PWRT.
3. OSWEN control bit (OSCCON<0>) is cleared.
After the PWRT expires, the LPRC oscillator will remain
ON if one of the following is TRUE: For the purpose of clock switching, the clock sources
are sectioned into four groups:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled • Primary
• Secondary
• The LPRC oscillator is selected as the system
• Internal FRC
clock via the COSC<2:0> control bits in the
• Internal LPRC
OSCCON register
The user can switch between these functional groups,
If one of the above conditions is not true, the LPRC will
but cannot switch between options within a group. If the
shut-off after the PWRT expires.
primary group is selected, then the choice within the
Note 1: OSC2 pin function is determined by the group is always determined by the FPR<4:0>
Primary Oscillator mode selection Configuration bits.
(FPR<4:0>).
The OSCCON register holds the control and Status bits
2: Note that OSC1 pin cannot be used as an related to clock switching.
I/O pin, even if the secondary oscillator or
• COSC<2:0>: Read-only Status bits always reflect
an internal clock source is selected at all
the current oscillator group in effect.
times.
• NOSC<2:0>: Control bits which are written to
21.2.7 FAIL-SAFE CLOCK MONITOR indicate the new oscillator group of choice.
- On POR and BOR, COSC<2:0> and
The Fail-Safe Clock Monitor (FSCM) allows the device
NOSC<2:0> are both loaded with the
to continue to operate even in the event of an oscillator
Configuration bit values FOS<2:0>.
failure. The FSCM function is enabled by appropriately
programming the FCKSM Configuration bits (Clock • LOCK: The LOCK Status bit indicates a PLL lock.
Switch and Monitor Selection bits) in the FOSC device • CF: Read-only Status bit indicating if a clock fail
Configuration register. If the FSCM function is detect has occurred.
enabled, the LPRC internal oscillator will run at all • OSWEN: Control bit changes from a ‘0’ to a ‘1’
times (except during Sleep mode) and will not be when a clock transition sequence is initiated.
subject to control by the SWDTEN bit. Clearing the OSWEN control bit will abort a clock
In the event of an oscillator failure, the FSCM will transition in progress (used for hang-up situations).
generate a clock failure trap event and will switch the If Configuration bits FCKSM<1:0> = 1x, then the clock
system clock over to the FRC oscillator. The user will switching and Fail-Safe Clock Monitor functions are
then have the option to either attempt to restart the disabled. This is the default Configuration bit setting.
oscillator or execute a controlled shutdown. The user If clock switching is disabled, then the FOS<2:0> and
may decide to treat the trap as a warm Reset by simply FPR<4:0> bits directly control the oscillator selection
loading the Reset address into the oscillator fail trap and the COSC<2:0> bits do not control the clock
vector. In this event, the CF (Clock Fail) Status bit selection. However, these bits will reflect the clock
(OSCCON<3>) is also set whenever a clock failure is source selection.
recognized.
In the event of a clock failure, the WDT is unaffected Note: The application should not attempt to
and continues to run on the LPRC clock. switch to a clock of frequency lower than
100 kHz when the Fail-Safe Clock Monitor
If the oscillator has a very slow start-up time coming is enabled. If clock switching is performed,
out of POR, BOR or Sleep, it is possible that the the device may generate an oscillator fail
PWRT timer will expire before the oscillator has trap and switch to the fast RC oscillator.
started. In such cases, the FSCM will be activated and

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 dsPIC30F6010A/6015
21.2.8 PROTECTION AGAINST 21.3 Reset
ACCIDENTAL WRITES TO OSCCON
The dsPIC30F differentiates between various kinds of
A write to the OSCCON register is intentionally made Reset:
difficult because it controls clock switching and clock
a) Power-on Reset (POR)
scaling.
b) MCLR Reset during normal operation
To write to the OSCCON low byte, the following code
c) MCLR Reset during Sleep
sequence must be executed without any other
instructions in between: d) Watchdog Timer (WDT) Reset (during normal
operation)
Byte Write “0x46” to OSCCON low e) Programmable Brown-out Reset (BOR)
Byte Write “0x57” to OSCCON low
f) RESET Instruction
Byte write is allowed for one instruction cycle. Write the g) Reset caused by trap lockup (TRAPR)
desired value or use bit manipulation instruction. h) Reset caused by illegal opcode, or by using an
To write to the OSCCON high byte, the following uninitialized W register as an Address Pointer
instructions must be executed without any other (IOPUWR)
instructions in between: Different registers are affected in different ways by
various Reset conditions. Most registers are not
Byte Write “0x78” to OSCCON high
affected by a WDT wake-up, since this is viewed as the
Byte Write “0x9A” to OSCCON high
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Byte write is allowed for one instruction cycle. Write the
Reset situations, as indicated in Table 21-5. These bits
desired value or use bit manipulation instruction.
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.

FIGURE 21-2: RESET SYSTEM BLOCK DIAGRAM

RESET
Instruction

Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module

VDD Rise POR

Detect S
VDD
Brown-out BOR
Reset
BOREN
R Q
SYSRST
Trap Conflict

Illegal Opcode/
Uninitialized W Register

© 2008 Microchip Technology Inc. DS70150D-page 155

dsPIC30F6010A/6015
21.3.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
A power-on event will generate an internal POR pulse
circuits are stable. Furthermore, a user selected
when a VDD rise is detected. The Reset pulse will occur
power-up time-out (TPWRT) is applied. The TPWRT
at the POR circuit threshold voltage (VPOR), which is
parameter is based on device Configuration bits and
nominally 1.85V. The device supply voltage
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
characteristics must meet specified starting voltage
delay is at device power-up TPOR + TPWRT. When
and rise rate requirements. The POR pulse will reset a
these delays have expired, SYSRST will be negated on
POR timer and place the device in the Reset state. The
the next leading edge of the Q1 clock, and the PC will
POR also selects the device clock source identified by
jump to the Reset vector.
the oscillator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.

FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

Internal POR

TOST
OST Time-out
TPWRT

PWRT Time-out

Internal Reset

FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

Internal POR

TOST
OST Time-out
TPWRT

PWRT Time-out

Internal Reset

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 dsPIC30F6010A/6015
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

Internal POR

TOST
OST Time-out
TPWRT

PWRT Time-out

Internal Reset

21.3.1.1 POR with Long Crystal Start-up Time 21.3.2 BOR: PROGRAMMABLE
(with FSCM Enabled) BROWN-OUT RESET
The oscillator start-up circuitry is not linked to the POR The BOR (Brown-out Reset) module is based on an
circuitry. Some crystal circuits (especially low frequency internal voltage reference circuit. The main purpose of
crystals) will have a relatively long start-up time. the BOR module is to generate a device Reset when a
Therefore, one or more of the following conditions is brown-out condition occurs. Brown-out conditions are
possible after the POR timer and the PWRT have generally caused by glitches on the AC mains (i.e.,
expired: missing portions of the AC cycle waveform due to bad
• The oscillator circuit has not begun to oscillate. power transmission lines or voltage sags due to exces-
sive current draw when a large inductive load is turned
• The Oscillator Start-up Timer has NOT expired (if
on).
a crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is The BOR module allows selection of one of the
used). following voltage trip points:

If the FSCM is enabled and one of the above conditions • 2.6V–2.71V

is true, then a clock failure trap will occur. The device • 4.1V–4.4V
will automatically switch to the FRC oscillator and the • 4.58V–4.73V
user can switch to the desired crystal oscillator in the
Note: The BOR voltage trip points indicated here
trap ISR.
are nominal values provided for design
21.3.1.2 Operating without FSCM and PWRT guidance only.

If the FSCM is disabled and the Power-up Timer A BOR will generate a Reset pulse which will reset the
(PWRT) is also disabled, then the device will exit rapidly device. The BOR will select the clock source, based on
from Reset on power-up. If the clock source is FRC, the device Configuration bit values (FOS<2:0> and
LPRC, EXTRC or EC, it will be active immediately. FPR<4:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
If the FSCM is disabled and the system clock has not Timer (OST). The system clock is held until OST
started, the device will be in a frozen state at the Reset expires. If the PLL is used, then the clock will be held
vector until the system clock starts. From the user’s until the LOCK bit (OSCCON<5>) is ‘1’.
perspective, the device will appear to be in Reset until
a system clock is available.

© 2008 Microchip Technology Inc. DS70150D-page 157

dsPIC30F6010A/6015
Concurrently, the POR time-out (TPOR) and the PWRT FIGURE 21-6: EXTERNAL POWER-ON
time-out (TPWRT) will be applied before the internal RESET CIRCUIT (FOR
Reset is released. If TPWRT = 0 and a crystal oscillator SLOW VDD POWER-UP)
is being used, then a nominal delay of TFSCM = 100 μs VDD
is applied. The total delay in this case is
(TPOR + TFSCM).
D R
The BOR Status bit (RCON<1>) will be set to indicate R1
that a BOR has occurred. The BOR circuit, if enabled, MCLR
will continue to operate while in Sleep or Idle modes C dsPIC30F
and will reset the device should VDD fall below the BOR
threshold voltage.
Note 1: External Power-on Reset circuit is
required only if the VDD power-up slope
is too slow. The diode D helps discharge
the capacitor quickly when VDD powers
down.
2: R should be suitably chosen so as to
make sure that the voltage drop across
R does not violate the device’s electrical
specification.
3: R1 should be suitably chosen so as to
limit any current flowing into MCLR from
external capacitor C, in the event of
MCLR/VPP pin breakdown due to Elec-
trostatic Discharge (ESD) or Electrical
Overstress (EOS).

Note: Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.

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 dsPIC30F6010A/6015
Table 21-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.
TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Program
Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1
MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0
operation
Software Reset during 0x000000 0 0 0 1 0 0 0 0 0
normal operation
MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0
MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0
WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0
WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0
Interrupt Wake-up from PC + 2(1) 0 0 0 0 0 0 1 0 0
Sleep
Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0
Trap Reset 0x000000 1 0 0 0 0 0 0 0 0
Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

Table 21-6 shows a second example of the bit

conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 21-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Program
Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 u u u u u u u 0 1
MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u
operation
Software Reset during 0x000000 u u 0 1 0 0 0 u u
normal operation
MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u
MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u
WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u
WDT Wake-up PC + 2 u u u u 1 u 1 u u
Interrupt Wake-up from PC + 2(1) u u u u u u 1 u u
Sleep
Clock Failure Trap 0x000004 u u u u u u u u u
Trap Reset 0x000000 1 u u u u u u u u
Illegal Operation Reset 0x000000 u 1 u u u u u u u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

© 2008 Microchip Technology Inc. DS70150D-page 159

dsPIC30F6010A/6015
21.4 Watchdog Timer (WDT) The processor wakes up from Sleep if at least one of
the following conditions has occurred:
21.4.1 WATCHDOG TIMER OPERATION • any interrupt that is individually enabled and
The primary function of the Watchdog Timer (WDT) is meets the required priority level
to reset the processor in the event of a software • any Reset (POR, BOR and MCLR)
malfunction. The WDT is a free running timer, which • WDT time-out
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to On waking up from Sleep mode, the processor will
operate even if the main processor clock (e.g., the restart the same clock that was active prior to entry
crystal oscillator) fails. into Sleep mode. When clock switching is enabled,
bits COSC<2:0> will determine the oscillator source
21.4.2 ENABLING AND DISABLING THE that will be used on wake-up. If clock switch is
WDT disabled, then there is only one system clock.

The Watchdog Timer can be “Enabled” or “Disabled” Note: If a POR or BOR occurred, the selection of
only through a Configuration bit (FWDTEN) in the the oscillator is based on the FOS<2:0>
Configuration register FWDT. and FPR<4:0> Configuration bits.
Setting FWDTEN = 1 enables the Watchdog Timer. If the clock source is an oscillator, the clock to the
The enabling is done when programming the device. device is held off until OST times out (indicating a
By default, after chip-erase, FWDTEN bit = 1. Any stable oscillator). If PLL is used, the system clock is
device programmer capable of programming held off until LOCK = 1 (indicating that the PLL is
dsPIC30F devices allows programming of this and stable). Either way, TPOR, TLOCK and TPWRT delays are
other Configuration bits. applied.
If enabled, the WDT will increment until it overflows or If EC, FRC, LPRC or ERC oscillators are used, then a
“times out”. A WDT time-out will force a device Reset delay of TPOR (~ 10 μs) is applied. This is the smallest
(except during Sleep). To prevent a WDT time-out, the delay possible on wake-up from Sleep.
user must clear the Watchdog Timer using a CLRWDT Moreover, if LP oscillator was active during Sleep, and
instruction. LP is the oscillator used on wake-up, then the start-up
If a WDT times out during Sleep, the device will delay will be equal to TPOR. PWRT delay and OST
wake-up. The WDTO bit in the RCON register will be timer delay are not applied. In order to have the
cleared to indicate a wake-up resulting from a WDT smallest possible start-up delay when waking up from
time-out. Sleep, one of these faster wake-up options should be
selected before entering Sleep.
Setting FWDTEN = 0 allows user software to
enable/disable the Watchdog Timer via the SWDTEN Any interrupt that is individually enabled (using the
(RCON<5>) control bit. corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The
21.5 Power-Saving Modes processor will process the interrupt and branch to the
ISR. The Sleep Status bit in RCON register is set upon
There are two power-saving states that can be entered wake-up.
through the execution of a special instruction, PWRSAV.
Note: In spite of various delays applied (TPOR,
These are: Sleep and Idle.
TLOCK and TPWRT), the crystal oscillator
The format of the PWRSAV instruction is as follows: (and PLL) may not be active at the end of
PWRSAV <parameter>, where ‘parameter’ defines the time-out (e.g., for low-frequency
Idle or Sleep mode. crystals). In such cases, if FSCM is
enabled, then the device will detect this as
21.5.1 SLEEP MODE a clock failure and process the clock failure
trap, the FRC oscillator will be enabled, and
In Sleep mode, the clock to the CPU and peripherals is
the user will have to re-enable the crystal
shut down. If an on-chip oscillator is being used, it is
oscillator. If FSCM is not enabled, then the
shut down.
device will simply suspend execution of
The Fail-Safe Clock Monitor is not functional during code until the clock is stable, and will
Sleep, since there is no clock to monitor. However, remain in Sleep until the oscillator clock has
LPRC clock remains active if WDT is operational during started.
Sleep.
All Resets will wake-up the processor from Sleep
The Brown-out protection circuit, if enabled, will remain mode. Any Reset, other than POR, will set the Sleep
functional during Sleep. Status bit. In a POR, the Sleep bit is cleared.

DS70150D-page 160 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
If Watchdog Timer is enabled, then the processor will 21.6 Device Configuration Registers
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO Status bits are both set. The Configuration bits in each device Configuration
register specify some of the device modes and are
21.5.2 IDLE MODE programmed by a device programmer, or by using the
In-Circuit Serial Programming™ (ICSP™) feature of the
In Idle mode, the clock to the CPU is shutdown while
device. Each device Configuration register is a 24-bit
peripherals keep running. Unlike Sleep mode, the clock
register, but only the lower 16 bits of each register are
source remains active.
used to hold configuration data. There are six device
Several peripherals have a control bit in each module, Configuration registers available to the user:
that allows them to operate during Idle.
1. FOSC (0xF80000): Oscillator Configuration
LPRC fail-safe clock remains active if clock failure register
detect is enabled. 2. FWDT (0xF80002): Watchdog Timer
The processor wakes up from Idle if at least one of the Configuration register
following conditions is true: 3. FBORPOR (0xF80004): BOR and POR
• on any interrupt that is individually enabled (IE bit Configuration register
is ‘1’) and meets the required priority level 4. FBS (0xF80006): Boot Code Segment
• on any Reset (POR, BOR, MCLR) Configuration register
• on WDT time-out 5. FSS (0xF80008): Secure Code Segment
Configuration register
Upon wake-up from Idle mode, the clock is re-applied
6. FGS (0xF8000A): General Code Segment
to the CPU and instruction execution begins
Configuration register
immediately, starting with the instruction following the
PWRSAV instruction. 7. FICD (0xF8000C): FUSE Configuration
Register
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to The placement of the Configuration bits is automatically
wake-up the processor. The processor will process the handled when you select the device in your device
interrupt and branch to the ISR. The Idle Status bit in programmer. The desired state of the Configuration bits
RCON register is set upon wake-up. may be specified in the source code (dependent on the
language tool used), or through the programming
Any Reset, other than POR, will set the Idle Status bit. interface. After the device has been programmed, the
On a POR, the Idle bit is cleared. application software may read the Configuration bit
If Watchdog Timer is enabled, then the processor will values through the table read instructions. For additional
wake-up from Idle mode upon WDT time-out. The Idle information, please refer to the “dsPIC30F/33F
and WDTO Status bits are both set. Programmers Reference Manual” (DS70157) and the
Unlike wake-up from Sleep, there are no time delays “dsPIC30F Family Reference Manual” (DS70046).
involved in wake-up from Idle. Note 1: If the code protection Configuration Fuse
bits (FBS(BSS<2:0>), FSS(SSS<2:0>),
FGS<GCP> and FGS<GWRP>) have
been programmed, an erase of the entire
code-protected device is only possible at
voltages VDD ≥ 4.5V.
2: This device supports an Advanced
implementation of CodeGuard™
Security. Please refer to the “CodeGuard
Security” chapter (DS70180) for
information on how CodeGuard Security
may be used in your application.

© 2008 Microchip Technology Inc. DS70150D-page 161

dsPIC30F6010A/6015
21.7 Peripheral Module Disable (PMD) 21.8 In-Circuit Debugger
Registers When MPLAB® ICD 2 is selected as a debugger, the
The Peripheral Module Disable (PMD) registers In-Circuit Debugging functionality is enabled. This
provide a method to disable a peripheral module by function allows simple debugging functions when used
stopping all clock sources supplied to that module. with MPLAB IDE. When the device has this feature
When a peripheral is disabled via the appropriate PMD enabled, some of the resources are not available for
control bit, the peripheral is in a minimum power general use. These resources include the first 80 bytes
consumption state. The control and STATUS registers of data RAM and two I/O pins.
associated with the peripheral will also be disabled so One of four pairs of debug I/O pins may be selected by
writes to those registers will have no effect and read the user using configuration options in MPLAB IDE.
values will be invalid. These pin pairs are named EMUD/EMUC,
A peripheral module will only be enabled if both the EMUD1/EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.
associated bit in the PMD register is cleared and the In each case, the selected EMUD pin is the
peripheral is supported by the specific dsPIC DSC Emulation/Debug Data line, and the EMUC pin is the
variant. If the peripheral is present in the device, it is Emulation/Debug Clock line. These pins will interface
enabled in the PMD register by default. to the MPLAB ICD 2 module available from Microchip.
Note: If a PMD bit is set, the corresponding The selected pair of debug I/O pins is used by MPLAB
module is disabled after a delay of 1 ICD 2 to send commands and receive responses, as
instruction cycle. Similarly, if a PMD bit is well as to send and receive data. To use the In-Circuit
cleared, the corresponding module is Debugger function of the device, the design must
enabled after a delay of 1 instruction cycle implement ICSP connections to MCLR, VDD, VSS,
(assuming the module control registers PGC, PGD and the selected EMUDx/EMUCx pin pair.
are already configured to enable module This gives rise to two possibilities:
operation). 1. If EMUD/EMUC is selected as the debug I/O pin
pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are
multiplexed with the PGD and PGC pin functions
in all dsPIC30F devices.
2. If EMUD1/EMUC1, EMUD2/EMUC2 or
EMUD3/EMUC3 is selected as the debug I/O
pin pair, then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.

DS70150D-page 162 © 2008 Microchip Technology Inc.

 TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F6010A(1)
© 2008 Microchip Technology Inc.

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset.
OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits.
OSCTUN 0744 — — — — — — — — — — TUN<5:0> 0000 0000 0000 0000
PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD — I2CMD U2MD U1MD SPI2MD SPI1MD C2MD C1MD ADCMD 0000 0000 0000 0000
PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

TABLE 21-8: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F6015(1)

SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name

RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset.
OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits.
OSCTUN 0744 — — — — — — — — — — TUN<5:0> 0000 0000 0000 0000
PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD — I2CMD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD 0000 0000 0000 0000
PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F6010A/6015
TABLE 21-9: DEVICE CONFIGURATION REGISTER MAP(1)
File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FOSC F80000 — FCKSM<1:0> — — — FOS<2:0> — — — FPR<4:0>

FWDT F80002 — FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 — MCLREN — — — — PWMPIN HPOL LPOL BOREN — BORV<1:0> — — FPWRT<1:0>
FBS F80006 RBS1 RBS0 EBS BSS<2:0> BWRP
FSS F80008 RSS1 RSS0 ESS1 ESS0 SSS<2:0> SWRP
FGS F8000A — — — — — — — — — — — — — — GSS<1:0> GWRP
FICD F8000C — — — — — — — — — BKBUG COE — — — — ICS<1:0>
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70150D-page 163
dsPIC30F6010A/6015
NOTES:

DS70150D-page 164 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
22.0 INSTRUCTION SET SUMMARY Most bit oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes features of
• The W register (with or without an address
this group of dsPIC30F devices and is not
modifier) or file register (specified by the value of
intended to be a complete reference
‘Ws’ or ‘f’)
source. For more information on the CPU,
peripherals, register descriptions and • The bit in the W register or file register
general device functionality, refer to the (specified by a literal value, or indirectly by the
“dsPIC30F Family Reference Manual” contents of register ‘Wb’)
(DS70046). For more information on the The literal instructions that involve data movement may
device instruction set and programming, use some of the following operands:
refer to the “dsPIC30F/33F Programmers
• A literal value to be loaded into a W register or file
Reference Manual” (DS70157).
register (specified by the value of ‘k’)
The dsPIC30F instruction set adds many • The W register or file register where the literal
enhancements to the previous PIC® Microcontroller value is to be loaded (specified by ‘Wb’ or ‘f’)
(MCU) instruction sets, while maintaining an easy
However, literal instructions that involve arithmetic or
migration from PIC MCU instruction sets.
logical operations use some of the following operands:
Most instructions are a single program memory word
• The first source operand, which is a register ‘Wb’
(24-bits). Only three instructions require two program
without any address modifier
memory locations.
• The second source operand, which is a literal
Each single-word instruction is a 24-bit word divided value
into an 8-bit opcode which specifies the instruction
• The destination of the result (only if not the same
type, and one or more operands which further specify
as the first source operand), which is typically a
the operation of the instruction.
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
The MAC class of DSP instructions may use some of the
into five basic categories:
following operands:
• Word or byte-oriented operations
• The accumulator (A or B) to be used (required
• Bit-oriented operations operand)
• Literal operations • The W registers to be used as the two operands
• DSP operations • The X and Y address space prefetch operations
• Control operations • The X and Y address space prefetch destinations
Table 22-1 shows the general symbols used in • The accumulator write-back destination
describing the instructions.
The other DSP instructions do not involve any
The dsPIC30F instruction set summary in Table 22-2 multiplication, and may include:
lists all the instructions along with the Status flags
• The accumulator to be used (required)
affected by each instruction.
• The source or destination operand (designated as
Most word or byte-oriented W register instructions Wso or Wdo, respectively) with or without an
(including barrel shift instructions) have three address modifier
operands:
• The amount of shift, specified by a W register ‘Wn’
• The first source operand, which is typically a or a literal value
register ‘Wb’ without any address modifier
The control instructions may use some of the following
• The second source operand, which is typically a operands:
register ‘Ws’ with or without an address modifier
• A program memory address
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier • The mode of the table read and table write
instructions
However, word or byte-oriented file register instructions
have two operands: All instructions are a single word, except for certain
double word instructions, which were made double
• The file register specified by the value ‘f’ word instructions so that all the required information is
• The destination, which could either be the file available in these 48 bits. In the second word, the
register ‘f’ or the W0 register, which is denoted as 8 MSbs are ‘0’s. If this second word is executed as an
‘WREG’ instruction (by itself), it will execute as a NOP.

© 2008 Microchip Technology Inc. DS70150D-page 165

dsPIC30F6010A/6015
Most single-word instructions are executed in a single require either two or three cycles if the skip is
instruction cycle, unless a conditional test is true or the performed, depending on whether the instruction being
program counter is changed as a result of the skipped is a single-word or two-word instruction.
instruction. In these cases, the execution takes two Moreover, double word moves require two cycles. The
instruction cycles with the additional instruction double word instructions execute in two instruction
cycle(s) executed as a NOP. Notable exceptions are the cycles.
BRA (unconditional/computed branch), indirect CALL/ Note: For more details on the instruction set,
GOTO, all table reads and writes and RETURN/RETFIE refer to the “dsPIC30F/33F Programmers
instructions, which are single-word instructions, but Reference Manual” (DS70157).
take two or three cycles. Certain instructions that
involve skipping over the subsequent instruction,

TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description
#text Means literal defined by “text”
(text) Means “content of “text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator Write-Back Destination Address register ∈ {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address ∈ {0x0000...0x1FFF}
lit1 1-bit unsigned literal ∈ {0,1}
lit4 4-bit unsigned literal ∈ {0...15}
lit5 5-bit unsigned literal ∈ {0...31}
lit8 8-bit unsigned literal ∈ {0...255}
lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal ∈ {0...16384}
lit16 16-bit unsigned literal ∈ {0...65535}
lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’
None Field does not require an entry, may be blank
OA, OB, SA, SB DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
PC Program Counter
Slit10 10-bit signed literal ∈ {-512...511}
Slit16 16-bit signed literal ∈ {-32768...32767}
Slit6 6-bit signed literal ∈ {-16...16}

DS70150D-page 166 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wb Base W register ∈ {W0..W15}
Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn One of 16 working registers ∈ {W0..W15}
Wnd One of 16 destination working registers ∈ {W0..W15}
Wns One of 16 source working registers ∈ {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space prefetch address register for DSP instructions
∈ {[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2,
[W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2,
[W9+W12], none}
Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7}
Wy Y data space prefetch address register for DSP instructions
∈ {[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2,
[W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2,
[W11+W12], none}
Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

© 2008 Microchip Technology Inc. DS70150D-page 167

dsPIC30F6010A/6015
TABLE 22-2: INSTRUCTION SET OVERVIEW
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic words cycles Affected
#
1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,S
B
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,S
B
2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3 AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6 BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if greater than or equal 1 1 (2) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None
BRA GT,Expr Branch if greater than 1 1 (2) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None
BRA LE,Expr Branch if less than or equal 1 1 (2) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None
BRA LT,Expr Branch if less than 1 1 (2) None
BRA LTU,Expr Branch if unsigned less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None
BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None
BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
7 BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
9 BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)

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 dsPIC30F6010A/6015
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic words cycles Affected
#
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None
(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call indirect Subroutine 1 2 None
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,S
B
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f=f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z
(Wb – Ws – C)
21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None
(2 or 3)
22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None
(2 or 3)
23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None
(2 or 3)
24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None
(2 or 3)
25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
26 DEC DEC f f = f –1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f –1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f=f–2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C, OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C, OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C, OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C, OV
30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C, OV
31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None
DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB

© 2008 Microchip Technology Inc. DS70150D-page 169

dsPIC30F6010A/6015
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic words cycles Affected
#
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to address 2 2 None
GOTO Wn Go to indirect 1 2 None
39 INC INC f f=f+1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f=f+2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
43 LNK LNK #lit14 Link Frame Pointer 1 1 None
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate 1 1 OA,OB,OAB,
AWB SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 N,Z
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N,Z
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store Accumulator 1 1 None
48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
AWB SA,SB,SAB
51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None

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 dsPIC30F6010A/6015
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic words cycles Affected
#
52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f=f+1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
53 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None
W(nd):W(nd+1)
POP.S Pop Shadow Registers 1 1 All
55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns +1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
57 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
59 RESET RESET Software device Reset 1 1 None
60 RETFIE RETFIE Return from interrupt 1 3 (2) None
61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None
62 RETURN RETURN Return from Subroutine 1 3 (2) None
63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
68 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z
69 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
71 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

© 2008 Microchip Technology Inc. DS70150D-page 171

dsPIC30F6010A/6015
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic words cycles Affected
#
72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 - (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z
75 SUBBR SUBBR f f = WREG – f - (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
81 ULNK ULNK Unlink Frame Pointer 1 1 None
82 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N

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 dsPIC30F6010A/6015
23.0 DEVELOPMENT SUPPORT 23.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers are supported with a full
range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit
microcontroller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB REAL ICE™ In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
- PICkit™ 2 Development Programmer • Integration of select third party tools, such as
• Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR
Boards and Evaluation Kits C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

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dsPIC30F6010A/6015
23.2 MPASM Assembler 23.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline • Command line interface
assembly code • Rich directive set
• Conditional assembly for multi-purpose • Flexible macro language
source files • MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process 23.6 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
23.3 MPLAB C18 and MPLAB C30
development in a PC-hosted environment by
C Compilers simulating the PIC MCUs and dsPIC® DSCs on an
The MPLAB C18 and MPLAB C30 Code Development instruction level. On any given instruction, the data
Systems are complete ANSI C compilers for areas can be examined or modified and stimuli can be
Microchip’s PIC18 and PIC24 families of applied from a comprehensive stimulus controller.
microcontrollers and the dsPIC30 and dsPIC33 family Registers can be logged to files for further run-time
of digital signal controllers. These compilers provide analysis. The trace buffer and logic analyzer display
powerful integration capabilities, superior code extend the power of the simulator to record and track
optimization and ease of use not found with other program execution, actions on I/O, most peripherals
compilers. and internal registers.

For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports
symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and
debugger. MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
23.4 MPLINK Object Linker/
of the hardware laboratory environment, making it an
MPLIB Object Librarian excellent, economical software development tool.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

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 dsPIC30F6010A/6015
23.7 MPLAB ICE 2000 23.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PIC
complete microcontroller design tool set for PIC MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
2000 In-Circuit Emulator is advanced by the MPLAB the in-circuit debugging capability built into the Flash
Integrated Development Environment, which allows devices. This feature, along with Microchip’s In-Circuit
editing, building, downloading and source debugging Serial ProgrammingTM (ICSPTM) protocol, offers
from a single environment. cost-effective, in-circuit Flash debugging from the graph-
ical user interface of the MPLAB Integrated Develop-
The MPLAB ICE 2000 is a full-featured emulator ment Environment. This enables a designer to develop
system with enhanced trace, trigger and data monitor- and debug source code by setting breakpoints, single
ing features. Interchangeable processor modules allow stepping and watching variables, and CPU status and
the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables
different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB
ICE 2000 In-Circuit Emulator allows expansion to ICD 2 also serves as a development programmer for
support new PIC microcontrollers. selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 23.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a
modular, detachable socket assembly to support
23.8 MPLAB REAL ICE In-Circuit
various package types. The ICSP™ cable assembly is
Emulator System included as a standard item. In Stand-Alone mode, the
MPLAB REAL ICE In-Circuit Emulator System is MPLAB PM3 Device Programmer can read, verify and
Microchip’s next generation high-speed emulator for program PIC devices without a PC connection. It can
Microchip Flash DSC and MCU devices. It debugs and also set code protection in this mode. The MPLAB PM3
programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable.
with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and
the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large
included with each kit. memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant,
Low-Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be
supported, and new features will be added, such as
software breakpoints and assembly code trace.
MPLAB REAL ICE offers significant advantages over
competitive emulators including low-cost, full-speed
emulation, real-time variable watches, trace analysis,
complex breakpoints, a ruggedized probe interface and
long (up to three meters) interconnection cables.

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dsPIC30F6010A/6015
23.11 PICSTART Plus Development 23.13 Demonstration, Development and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully
Integrated Development Environment software makes functional systems. Most boards include prototyping
using the programmer simple and efficient. The areas for adding custom circuitry and provide application
PICSTART Plus Development Programmer supports firmware and source code for examination and
most PIC devices in DIP packages up to 40 pins. modification.
Larger pin count devices, such as the PIC16C92X and The boards support a variety of features, including LEDs,
PIC17C76X, may be supported with an adapter socket. temperature sensors, switches, speakers, RS-232
The PICSTART Plus Development Programmer is CE interfaces, LCD displays, potentiometers and additional
compliant. EEPROM memory.
The demonstration and development boards can be
23.12 PICkit 2 Development Programmer
used in teaching environments, for prototyping custom
The PICkit™ 2 Development Programmer is a low-cost circuits and for learning about various microcontroller
programmer and selected Flash device debugger with applications.
an easy-to-use interface for programming many of In addition to the PICDEM™ and dsPICDEM™
Microchip’s baseline, mid-range and PIC18F families of demonstration/development board series of circuits,
Flash memory microcontrollers. The PICkit 2 Starter Kit Microchip has a line of evaluation kits and
includes a prototyping development board, twelve demonstration software for analog filter design,
sequential lessons, software and HI-TECH’s PICC™ KEELOQ® security ICs, CAN, IrDA®, PowerSmart
Lite C compiler, and is designed to help get up to speed battery management, SEEVAL® evaluation system,
quickly using PIC® microcontrollers. The kit provides Sigma-Delta ADC, flow rate sensing, plus many more.
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range Check the Microchip web page (www.microchip.com)
Flash memory family of microcontrollers. for the complete list of demonstration, development
and evaluation kits.

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 dsPIC30F6010A/6015
24.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual”
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1) ..................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS........................................................................................................ 0V to +13.25V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 2)................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 24-6.

†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

© 2008 Microchip Technology Inc. DS70150D-page 177

dsPIC30F6010A/6015
24.1 DC Characteristics

TABLE 24-1: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6010A

VDD Range Temp Range Max MIPS
(in Volts) (in °C) dsPIC30F6010A-30I dsPIC30F6010A-20E
4.5-5.5 -40 to +85 30 —
4.5-5.5 -40 to +125 — 20
3.0-3.6 -40 to +85 20 —
3.0-3.6 -40 to +125 — 15
2.5-3.0 -40 to +85 10 —

TABLE 24-2: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6015

VDD Range Temp Range Max MIPS
(in Volts) (in °C) dsPIC30F6015-30I dsPIC30F6015-20E
4.5-5.5 -40 to +85 30 —
4.5-5.5 -40 to +125 — 20
3.0-3.6 -40 to +85 20 —
3.0-3.6 -40 to +125 — 15
2.5-3.0 -40 to +85 10 —

TABLE 24-3: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit
dsPIC30F6010A-30I/dsPIC30F6015-30I
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
dsPIC30F6010A-20E/dsPIC30F6015-20E
Operating Junction Temperature Range TJ -40 — +150 °C
Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal chip power dissipation:
P INT = V D D × ( I DD – ∑ I O H) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O =
∑ ( { VD D – VO H } × IOH ) + ∑ ( VOL × I OL )
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W

TABLE 24-4: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 80-pin TQFP (14x14x1mm) θJA 36 — °C/W 1
Package Thermal Resistance, 80-pin TQFP (12x12x1mm) θJA 39 — °C/W 1
Package Thermal Resistance, 64-pin TQFP (10x10x1mm) θJA 39 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.

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 dsPIC30F6010A/6015
TABLE 24-5: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Operating Voltage(2)
DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature
DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature
DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V
DC16 VPOR VDD Start Voltage — — VSS V
to ensure internal
Power-on Reset signal
DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-5V in 0.1 sec
to ensure internal 0-3V in 60 ms
Power-on Reset signal
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: This is the limit to which VDD can be lowered without losing RAM data.

© 2008 Microchip Technology Inc. DS70150D-page 179

dsPIC30F6010A/6015
TABLE 24-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1) Max Units Conditions
No.
Operating Current (IDD)(2)
DC31a 9.5 15 mA 25°C
DC31b 9.5 15 mA 85°C 3.3V
DC31c 9.4 15 mA 125°C 0.128 MIPS
DC31e 18 27 mA 25°C LPRC (512 kHz)
DC31f 17 27 mA 85°C 5V
DC31g 17 27 mA 125°C
DC30a 15 23 mA 25°C
DC30b 15 23 mA 85°C 3.3V
DC30c 14 23 mA 125°C (1.8 MIPS)
DC30e 30 45 mA 25°C FRC (7.37 MHz)
DC30f 29 45 mA 85°C 5V
DC30g 27 45 mA 125°C
DC23a 40 50 mA 25°C
DC23b 40 50 mA 85°C 3.3V
DC23c 36 50 mA 125°C
4 MIPS
DC23e 44 64 mA 25°C
DC23f 43 64 mA 85°C 5V
DC23g 43 64 mA 125°C
DC24a 50 75 mA 25°C
DC24b 51 75 mA 85°C 3.3V
DC24c 51 75 mA 125°C
10 MIPS
DC24e 85 125 mA 25°C
DC24f 84 125 mA 85°C 5V
DC24g 84 125 mA 125°C
DC27a 89 115 mA 25°C
3.3V
DC27b 89 115 mA 85°C
DC27d 147 185 mA 25°C 20 MIPS
DC27e 146 185 mA 85°C 5V
DC27f 145 185 mA 125°C
DC29a 206 255 mA 25°C
5V 30 MIPS
DC29b 205 255 mA 85°C
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail-to-rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.

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 dsPIC30F6010A/6015
TABLE 24-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1,2) Max Units Conditions
No.
Operating Current (IDD)(3)
DC51a 9.0 14 mA 25°C
DC51b 9.0 14 mA 85°C 3.3V
DC51c 9.0 14 mA 125°C 0.128 MIPS
DC51e 17 26 mA 25°C LPRC (512 kHz)
DC51f 16 26 mA 85°C 5V
DC51g 16 26 mA 125°C
DC50a 11 18 mA 25°C
DC50b 12 18 mA 85°C 3.3V
DC50c 11 18 mA 125°C (1.8 MIPS)
DC50e 25 38 mA 25°C FRC (7.37 MHz)
DC50f 24 38 mA 85°C 5V
DC50g 23 38 mA 125°C
DC43a 19 30 mA 25°C
DC43b 20 30 mA 85°C 3.3V
DC43c 20 30 mA 125°C
4 MIPS
DC43e 34 51 mA 25°C
DC43f 33 51 mA 85°C 5V
DC43g 33 51 mA 125°C
DC44a 34 53 mA 25°C
DC44b 35 53 mA 85°C 3.3V
DC44c 35 53 mA 125°C
10 MIPS
DC44e 59 89 mA 25°C
DC44f 59 89 mA 85°C 5V
DC44g 59 89 mA 125°C
DC47a 59 70 mA 25°C
3.3V
DC47b 60 70 mA 85°C
DC47d 99 115 mA 25°C 20 MIPS
DC47e 99 115 mA 85°C 5V
DC47f 100 115 mA 125°C
DC49a 138 155 mA 25°C
5V 30 MIPS
DC49b 139 155 mA 85°C
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail-to-rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.

© 2008 Microchip Technology Inc. DS70150D-page 181

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TABLE 24-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1) Max Units Conditions
No.
Power-Down Current (IPD)(2)
DC60a 0.2 — μA 25°C
DC60b 1.2 40 μA 85°C 3.3V
DC60c 12 65 μA 125°C
Base Power-Down Current(3)
DC60e 0.4 — μA 25°C
DC60f 1.7 55 μA 85°C 5V
DC60g 15 90 μA 125°C
DC61a 9 15 μA 25°C
DC61b 9 15 μA 85°C 3.3V
DC61c 9 15 μA 125°C
Watchdog Timer Current: ΔIWDT(3)
DC61e 18 30 μA 25°C
DC61f 17 30 μA 85°C 5V
DC61g 16 30 μA 125°C
DC62a 4 10 μA 25°C
DC62b 5 10 μA 85°C 3.3V
DC62c 4 10 μA 125°C
Timer1 w/32 kHz Crystal: ΔITI32(3)
DC62e 4 15 μA 25°C
DC62f 6 15 μA 85°C 5V
DC62g 5 15 μA 125°C
DC63a 29 52 μA 25°C 3.3V
DC63b 32 52 μA 85°C
DC63c 33 52 μA 125°C
BOR On: ΔIBOR(3)
DC63e 34 60 μA 25°C
DC63f 39 60 μA 85°C 5V
DC63g 38 60 μA 125°C
Note 1: Data in the “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. BOR, WDT, etc. are all switched off.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

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 dsPIC30F6010A/6015
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
VIL Input Low Voltage(2)
DI10 I/O pins:
with Schmitt Trigger buffer VSS — 0.2 VDD V
DI15 MCLR VSS — 0.2 VDD V
DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2 VDD V
DI17 OSC1 (in RC mode)(3) VSS — 0.3 VDD V
DI18 SDA, SCL VSS — 0.3 VDD V SMBus disabled
DI19 SDA, SCL VSS — 0.2 VDD V SMBus enabled
VIH Input High Voltage(2)
DI20 I/O pins:
with Schmitt Trigger buffer 0.8 VDD — VDD V
DI25 MCLR 0.8 VDD — VDD V
DI26 OSC1 (in XT, HS and LP modes) 0.7 VDD — VDD V
DI27 OSC1 (in RC mode)(3) 0.9 VDD — VDD V
DI28 SDA, SCL 0.7 VDD — VDD V SMBus disabled
DI29 SDA, SCL 0.8 VDD — VDD V SMBus enabled
ICNPU CNXX Pull-up Current(2)
DI30 50 250 400 μA VDD = 5V, VPIN = VSS
IIL Input Leakage Current(2)(4)(5)
DI50 I/O ports — 0.01 ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI51 Analog Input Pins — 0.50 — μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55 MCLR — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD
DI56 OSC1 — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS
and LP Osc mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
5: Negative current is defined as current sourced by the pin.

© 2008 Microchip Technology Inc. DS70150D-page 183

dsPIC30F6010A/6015
TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
VOL Output Low Voltage(2)
DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V
— — 0.15 V IOL = 2.0 mA, VDD = 3V
DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V
(RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V
VOH (2)
Output High Voltage
DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V
VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V
DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V
(RC or EC Osc mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V
Capacitive Loading Specs
on Output Pins(2)
DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes
when external clock is used to
drive OSC1.
DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode
DO58 CB SCL, SDA — — 400 pF In I2C™ mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.

FIGURE 24-1: BROWN-OUT RESET CHARACTERISTICS

VDD

(Device not in Brown-out Reset)

BO15
BO10
(Device in Brown-out Reset)

Reset (due to BOR)

Power-up Time-out

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TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
BO10 VBOR BOR Voltage(2) on BORV = 11(3) — — — V Not in operating
VDD transition range
high-to-low BORV = 10 2.6 — 2.71 V
BORV = 01 4.1 — 4.4 V
BORV = 00 4.58 — 4.73 V
BO15 VBHYS — 5 — mV
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: ‘11’ values not in usable operating range.

TABLE 24-12: DC CHARACTERISTICS: PROGRAM AND EEPROM

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Data EEPROM Memory(2)
D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 2 — ms
D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications
are violated
D124 IDEW IDD During Programming — 10 30 mA Row Erase
Program FLASH Memory(2)
D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VEB VDD for Bulk Erase 4.5 — 5.5 V
D133 VPEW VDD for Erase/Write 3.0 — 5.5 V
D134 TPEW Erase/Write Cycle Time 1 — 2 ms
D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifica-
tions are violated
D136 TEB ICSP™ Block Erase Time — 4 — ms
D137 IPEW IDD During Programming — 10 30 mA Row Erase
D138 IEB IDD During Programming — 10 30 mA Bulk Erase
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
2: These parameters are characterized but not tested in manufacturing.

© 2008 Microchip Technology Inc. DS70150D-page 185

dsPIC30F6010A/6015
24.2 AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 24-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in DC Spec Section 24.1 “DC
Characteristics”.

FIGURE 24-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2

VDD/2

RL Pin CL

VSS
Legend:
CL
Pin RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS 5 pF for OSC2 output

FIGURE 24-3: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO

OS40 OS41

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TABLE 24-14: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param Symb
Characteristic Min Typ(1) Max Units Conditions
No. ol
OS10 FOSC External CLKN Frequency(2) DC — 40 MHz EC
(External clocks allowed only 4 — 10 MHz EC with 4x PLL
in EC mode) 4 — 10 MHz EC with 8x PLL
4 — 7.5(3) MHz EC with 16x PLL
Oscillator Frequency(2) DC — 4 MHz RC
0.4 — 4 MHz XTL
4 — 10 MHz XT
4 — 10 MHz XT with 4x PLL
4 — 10 MHz XT with 8x PLL
4 — 7.5(3) MHz XT with 16x PLL
10 — 25 MHz HS
10 — 20(4) MHz HS/2 with 4x PLL
10 — 20(4) MHz HS/2 with 8x PLL
10 — 15(3) MHz HS/2 with 16x PLL
12(4) — 25 MHz HS/3 with 4x PLL
12(4) — 25 MHz HS/3 with 8x PLL
12(4) — 22.5(3) MHz HS/3 with 16x PLL
— 32.768 — kHz LP
OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10
for FOSC value
OS25 TCY Instruction Cycle Time(2)(5) 33 — DC ns See Table 24-16
(2)
OS30 TosL, External Clock in (OSC1) .45 x TOSC — — ns EC
TosH High or Low Time
OS31 TosR, External Clock(2) in (OSC1) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(2)(6) — — — ns See parameter DO31
OS41 TckF CLKO Fall Time(2)(6) — — — ns See parameter DO32
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: Limited by the PLL output frequency range.
4: Limited by the PLL input frequency range.
5: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
6: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is
low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

© 2008 Microchip Technology Inc. DS70150D-page 187

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TABLE 24-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OS50 FPLLI PLL Input Frequency Range(2) 4 — 10 MHz EC with 4x PLL
4 — 10 MHz EC with 8x PLL
4 — 7.5(4) MHz EC with 16x PLL
4 — 10 MHz XT with 4x PLL
4 — 10 MHz XT with 8x PLL
4 — 7.5(4) MHz XT with 16x PLL
5(3) — 10 MHz HS/2 with 4x PLL
5(3) — 10 MHz HS/2 with 8x PLL
5(3) — 7.5(4) MHz HS/2 with 16x PLL
4 — 8.33(3) MHz HS/3 with 4x PLL
4 — 8.33(3) MHz HS/3 with 8x PLL
4 — 7.5(4) MHz HS/3 with 16x PLL
OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT, HS/2, HS/3 modes
with PLL
OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Limited by oscillator frequency range.
4: Limited by device operating frequency range.

TABLE 24-16: PLL JITTER

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Characteristic Min Typ(1) Max Units Conditions
No.
OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V
— 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V
— 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V
— 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V
— 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V
Note 1: These parameters are characterized but not tested in manufacturing.

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TABLE 24-17: INTERNAL CLOCK TIMING EXAMPLES
Clock
FOSC MIPS(3) MIPS(3) MIPS(3) MIPS(3)
Oscillator TCY (μsec)(2)
(MHz)(1) w/o PLL w/PLL x4 w/PLL x8 w/PLL x16
Mode
EC 0.200 20.0 0.05 — — —
4 1.0 1.0 4.0 8.0 16.0
10 0.4 2.5 10.0 20.0 —
25 0.16 6.25 — — —
XT 4 1.0 1.0 4.0 8.0 16.0
10 0.4 2.5 10.0 20.0 —
Note 1: Assumption: Oscillator Postscaler is divide by 1.
2: Instruction Execution Cycle Time: TCY = 1/MIPS.
3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction
cycle].

© 2008 Microchip Technology Inc. DS70150D-page 189

dsPIC30F6010A/6015
TABLE 24-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
Characteristic Min Typ Max Units Conditions
No.
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
OS63 FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V
— — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.

TABLE 24-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Characteristic Min Typ Max Units Conditions
No.
LPRC @ Freq. = 512 kHz(1)
OS65A -50 — +50 % VDD = 5.0V, ±10%
OS65B -60 — +60 % VDD = 3.3V, ±10%
OS65C -70 — +70 % VDD = 2.5V
Note 1: Change of LPRC frequency as VDD changes.

DS70150D-page 190 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-4: CLKOUT AND I/O TIMING CHARACTERISTICS

I/O Pin
(Input)

DI35
DI40

I/O Pin Old Value New Value

(Output)
DO31
DO32

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-20: CLKOUT AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions
No.
DO31 TIOR Port output rise time — 7 20 ns
DO32 TIOF Port output fall time — 7 20 ns
DI35 TINP INTx pin high or low time (output) 20 — — ns
DI40 TRBP CNx high or low time (input) 2 TCY — — —
Note 1: These parameters are asynchronous events not related to any internal clock edges.
2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.
3: These parameters are characterized but not tested in manufacturing.
4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

© 2008 Microchip Technology Inc. DS70150D-page 191

dsPIC30F6010A/6015
FIGURE 24-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS

VDD SY12

MCLR

Internal SY10
POR

SY11
PWRT
Time-out
SY30
OSC
Time-out

Internal
Reset

Watchdog
Timer
Reset
SY20
SY13
SY13

I/O Pins

SY35
FSCM
Delay

Note: Refer to Figure 24-2 for load conditions.

DS70150D-page 192 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C
SY11 TPWRT Power-up Timer Period 2 4 8 ms -40°C to +85°C, VDD =
10 16 32 5V
43 64 128 User programmable
SY12 TPOR Power-on Reset Delay(4) 3 10 30 μs -40°C to +85°C
SY13 TIOZ I/O High-impedance from MCLR — 0.8 1.0 μs
Low or Watchdog Timer Reset
SY20 TWDT1 Watchdog Timer Time-out Period 1.1 2.0 6.6 ms VDD = 2.5V
TWDT2 (No Prescaler) 1.2 2.0 5.0 ms VDD = 3.3V, ±10%
TWDT3 1.3 2.0 4.0 ms VDD = 5V, ±10%
SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μs VDD ≤ VBOR (D034)
SY30 TOST Oscillator Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
3: Refer to Figure 24-1 and Table for BOR
4: Characterized by design but not tested.

FIGURE 24-6: BAND GAP START-UP TIME CHARACTERISTICS

VBGAP
0V

Enable Band Gap

(see Note)
Band Gap
SY40 Stable

Note: Set FBORPOR<7>.

TABLE 24-22: BAND GAP START-UP TIME REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
SY40 TBGAP Band Gap Start-up Time — 40 65 μs Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable
(RCON<13>Status bit).
Note 1: These parameters are characterized but not tested in manufacturing.

© 2008 Microchip Technology Inc. DS70150D-page 193

dsPIC30F6010A/6015
FIGURE 24-7: TIMER1, 2, 3, 4 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK
Tx10 Tx11

Tx15 Tx20
OS60
TMRX

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TA15
Synchronous, 10 — — ns
with prescaler
Asynchronous 10 — — ns
TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TA15
Synchronous, 10 — — ns
with prescaler
Asynchronous 10 — — ns
TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns
no prescaler
Synchronous, Greater of: — — — N = prescale
with prescaler 20 ns or value
(TCY + 40)/N (1, 8, 64, 256)
Asynchronous 20 — — ns
OS60 Ft1 SOSC1/T1CK oscillator input DC — 50 kHz
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY —
Edge to Timer Increment
Note: Timer1 is a Type A.

DS70150D-page 194 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 24-24: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TB15
Synchronous, 10 — — ns
with prescaler
TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet
no prescaler parameter TB15
Synchronous, 10 — — ns
with prescaler
TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY —
Edge to Timer Increment

TABLE 24-25: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 —
Edge to Timer Increment TCY

© 2008 Microchip Technology Inc. DS70150D-page 195

dsPIC30F6010A/6015
FIGURE 24-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS

QEB

TQ10 TQ11

TQ15 TQ20

POSCNT

TABLE 24-26: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
TQ10 TtQH TQCK High Time Synchronous, TCY + 20 — — ns Must also meet
with prescaler parameter TQ15
TQ11 TtQL TQCK Low Time Synchronous, TCY + 20 — — ns Must also meet
with prescaler parameter TQ15
TQ15 TtQP TQCP Input Synchronous, 2 * TCY + 40 — — ns
Period with prescaler
TQ20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY —
Edge to Timer Increment
Note 1: These parameters are characterized but not tested in manufacturing.

DS70150D-page 196 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICX

IC10 IC11
IC15

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-27: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Max Units Conditions
No.
IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 24-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx
(Output Compare
or PWM Mode) OC11 OC10

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-28: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OC10 TccF OCx Output Fall Time — — — ns See parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

© 2008 Microchip Technology Inc. DS70150D-page 197

dsPIC30F6010A/6015
FIGURE 24-11: OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OCFA/OCFB

OC15

OCx

TABLE 24-29: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
OC15 TFD Fault Input to PWM I/O — — 50 ns
Change
OC20 TFLT Fault Input Pulse Width 50 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

DS70150D-page 198 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

MP30

FLTA/B

MP20

PWMx

FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

MP11 MP10

PWMx

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-30: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
MP10 TFPWM PWM Output Fall Time — — — ns See parameter DO32
MP11 TRPWM PWM Output Rise Time — — — ns See parameter DO31
TFD Fault Input ↓ to PWM — — 50 ns
MP20
I/O Change
MP30 TFH Minimum Pulse Width 50 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

© 2008 Microchip Technology Inc. DS70150D-page 199

dsPIC30F6010A/6015
FIGURE 24-14: QEA/QEB INPUT CHARACTERISTICS

TQ36

QEA
(input)
TQ31 TQ30

TQ35

QEB
(input) TQ41 TQ40

TQ31 TQ30

TQ35

QEB
Internal

TABLE 24-31: QUADRATURE DECODER TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Typ(2) Max Units Conditions
No.
TQ30 TQUL Quadrature Input Low Time 6 TCY — ns
TQ31 TQUH Quadrature Input High Time 6 TCY — ns
TQ35 TQUIN Quadrature Input Period 12 TCY — ns
TQ36 TQUP Quadrature Phase Period 3 TCY — ns
TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
with Digital Filter 128 and 256 (Note 2)
TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
with Digital Filter 128 and 256 (Note 2)
Note 1: These parameters are characterized but not tested in manufacturing.
2: N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder
Interface (QEI)” in the “dsPIC30F Family Reference Manual” (DS70046).

DS70150D-page 200 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS

QEA
(input)

QEB
(input)

Ungated
Index TQ50
TQ51

Index Internal

TQ55

Position Coun-

TABLE 24-32: QEI INDEX PULSE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Max Units Conditions
No.
TQ50 TqIL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
with Digital Filter 128 and 256 (Note 2)
TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
with Digital Filter 128 and 256 (Note 2)
TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns
Counter Reset (Ungated Index)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Alignment of index pulses to QEA and QEB is shown for position counter reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on falling edge.

© 2008 Microchip Technology Inc. DS70150D-page 201

dsPIC30F6010A/6015
FIGURE 24-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx
(CKP = 0)

SP11 SP10 SP21 SP20

SCKx
(CKP = 1)

SP35 SP20 SP21

SDOx MSb BIT14 - - - - - -1 LSb

SP31 SP30

SDIx MSb IN BIT14 - - - -1 LSb IN

SP40 SP41

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-33: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns
SP11 TscH SCKX Output High Time(3) TCY/2 — — ns
SP20 TscF SCKX Output Fall Time(4) — — — ns See parameter DO32
SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31
SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter DO32
SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns
TscL2diL to SCKX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

DS70150D-page 202 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS

SP36
SCKX
(CKP = 0)

SP11 SP10 SP21 SP20

SCKX
(CKP = 1)
SP35
SP20 SP21

SDOX MSb BIT14 - - - - - -1 LSb

SP40 SP30,SP31

SDIX MSb IN BIT14 - - - -1 LSb IN

SP41

Note: Refer to Figure 24-2 for load conditions.

TABLE 24-34: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP10 TscL SCKX output low time(3) TCY/2 — — ns
SP11 TscH SCKX output high time(3) TCY/2 — — ns
SP20 TscF SCKX output fall time(4) — — — ns See parameter DO32
SP21 TscR SCKX output rise time(4) — — — ns See parameter DO31
SP30 TdoF SDOX data output fall time(4) — — — ns See parameter DO32
SP31 TdoR SDOX data output rise time (4)
— — — ns See parameter DO31
SP35 TscH2doV, SDOX data output valid after — — — ns
TscL2doV SCKX edge
SP36 TdoV2sc, SDOX data output setup to 30 — — ns
TdoV2scL first SCKX edge
SP40 TdiV2scH, Setup time of SDIX data input 20 — — ns
TdiV2scL to SCKX edge
SP41 TscH2diL, Hold time of SDIX data input 20 — — ns
TscL2diL to SCKX edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

© 2008 Microchip Technology Inc. DS70150D-page 203

dsPIC30F6010A/6015
FIGURE 24-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP50 SP52
SCKX
(CKP = 0)

SP71 SP70 SP73 SP72

SCKX
(CKP = 1)

SP72 SP73
SP35

SDOX MSb BIT14 - - - - - -1 LSb

SP30,SP31 SP51

SDIX MSb IN BIT14 - - - -1 LSb IN

SP41
SP40 Note: Refer to Figure 24-2 for load conditions.

TABLE 24-35: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP70 TscL SCKX Input Low Time 30 — — ns
SP71 TscH SCKX Input High Time 30 — — ns
SP72 TscF SCKX Input Fall Time(3) — 10 25 ns
SP73 TscR SCKX Input Rise Time(3) — 10 25 ns
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32
(3)
SP31 TdoR SDOX Data Output Rise Time — — — ns See parameter DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns
TscL2diL to SCKX Edge
SP50 TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns
TssL2scL
SP51 TssH2doZ SSX↑ to SDOX Output 10 — 50 ns
High-impedance(3)
SP52 TscH2ssH SSX after SCK Edge 1.5 TCY +40 — — ns
TscL2ssH
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Assumes 50 pF load on all SPI pins.

DS70150D-page 204 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSX

SP50 SP52
SCKX
(CKP = 0)

SP71 SP70 SP73 SP72

SCKX
(CKP = 1)
SP35
SP72 SP73
SP52

SDOX MSb BIT14 - - - - - -1 LSb

SP30,SP31 SP51

SDIX
MSb IN BIT14 - - - -1 LSb IN
SP41
SP40 Note: Refer to Figure 24-2 for load conditions.

TABLE 24-36: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP70 TscL SCKX Input Low Time 30 — — ns
SP71 TscH SCKX Input High Time 30 — — ns
SP72 TscF SCKX Input Fall Time(3) — 10 25 ns
SP73 TscR SCKX Input Rise Time (3)
— 10 25 ns
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32
SP31 TdoR SDOX Data Output Rise Time (3)
— — — ns See parameter DO31
SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns
TscL2doV SCKX Edge
SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns
TdiV2scL to SCKX Edge
SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns
TscL2diL to SCKX Edge
SP50 TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns
TssL2scL
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

© 2008 Microchip Technology Inc. DS70150D-page 205

dsPIC30F6010A/6015
TABLE 24-36: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SP51 TssH2doZ SS↑ to SDOX Output 10 — 50 ns
High-impedance(4)
SP52 TscH2ssH SSX↑ after SCKX Edge 1.5 TCY + — — ns
TscL2ssH 40
SP60 TssL2doV SDOX Data Output Valid after — — 50 ns
SSX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.

DS70150D-page 206 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCL
IM31 IM34
IM30 IM33

SDA

Start Stop
Condition Condition

Note: Refer to Figure 24-2 for load conditions.

FIGURE 24-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20 IM11 IM21

IM10
SCL
IM11 IM26
IM10 IM25 IM33
SDA
In
IM40 IM40 IM45

SDA
Out

Note: Refer to Figure 24-2 for load conditions.

© 2008 Microchip Technology Inc. DS70150D-page 207

dsPIC30F6010A/6015
TABLE 24-37: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min(1) Max Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs
400 kHz mode TCY/2 (BRG + 1) — μs
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs
400 kHz mode TCY/2 (BRG + 1) — μs
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 100 ns
IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 300 ns
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(2) — — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode(2) — — ns
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for
Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start
condition
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the
Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is
generated
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs
Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs
1 MHz mode(2) TCY/2 (BRG + 1) — μs
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2) TCY/2 (BRG + 1) — ns
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
From Clock 400 kHz mode — 1000 ns
1 MHz mode(2) — — ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be
400 kHz mode 1.3 — μs free before a new
transmission can start
1 MHz mode(2) — — μs
IM50 CB Bus Capacitive Loading — 400 pF
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I2C™)”
in the “dsPIC30F Family Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).

DS70150D-page 208 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCL
IS31 IS34
IS30 IS33

SDA

Start Stop
Condition Condition

FIGURE 24-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20 IS11 IS21

IS10
SCL
IS30 IS26
IS31 IS25 IS33
SDA
In
IS40 IS40 IS45

SDA
Out

© 2008 Microchip Technology Inc. DS70150D-page 209

dsPIC30F6010A/6015
TABLE 24-38: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Max Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — μs Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — µs
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — µs Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — µs
IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
(1)
1 MHz mode 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode(1) 0 0.3 μs
IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated
Setup Time 400 kHz mode 0.6 — μs Start condition
1 MHz mode(1) 0.25 — μs
IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first
Hold Time 400 kHz mode 0.6 — μs clock pulse is generated
1 MHz mode(1) 0.25 — μs
IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs
Setup Time 400 kHz mode 0.6 — μs
(1)
1 MHz mode 0.6 — μs
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 — ns
1 MHz mode(1) 250 ns
IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns
Clock 400 kHz mode 0 1000 ns
1 MHz mode(1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free
400 kHz mode 1.3 — μs before a new transmission
1 MHz mode(1) 0.5 — μs can start
IS50 CB Bus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).

DS70150D-page 210 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-24: CAN MODULE I/O TIMING CHARACTERISTICS

CXTX Pin Old Value New Value

(output)

CA10 CA11
CXRX Pin
(input)
CA20

TABLE 24-39: CAN MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
CA10 TioF Port Output Fall Time — — — ns See parameter DO32
CA11 TioR Port Output Rise Time — — — ns See parameter DO31
CA20 Tcwf Pulse Width to Trigger 500 — — ns
CAN Wake-up Filter
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.

© 2008 Microchip Technology Inc. DS70150D-page 211

dsPIC30F6010A/6015
TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1)
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD – 0.3 VDD + 0.3
or 2.7 or 5.5
AD02 AVSS Module VSS Supply Vss - 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVss + 2.7 — AVDD V
AD06 VREFL Reference Voltage Low AVss — AVDD – 2.7 V
AD07 VREF Absolute Reference Voltage AVss – 0.3 — AVDD + 0.3 V
AD08 IREF Current Drain — 200 300 μA A/D operating
.001 3 μA A/D off
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL VREFH V
AD12 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
Source Impedance = 5 kΩ
AD13 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Source Impedance = 5 kΩ
AD17 RIN Recommended Impedance — — — Ω See Table 20-2
of Analog Voltage Source
DC Accuracy
AD20 Nr Resolution 10 data bits bits —
AD21 INL Integral Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD21A INL Integral Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22 DNL Differential Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD22A DNL Differential Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23 GERR Gain Error(2) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD23A GERR Gain Error(2) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Note 1: These parameters are characterized but not tested in manufacturing.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.

DS70150D-page 212 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1) (CONTINUED)
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
AD24 EOFF Offset Error(2) ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD24A EOFF Offset Error(2) ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25 — Monotonicity(3) — — — — Guaranteed
Dynamic Performance
AD30 THD Total Harmonic Distortion — -64 -67 dB
AD31 SINAD Signal to Noise and — 57 58 dB
Distortion
AD32 SFDR Spurious Free Dynamic — 67 71 dB
Range
AD33 FNYQ Input Signal Bandwidth — — 500 kHz
AD34 ENOB Effective Number of Bits 9.29 9.41 — bits
Note 1: These parameters are characterized but not tested in manufacturing.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.

© 2008 Microchip Technology Inc. DS70150D-page 213

dsPIC30F6010A/6015
FIGURE 24-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)

AD50

ADCLK
Instruction
Execution SET SAMP CLEAR SAMP

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

AD61
AD60

TSAMP AD55 AD55

DONE

ADIF

ADRES(0)

ADRES(1)

1 2 3 4 5 6 8 9 5 6 8 9

1 - Software sets ADCON. SAMP to start sampling.

2 - Sampling starts after discharge period.
TSAMP is described in Section 17. “10-bit A/D Converter” of the “dsPIC30F Family Reference Manual” (DS70046).
3 - Software clears ADCON. SAMP to start conversion.
4 - Sampling ends, conversion sequence starts.
5 - Convert bit 9.
6 - Convert bit 8.
8 - Convert bit 0.
9 - One TAD for end of conversion.

DS70150D-page 214 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
FIGURE 24-26: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)

AD50

ADCLK
Instruction
Execution SET ADON

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

TSAMP TSAMP
AD55 AD55 TCONV

DONE

ADIF

ADRES(0)

ADRES(1)

1 2 3 4 5 6 7 3 4 5 6 8 3 4

1 - Software sets ADCON. ADON to start AD operation. 5 - Convert bit 0.

2 - Sampling starts after discharge period. 6 - One TAD for end of conversion.
TSAMP is described in Section 17. “10-bit A/D Converter”
of the “dsPIC30F Family Reference Manual” (DS70046). 7 - Begin conversion of next channel.

3 - Convert bit 9. 8 - Sample for time specified by SAMC.

TSAMP is described in Section 17. “10-bit A/D Converter”
4 - Convert bit 8. of the “dsPIC30F Family Reference Manual” (DS70046).

© 2008 Microchip Technology Inc. DS70150D-page 215

dsPIC30F6010A/6015
TABLE 24-41: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min. Typ(1) Max. Units Conditions
No.
Clock Parameters
AD50 TAD A/D Clock Period 84 — — ns See Table 20-2(2)
AD51 tRC A/D Internal RC Oscillator Period 700 900 1100 ns
Conversion Rate
AD55 tCONV Conversion Time — 12 TAD — —
AD56 FCNV Throughput Rate — 1.0 — Msps See Table 20-2(2)
AD57 TSAMP Sample Time 1 TAD — — — See Table 20-2(2)
Timing Parameters
AD60 tPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger
Trigger(3) (SSRC = 111) not
selected
AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 TAD —
Sample (SAMP) Bit
AD62 tCSS Conversion Completion to — 0.5 TAD — —
Sample Start (ASAM = 1)(3)
AD63 tDPU(4) Time to Stabilize Analog Stage — — 20 μs
from A/D Off to A/D On(3)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.
4: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). Dur-
ing this time the ADC result is indeterminate.

DS70150D-page 216 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
25.0 PACKAGING INFORMATION
25.1 Package Marking Information

64-Lead TQFP Example

XXXXXXXXXXXX dsPIC30F6015
XXXXXXXXXXXX -30I/PT e3
YYWWNNN 0712XXX

80-Lead TQFP Example

XXXXXXXXXXXX dsPIC30F6010
XXXXXXXXXXXX A-30I/PT e3
YYWWNNN 0712XXX

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2008 Microchip Technology Inc. DS70150D-page 217

dsPIC30F6010A/6015
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
D1

E
e
E1

N
b

NOTE 1 123 NOTE 2

α
A
c φ
A2

β A1
L L1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top α 11° 12° 13°
Mold Draft Angle Bottom β 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B

DS70150D-page 218 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015

80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
D1

E
e
E1

b N

NOTE 1
12 3 NOTE 2 α
A
c

φ
β A2
A1
L L1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 80
Lead Pitch e 0.50 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° 3.5° 7°
Overall Width E 14.00 BSC
Overall Length D 14.00 BSC
Molded Package Width E1 12.00 BSC
Molded Package Length D1 12.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top α 11° 12° 13°
Mold Draft Angle Bottom β 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-092B

© 2008 Microchip Technology Inc. DS70150D-page 219

dsPIC30F6010A/6015

80-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
D1

e E

E1

N
NOTE 1
1 23 α
NOTE 2
c
φ
A

β L A1 L1 A2

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 80
Lead Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° 3.5° 7°
Overall Width E 16.00 BSC
Overall Length D 16.00 BSC
Molded Package Width E1 14.00 BSC
Molded Package Length D1 14.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.22 0.32 0.38
Mold Draft Angle Top α 11° 12° 13°
Mold Draft Angle Bottom β 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-116B

DS70150D-page 220 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
APPENDIX A: REVISION HISTORY Revision D (June 2008)
This revision reflects these updates:
Revision A (July 2005)
• Changed the location of the input reference in the
Original data sheet for dsPIC30F6010A/6015 devices. 10-bit High-Speed ADC Functional Block Diagram
(see Figure 20-1)
Revision B (September 2006) • Added FUSE Configuration Register (FICD)
details (see Section 21.6 “Device Configuration
This revision reflects updates in these areas: Registers” and Table 21-9)
• Data Ram protection feature enables segments of • Removed erroneous statement regarding genera-
RAM to be protected when used in conjunction tion of CAN receive errors (see Section 19.4.5
with Boot and Secure Code Segment Security “Receive Errors”)
(see Section 3.2.7 “Data Ram Protection Fea- • Electrical Specifications:
ture”)
- Resolved TBD values for parameters DO10,
• BSRAM and SSRAM SFRs added to support DO16, DO20, and DO26 (see Table 24-10)
Data Ram Protection (see Table 3-3)
- 10-bit High-Speed ADC tPDU timing parame-
• Base Instruction CP1 removed (see Table 22-2) ter (time to stabilize) has been updated from
• Supported I2C Slave addresses (see Table 17-2) 20 µs typical to 20 µs maximum (see
• Revised Electrical Characteristics: Table 24-41)
- Operating current (IDD) specifications (see - Parameter OS65 (Internal RC Accuracy) has
Table 24-6) been expanded to reflect multiple Min and
- Idle current (IIDLE) specifications (see Max values for different temperatures (see
Table 24-7) Table 24-19)
- Power-down current (IPD) specifications (see - Parameter DC12 (RAM Data Retention Volt-
Table 24-8) age) Min and Max values have been updated
- I/O Pin input specifications (see Table 24-9) (see Table 24-5)
- BOR voltage limits (see Table 24-11) - Parameter D134 (Erase/Write Cycle Time)
has been updated to include Min and Max
- Watchdog Timer time-out limits (see
values and the Typ value has been removed
Table 24-21)
(see Table 24-12)
• Added note to package drawings.
- Removed parameters OS62 (Internal FRC
Jitter) and OS64 (Internal FRC Drift) and
Revision C (January 2007) Note 2 from AC Characteristics (see
This revision includes updates to the packaging Table 24-18)
diagrams. - Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 24-18)
- Updated Min and Max values and Conditions
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for parame-
ter SY20 (see Table 24-21)
• Additional minor corrections throughout the
document

© 2008 Microchip Technology Inc. DS70150D-page 221

dsPIC30F6010A/6015
NOTES:

DS70150D-page 222 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
INDEX
A Oscillator System ..................................................... 151
A/D Output Compare Mode .............................................. 85
PWM Module ............................................................. 96
Aborting a Conversion ............................................. 140
Quadrature Encoder Interface ................................... 89
Acquisition Requirements ........................................ 144
ADCHS .................................................................... 137 Reset System .......................................................... 155
Shared Port Structure ................................................ 60
ADCON1 .................................................................. 137
SPI ........................................................................... 106
ADCON2 .................................................................. 137
ADCON3 .................................................................. 137 SPI Master/Slave Connection .................................. 106
UART Receiver ........................................................ 118
ADCSSL ................................................................... 137
UART Transmitter .................................................... 117
ADPCFG .................................................................. 137
Configuring Analog Port Pins ................................... 146 10-bit High-Speed A/D Functional ........................... 138
16-bit Timer1 Module (Type A Timer) ........................ 66
Connection Considerations ...................................... 146
16-bit Timer2 (Type B Timer) for dsPIC30F6010A .... 72
Conversion Operation .............................................. 139
Conversion Rate Parameters ................................... 141 16-bit Timer2 (Type B Timer) for dsPIC30F6015 ...... 72
16-bit Timer3 (Type C Timer) .................................... 73
Conversion Speeds .................................................. 141
16-bit Timer4 (Type B Timer) .................................... 78
Effects of a Reset ..................................................... 145
Operation During CPU Idle Mode ............................ 145 16-bit Timer5 (Type C Timer) .................................... 78
32-bit Timer2/3 for dsPIC30F6010A .......................... 70
Operation During CPU Sleep Mode ......................... 145
32-bit Timer2/3 for dsPIC30F6015 ............................ 71
Output Formats ........................................................ 145
Power-Down Modes ................................................. 145 32-bit Timer4/5 .......................................................... 77
BOR. See Brown-out Reset.
Programming the Start of Conversion Trigger ......... 140
Brown-out Reset (BOR) ................................................... 149
Register Map ............................................................ 147
Result Buffer ............................................................ 139 C
Selecting the Conversion Clock ............................... 140
C Compilers
Selecting the Conversion Sequence ........................ 139
MPLAB C18 ............................................................. 174
Voltage Reference Schematic ................................. 142
MPLAB C30 ............................................................. 174
1 Msps Configuration Guideline ............................... 142
CAN
10-bit High-Speed Analog-to-Digital
Baud Rate Setting ................................................... 130
Converter Module .................................................... 137
Bit Timing ......................................................... 130
600 ksps Configuration Guideline ............................ 143
Phase Segments ............................................. 131
750 ksps Configuration Guideline ............................ 143
Prescaler ......................................................... 131
AC Characteristics ........................................................... 186
Propagation Segment ...................................... 131
Internal FRC Jitter, Accuracy and Drift .................... 190
Sample Point ................................................... 131
Internal LPRC Accuracy ........................................... 190
Synchronization ............................................... 131
Load Conditions ....................................................... 186
CAN1 Register Map for dsPIC30F6010A/6015 ....... 132
Temperature and Voltage Specifications ................. 186
CAN2 Register Map for dsPIC30F6010A ................ 134
Address Generator Units ................................................... 35
Frame Types ........................................................... 125
Alternate Vector Table ....................................................... 45
Message Reception ................................................. 128
Alternate 16-bit Timer/Counter ........................................... 91
Acceptance Filter Masks ................................. 128
Assembler
Acceptance Filters ........................................... 128
MPASM Assembler .................................................. 174
Receive Buffers ............................................... 128
Automatic Clock Stretch ................................................... 112
Receive Errors ................................................. 128
During 10-bit Addressing (STREN = 1) .................... 112
Receive Interrupts ........................................... 128
During 7-bit Addressing (STREN = 1) ...................... 112
Receive Overrun .............................................. 128
Receive Mode .......................................................... 112
Message Transmission ............................................ 129
Transmit Mode ......................................................... 112
Aborting ........................................................... 129
B Errors ............................................................... 129
Barrel Shifter ...................................................................... 22 Priority ............................................................. 129
Sequence ........................................................ 129
Bit-Reversed Addressing ................................................... 38
Transmit Buffers .............................................. 129
Example ..................................................................... 38
Implementation .......................................................... 38 Transmit Interrupts .......................................... 130
Operation Modes ..................................................... 127
Modifier Values (table) ............................................... 39
Disable ............................................................ 127
Sequence Table (16-Entry) ........................................ 39
Block Diagrams Error Recognition ............................................. 127
Initialization ...................................................... 127
CAN Buffers and Protocol Engine ............................ 126
Listen-Only ...................................................... 127
Dedicated Port Structure ............................................ 59
DSP Engine ............................................................... 19 Loopback ......................................................... 127
Normal ............................................................. 127
dsPIC30F6010A ......................................................... 10
Overview .................................................................. 125
dsPIC30F6015 ........................................................... 11
External Power-on Reset Circuit .............................. 158 CAN Module .................................................................... 125
Center-Aligned PWM ......................................................... 99
Input Capture Mode ................................................... 81
Code Examples
I2C ............................................................................ 110
Data EEPROM Block Erase ...................................... 56

© 2008 Microchip Technology Inc. DS70150D-page 223

dsPIC30F6010A/6015
Data EEPROM Block Write ........................................ 58 FBORPOR ............................................................... 161
Data EEPROM Read ................................................. 55 FGS ......................................................................... 161
Data EEPROM Word Erase ....................................... 56 FOSC ....................................................................... 161
Data EEPROM Word Write ........................................ 57 FWDT ...................................................................... 161
Erasing a Row of Program Memory ........................... 51 Device Overview .................................................................. 9
Initiating a Programming Sequence ........................... 52 Divide Support ................................................................... 18
Loading Write Latches ............................................... 52 DSP Engine ....................................................................... 18
Port Write/Read Example .......................................... 60 Multiplier .................................................................... 20
Code Protection ............................................................... 149 dsPIC30F6010A Port Register Map .................................. 61
Complementary PWM Operation ..................................... 100 dsPIC30F6015 Port Register Map ..................................... 62
Configuring Analog Port Pins ............................................. 60 Dual Output Compare Match Mode ................................... 86
Core Overview ................................................................... 15 Continuous Pulse Mode ............................................. 86
CPU Architecture Overview ............................................... 15 Single Pulse Mode ..................................................... 86
Customer Change Notification Service ............................ 228
Customer Notification Service .......................................... 228 E
Customer Support ............................................................ 228 Edge-Aligned PWM ........................................................... 98
Electrical Characteristics ................................................. 177
D Absolute Maximum Ratings ..................................... 177
Data Access from Program Memory Using BOR ......................................................................... 185
Program Space Visibility .................................................... 26 Equations
Data Accumulators and Adder/Subtracter .......................... 20 A/D Conversion Clock .............................................. 140
Data Space Write Saturation ..................................... 22 Baud Rate ................................................................ 121
Write Back .................................................................. 21 PWM Period ............................................................... 98
Data Accumulators and Adder/Subtractor PWM Resolution ........................................................ 98
Overflow and Saturation ............................................ 20 Serial Clock Rate ..................................................... 114
Round Logic ............................................................... 21 Time Quantum for Clock Generation ....................... 131
Data Address Space .......................................................... 27 Errata ................................................................................... 7
Alignment ................................................................... 30 External Interrupt Requests ............................................... 45
Alignment (Figure) ..................................................... 30
Effect of Invalid Memory Accesses ............................ 30 F
MCU and DSP (MAC Class) Instructions Example .... 29 Fast Context Saving .......................................................... 45
Memory Map ........................................................ 27, 28 Flash Program Memory ..................................................... 49
Near Data Space ....................................................... 31 In-Circuit Serial Programming (ICSP) ........................ 49
Software Stack ........................................................... 31 Run-Time Self-Programming (RTSP) ........................ 49
Spaces ....................................................................... 30 Table Instruction Operation Summary ....................... 49
Width .......................................................................... 30
Data EEPROM Memory ..................................................... 55
I
Erasing ....................................................................... 56 I/O Ports ............................................................................. 59
Erasing, Block ............................................................ 56 Parallel I/O (PIO) ....................................................... 59
Erasing, Word ............................................................ 56 Idle Current (IIDLE) ........................................................... 181
Protection Against Spurious Write ............................. 58 In-Circuit Debugger (ICD 2) ............................................. 162
Reading ...................................................................... 55 In-Circuit Serial Programming (ICSP) .............................. 149
Write Verify ................................................................ 58 Independent PWM Output ............................................... 101
Writing ........................................................................ 57 Initialization Condition for RCON Register Case 1 .......... 159
Writing, Block ............................................................. 58 Initialization Condition for RCON Register Case 2 .......... 159
Writing, Word ............................................................. 57 Input Capture Module ........................................................ 81
DC Characteristics ........................................................... 178 Interrupts ................................................................... 82
Brown-out Reset ...................................................... 184 Operation During Sleep and Idle Modes .................... 82
I/O Pin Output Specifications ................................... 184 Register Map ............................................................. 83
Idle Current (IIDLE) ................................................... 181 Simple Capture Event Mode ...................................... 81
Operating Current (IDD) ............................................ 180 Input Change Notification Module ...................................... 63
Operating MIPS vs. Voltage for dsPIC30F6010A .... 178 Register Map (bits 15-8) ............................................ 63
Operating MIPS vs. Voltage for dsPIC30F6015 ...... 178 Register Map (bits 7-0 for dsPIC30F6010A) .............. 63
Power-Down Current (IPD) ....................................... 182 Register Map (bits 7-0 for dsPIC30F6015) ................ 63
Program and EEPROM ............................................ 185 Instruction Addressing Modes ........................................... 35
Thermal Operating Conditions for File Register Instructions ........................................... 35
dsPIC30F6010A/6015 .............................................. 178 Fundamental Modes Supported ................................ 35
Thermal Packaging Characteristics ......................... 178 MAC Instructions ....................................................... 36
Dead-Time Generators .................................................... 100 MCU Instructions ....................................................... 35
Assignment .............................................................. 100 Move and Accumulator Instructions ........................... 36
Ranges ..................................................................... 100 Other Instructions ...................................................... 36
Selection Bits ........................................................... 100 Instruction Set
Development Support ...................................................... 173 Overview .................................................................. 168
Device Configuration Summary ................................................................. 165
Register Map ............................................................ 163 Internet Address .............................................................. 228
Device Configuration Registers ........................................ 161 Interrupt Controller

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 dsPIC30F6010A/6015
Register Map (dsPIC30F6010A) ................................ 46 Initial Clock Source Selection .................................. 152
Register Map (dsPIC30F6015) .................................. 47 Low-Power RC (LPRC) ........................................... 154
Interrupt Priority ................................................................. 42 LP Oscillator Control ................................................ 153
Interrupt Sequence ............................................................ 45 Phase Locked Loop (PLL) ....................................... 153
Interrupt Stack Frame ................................................ 45 Start-up Timer (OST) ............................................... 153
Interrupts ............................................................................ 41 Oscillator Selection .......................................................... 149
I2C Master Operation Output Compare Module ................................................... 85
Baud Rate Generator ............................................... 113 Interrupts ................................................................... 87
Clock Arbitration ....................................................... 114 Operation During CPU Idle Mode .............................. 87
Multi-Master Communication, Bus Collision Operation During CPU Sleep Mode .......................... 87
and Bus Arbitration .................................................. 114 Register Map ............................................................. 88
Reception ................................................................. 113
Transmission ............................................................ 113 P
I2C Module Packaging Information ..................................................... 217
Addresses ................................................................ 111 Marking .................................................................... 217
General Call Address Support ................................. 113 Peripheral Module Disable (PMD) Registers ................... 162
Interrupts .................................................................. 113 PICSTART Plus Development Programmer .................... 176
IPMI Support ............................................................ 113 Pin Diagrams ................................................................... 5–6
Master Operation ..................................................... 113 Pinout Descriptions ............................................................ 12
Master Support ........................................................ 113 POR. See Power-on Reset.
Operating Function Description ............................... 109 Position Measurement Mode ............................................. 90
Operation During CPU Sleep and Idle Modes ......... 114 Power Saving Modes
Pin Configuration ..................................................... 109 Idle ........................................................................... 161
Programmer’s Model ................................................ 109 Sleep ....................................................................... 160
Register Map ............................................................ 115 Power-on Reset (POR) .................................................... 149
Registers .................................................................. 109 Oscillator Start-up Timer (OST) ............................... 149
Slope Control ........................................................... 113 Power-up Timer (PWRT) ......................................... 149
Software Controlled Clock Stretching (STREN = 1) . 112 Power-Saving Modes ....................................................... 160
Various Modes ......................................................... 109 Power-Saving Modes (Sleep and Idle) ............................ 149
I2C 10-bit Slave Mode Operation ..................................... 111 Program Address Space .................................................... 23
10-bit Mode Slave Reception ................................... 112 Construction .............................................................. 24
10-bit Mode Slave Transmission .............................. 112 Data Access from Program Memory Using Table Instruc-
I2C 7-bit Slave Mode Operation ....................................... 111 tions ................................................................... 25
Reception ................................................................. 111 Data Access from, Address Generation .................... 24
Transmission ............................................................ 111 Memory Map .............................................................. 23
I2C™ Module ................................................................... 109 Table Instructions
TBLRDH ............................................................ 25
M TBLRDL ............................................................. 25
Memory Organization ......................................................... 23 TBLWTH ............................................................ 25
Core Register Map ..................................................... 32 TBLWTL ............................................................ 25
Microchip Internet Web Site ............................................. 228 Program Counter ............................................................... 16
Modulo Addressing ............................................................ 36 Program Data Table Access .............................................. 26
Applicability ................................................................ 38 Program Space Visibility
Operation Example .................................................... 37 Window into Program Space Operation .................... 27
Start and End Address ............................................... 37 Programmable ................................................................. 149
W Address Register Selection ................................... 37 Programmable Digital Noise Filters ................................... 91
Motor Control PWM Module ............................................... 95 Programmer’s Model ......................................................... 16
8-Output Register Map ............................................. 104 Diagram ..................................................................... 17
MPLAB ASM30 Assembler, Linker, Librarian .................. 174 Programming Operations ................................................... 51
MPLAB ICD 2 In-Circuit Debugger .................................. 175 Algorithm for Program Flash ...................................... 51
MPLAB ICE 2000 High-Performance Universal Erasing a Row of Program Memory .......................... 51
In-Circuit Emulator ........................................................... 175 Initiating the Programming Sequence ....................... 52
MPLAB Integrated Development Environment Loading Write Latches ............................................... 52
Software ........................................................................... 173 Protection Against Accidental Writes to OSCCON .......... 155
MPLAB PM3 Device Programmer ................................... 175 PWM Duty Cycle Comparison Units .................................. 99
MPLAB REAL ICE In-Circuit Emulator System ................ 175 Duty Cycle Immediate Updates ................................. 99
MPLINK Object Linker/MPLIB Object Librarian ............... 174 Duty Cycle Register Buffers ...................................... 99
PWM Fault Pins ............................................................... 102
O Enable Bits .............................................................. 102
Operating Current (IDD) .................................................... 180 Fault States ............................................................. 102
Oscillator Input Modes ............................................................. 102
Operating Modes (Table) ......................................... 150 Cycle-by-Cycle ................................................ 102
System Overview ..................................................... 149 Latched ............................................................ 102
Oscillator Configurations .................................................. 152 Priority ..................................................................... 102
Fail-Safe Clock Monitor ............................................ 154 PWM Operation During CPU Idle Mode .......................... 103
Fast RC (FRC) ......................................................... 153 PWM Operation During CPU Sleep Mode ....................... 103

© 2008 Microchip Technology Inc. DS70150D-page 225

dsPIC30F6010A/6015
PWM Output and Polarity Control .................................... 102 Operation During CPU Idle Mode ............................ 107
Output Pin Control ................................................... 102 Operation During CPU Sleep Mode ......................... 107
PWM Output Override ...................................................... 101 SDOx Disable .......................................................... 105
Complementary Output Mode .................................. 101 Slave Select Synchronization .................................. 107
Synchronization ....................................................... 101 SPI1 Register Map ................................................... 108
PWM Period ....................................................................... 98 SPI2 Register Map ................................................... 108
PWM Special Event Trigger ............................................. 103 Word and Byte Communication ............................... 105
Postscaler ................................................................ 103 STATUS Register .............................................................. 16
PWM Time Base ................................................................ 97 Symbols Used in Opcode Descriptions ........................... 166
Continuous Up/Down Counting Modes ...................... 97 System Integration ........................................................... 149
Double Update Mode ................................................. 98 Register Map for dsPIC30F6010A ........................... 163
Free-Running Mode ................................................... 97 Register Map for dsPIC30F6015 ............................. 163
Postscaler .................................................................. 98
Prescaler .................................................................... 98 T
Single-Shot Mode ...................................................... 97 Timer1 Module ................................................................... 65
PWM Update Lockout ...................................................... 103 Gate Operation .......................................................... 66
Interrupt ..................................................................... 67
Q Operation During Sleep Mode ................................... 66
QEI Prescaler ................................................................... 66
16-bit Up/Down Position Counter Mode ..................... 90 Real-Time Clock ........................................................ 67
Count Direction Status ....................................... 90 Interrupts ........................................................... 67
Error Checking ................................................... 90 Oscillator Operation ........................................... 67
Quadrature Encoder Interface (QEI) Module ..................... 89 Register Map ............................................................. 68
Interrupts .................................................................... 92 16-bit Asynchronous Counter Mode .......................... 65
Logic .......................................................................... 90 16-bit Synchronous Counter Mode ............................ 65
Operation During CPU Idle Mode .............................. 91 16-bit Timer Mode ...................................................... 65
Operation During CPU Sleep Mode ........................... 91 Timer2 and Timer3 Selection Mode ................................... 86
Register Map .............................................................. 93 Timer2/3 Module ................................................................ 69
Timer Operation During CPU Idle Mode .................... 92 ADC Event Trigger ..................................................... 74
Timer Operation During CPU Sleep Mode ................. 91 Gate Operation .......................................................... 74
Interrupt ..................................................................... 74
R Operation During Sleep Mode ................................... 74
Reader Response ............................................................ 229 Register Map ............................................................. 75
Reset ........................................................................ 149, 155 Timer Prescaler ......................................................... 74
Reset Sequence ................................................................. 43 32-bit Synchronous Counter Mode ............................ 69
Reset Sources ........................................................... 43 32-bit Timer Mode ...................................................... 69
Resets Timer4/5 Module ................................................................ 77
Brown-out Rest (BOR), Programmable ................... 157 Register Map ............................................................. 79
POR with Long Crystal Start-up Time ...................... 157 Timing Diagrams
POR, Operating without FSCM and PWRT ............. 157 Band Gap Start-up Time .......................................... 193
Power-on Reset (POR) ............................................ 156 CAN Bit .................................................................... 130
Revision History ............................................................... 221 CAN I/O ................................................................... 211
RTSP Control Registers ..................................................... 50 Center-Aligned PWM ................................................. 99
NVMADR ................................................................... 50 Dead-Time ............................................................... 101
NVMADRU ................................................................. 50 Edge-Aligned PWM ................................................... 98
NVMCON ................................................................... 50 External Clock .......................................................... 186
NVMKEY .................................................................... 50 Input Capture (CAPx) .............................................. 197
I2C Bus Data (Master Mode) ................................... 207
S I2C Bus Data (Slave Mode) ..................................... 209
Simple Capture Event Mode I2C Bus Start/Stop Bits (Master Mode) .................... 207
Capture Buffer Operation ........................................... 82 I2C Bus Start/Stop Bits (Slave Mode) ...................... 209
Capture Prescaler ...................................................... 81 Motor Control PWM ................................................. 199
Hall Sensor Mode ...................................................... 82 Motor Control PWM Fault ........................................ 199
Timer2 and Timer3 Selection Mode ........................... 82 OC/PWM .................................................................. 198
Simple Output Compare Match Mode ................................ 86 Output Compare (OCx) ............................................ 197
Simple PWM Mode ............................................................ 86 PWM Output .............................................................. 87
Input Pin Fault Protection ........................................... 86 QEA/QEB Input ....................................................... 200
Period ......................................................................... 87 QEI Module Index Pulse .......................................... 201
Single-Pulse PWM Operation .......................................... 101 Reset, Watchdog Timer, Oscillator Start-up
Software Controlled Clock Stretching (STREN = 1) ......... 112 Timer and Power-up Timer ...................................... 192
Software Simulator (MPLAB SIM) .................................... 174 SPI Master Mode (CKE = 0) .................................... 202
Software Stack Pointer, Frame Pointer .............................. 16 SPI Master Mode (CKE = 1) .................................... 203
CALL Stack Frame ..................................................... 31 SPI Slave Mode (CKE = 0) ...................................... 204
SPI Module ....................................................................... 105 SPI Slave Mode (CKE = 1) ...................................... 205
Framed SPI Support ................................................ 107 Time-out Sequence on Power-up
Operating Function Description ............................... 105 (MCLR Not Tied to VDD), Case 1 ............................. 156

DS70150D-page 226 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
Time-out Sequence on Power-up (MCLR Receive Buffer Overrun Error (OERR Bit) ....... 120
Not Tied to VDD), Case 2 ......................................... 157 Setting Up Data, Parity and Stop Bit Selections ...... 119
Time-out Sequence on Power-up (MCLR Transmitting Data .................................................... 119
Tied to VDD) ............................................................. 156 In 8-bit Data Mode ........................................... 119
TimerQ (QEI Module) External Clock ...................... 196 In 9-bit Data Mode ........................................... 119
Timer1, 2, 3, 4, 5 External Clock .............................. 194 Interrupt ........................................................... 120
10-bit High-Speed A/D Conversion (CHPS = 01, Transmit Break ................................................ 120
SIMSAM = 0, ASAM = 0, SSRC = 000) ................... 214 Transmit Buffer (UxTXB) ................................. 119
10-bit High-Speed A/D Conversion (CHPS = 01, UART1 Register Map .............................................. 123
SIMSAM = 0, ASAM = 1, SSRC = 111, UART2 Register Map .............................................. 123
SAMC = 00001) ....................................................... 215 Unit ID Locations ............................................................. 149
Timing Requirements Universal Asynchronous Receiver
Input Capture ........................................................... 197 Transmitter Module (UART) ............................................. 117
Timing Specifications
Band Gap Start-up Time Requirements ................... 193 W
CAN I/O Requirements ............................................ 211 Wake-up from Sleep ........................................................ 149
CLKOUT and I/O Characteristics ............................. 191 Wake-up from Sleep and Idle ............................................ 45
CLKOUT and I/O Requirements .............................. 191 Watchdog Timer (WDT) ........................................... 149, 160
External Clock Requirements .................................. 187 Enabling and Disabling ............................................ 160
Internal Clock Examples .......................................... 189 Operation ................................................................. 160
I2C Bus Data Requirements (Master Mode) ............ 208 WWW Address ................................................................ 228
I2C Bus Data Requirements (Slave Mode) .............. 210 WWW, On-Line Support ...................................................... 7
Motor Control PWM Requirements .......................... 199
Output Compare Requirements ............................... 197
PLL Clock ................................................................. 188
PLL Jitter .................................................................. 188
QEI External Clock Requirements ........................... 196
QEI Index Pulse Requirements ................................ 201
Quadrature Decoder Requirements ......................... 200
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ................................................ 193
Simple OC/PWM Mode Requirements .................... 198
SPI Master Mode (CKE = 0) Requirements ............. 202
SPI Master Mode (CKE = 1) Requirements ............. 203
SPI Slave Mode (CKE = 0) Requirements ............... 204
SPI Slave Mode (CKE = 1) Requirements ............... 205
Timer1 External Clock Requirements ...................... 194
Timer2 and Timer4 External Clock Requirements ... 195
Timer3 and Timer5 External Clock Requirements ... 195
10-bit High-Speed A/D ............................................. 212
10-bit High-Speed A/D Conversion Requirements .. 216
Traps .................................................................................. 43
Hard and Soft ............................................................. 44
Sources ...................................................................... 43
Vectors ....................................................................... 44

U
UART
Address Detect Mode .............................................. 121
Auto-Baud Support .................................................. 122
Baud Rate Generator (BRG) .................................... 121
Disabling .................................................................. 119
Enabling and Setup .................................................. 119
Loopback Mode ....................................................... 121
Module Overview ..................................................... 117
Operation During CPU Sleep and Idle Modes ......... 122
Receiving Data ......................................................... 120
In 8-bit or 9-bit Data Mode ............................... 120
Interrupt ........................................................... 120
Receive Buffer (UxRXB) .................................. 120
Reception Error Handling ......................................... 120
Framing Error (FERR) ..................................... 121
Idle Status ........................................................ 121
Parity Error (PERR) ......................................... 121
Receive Break ................................................. 121

© 2008 Microchip Technology Inc. DS70150D-page 227

dsPIC30F6010A/6015
NOTES:

DS70150D-page 228 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
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Questions (FAQ), technical support requests, included in the back of this document.
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© 2008 Microchip Technology Inc. DS70150D-page 229

dsPIC30F6010A/6015
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: dsPIC30F6010A/6015 Literature Number: DS70150D

Questions:

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DS70150D-page 230 © 2008 Microchip Technology Inc.

 dsPIC30F6010A/6015
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

d s P I C 3 0 F 6 0 1 0 AT- 3 0 I / P F - 0 0 0
Custom ID (3 digits) or
Trademark Engineering Sample (ES)

Architecture

Package
Flash PF = TQFP 14x14
PT = TQFP 12x12
PT = TQFP 10x10
Memory Size in Bytes S = Die (Waffle Pack)
0 = ROMless W = Die (Wafers)
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K Temperature
5 = 49K to 96K I = Industrial -40°C to +85°C
6 = 97K to 192K E = Extended High Temp -40°C to +125°C
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID
T = Tape and Reel

A,B,C… = Revision Level

Example:
dsPIC30F6010AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A

© 2008 Microchip Technology Inc. DS70150D-page 231

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Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid
Fax: 630-285-0075 China - Nanjing Tel: 34-91-708-08-90
Malaysia - Kuala Lumpur
Tel: 86-25-8473-2460 Fax: 34-91-708-08-91
Dallas Tel: 60-3-6201-9857
Addison, TX Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham
Tel: 972-818-7423 China - Qingdao Tel: 44-118-921-5869
Malaysia - Penang
Fax: 972-818-2924 Tel: 86-532-8502-7355 Fax: 44-118-921-5820
Tel: 60-4-227-8870
Detroit Fax: 86-532-8502-7205 Fax: 60-4-227-4068
Farmington Hills, MI China - Shanghai Philippines - Manila
Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 63-2-634-9065
Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 63-2-634-9069
Kokomo China - Shenyang Singapore
Kokomo, IN Tel: 86-24-2334-2829 Tel: 65-6334-8870
Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 65-6334-8850
Fax: 765-864-8387
China - Shenzhen Taiwan - Hsin Chu
Los Angeles Tel: 86-755-8203-2660 Tel: 886-3-572-9526
Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-3-572-6459
Tel: 949-462-9523
China - Wuhan Taiwan - Kaohsiung
Fax: 949-462-9608
Tel: 86-27-5980-5300 Tel: 886-7-536-4818
Santa Clara Fax: 86-27-5980-5118 Fax: 886-7-536-4803
Santa Clara, CA
China - Xiamen Taiwan - Taipei
Tel: 408-961-6444
Tel: 86-592-2388138 Tel: 886-2-2500-6610
Fax: 408-961-6445
Fax: 86-592-2388130 Fax: 886-2-2508-0102
Toronto
China - Xian Thailand - Bangkok
Mississauga, Ontario,
Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Canada
Tel: 905-673-0699 Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Fax: 905-673-6509 China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

01/02/08

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