Scribd
Upload
48 views

Lab 5

This document provides a circuit diagram with the following key details: 1) It shows connections between multiple DIP switches, logic gates (74LS00, 74LS147, 74LS83, 74LS86), and a common anode display. 2) Resistors are connected in series with the DIP switches and logic gates to reduce current. 3) The logic gates are connected such that their outputs determine which switches will control the segments of the display.

Uploaded by

Duvan Bustos
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
48 views

Lab 5

This document provides a circuit diagram with the following key details: 1) It shows connections between multiple DIP switches, logic gates (74LS00, 74LS147, 74LS83, 74LS86), and a common anode display. 2) Resistors are connected in series with the DIP switches and logic gates to reduce current. 3) The logic gates are connected such that their outputs determine which switches will control the segments of the display.

Uploaded by

Duvan Bustos
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 1

VCC

75K 75K 75K 75K 75K 75K 75K 75K VCC


DSW1
OFF ON
16 1 10 9 1
0 A0
15 2 11 7 3
1 A1
14 3 12 6 2
2 A2
13 4 13
3
12 5 1 14 74LS00
4 GS
11 6 2
5
10 7 3 4
6
9 8 4 6
VCC 7
5
DIPSW_8 5 15
EI EO
74LS00
10
74LS148 8
75K 75K 75K 75K 9

DSW2 74LS00 10 9 7 13
OFF ON A1 S1 A QA
8 1 10 9 8 6 1 12
0 A0 A2 S2 B QB
7 2 11 7 3 2 2 11
1 A1 A3 S3 C QC
6 3 12 6 1 15 6 10
2 A2 A4 S4 D QD
5 4 13 4 9
3 BI/RBO QE
1 14 11 5 15
4 GS B1 RBI QF
DIPSW_4 2 7 3 14
5 B2 LT QG
3 4
6 B3
4 16
7 B4 74LS47
5 15 13 14
EI EO C0 C4

VCC 74LS83
| VCC 74LS148
220 220 220 220 220 220 220 VCC
1
3
2

75K 75K 75K 75K


74LS86 VCC
4
6
5
DSW3
OFF ON
8 1 74LS86
7 2
6 3 9
5 4 8
10
DIPSW_4
74LS86
Display ánodo común
12
11
13
75K
74LS86 Vcc= 5v
SW1

SW-SPST

You might also like