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VHDL Interface Programs

This document describes code for controlling a stepper motor and an elevator using a keypad. The stepper motor code uses a clock divider, key press detection, and 4-step counter to generate step signals for a stepper motor. The elevator code uses a clock divider, key scan logic, and floor selection logic to control a 7-segment display showing the current floor. Key presses are decoded to select and move between floors. The keypad interface code is reused for both applications to handle key scanning and key press detection from a 4x4 keypad.

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251 views

VHDL Interface Programs

This document describes code for controlling a stepper motor and an elevator using a keypad. The stepper motor code uses a clock divider, key press detection, and 4-step counter to generate step signals for a stepper motor. The elevator code uses a clock divider, key scan logic, and floor selection logic to control a 7-segment display showing the current floor. Key presses are decoded to select and move between floors. The keypad interface code is reused for both applications to handle key scanning and key press detection from a 4x4 keypad.

Uploaded by

sshhaz
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 17

***STEPPER MOTOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
pclk100K : in std_logic );
end TKBSTP;

architecture behavioral of TKBSTP is


signal sclkdiv : std_logic_vector(20 downto 0);
signal sstpcnt : std_logic_vector(1 downto 0);
signal sstpclk,skeyhit : std_logic;
signal skeysts :std_logic_vector (3 downto 0);

begin

-- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

sstpclk <= sclkdiv(15);


end process;

-- key process
-- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin
if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;
-- latch key press
process(skeyhit)
begin
if( falling_edge(skeyhit)) then
skeysts <= pkeycol;
end if;
end process;

-- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;

-- outputs signal pstpsig = D, C, B & A for stepper motor


-- TKBase from ucf file = 33,31,30, 29
-- als stepper controller = 4, 6, 3 & 5
process(sstpcnt)
begin
if (sstpcnt = "00") then pstpsig <= "0001";
elsif(sstpcnt = "01") then pstpsig <= "0111";
elsif(sstpcnt = "10") then pstpsig <= "1110";
elsif(sstpcnt = "11") then pstpsig <= "1000";
end if;
end process;

end behavioral;

// Template UCF file created by the Project Navigator

#PINLOCK_BEGIN

#Fri Sep 17 15:40:24 2004

NET "pclk100K" LOC = "p77" ;


# NET PKEY RET
NET "pkeycol<0>" LOC = "P3" ;
NET "pkeycol<1>" LOC = "P4" ;
NET "pkeycol<2>" LOC = "P5" ;
NET "pkeycol<3>" LOC = "P6" ;
# NET PKEY SCAN
NET "pkeyrow<0>" LOC = "P8" ;
NET "pkeyrow<1>" LOC = "P9" ;
NET "pkeyrow<2>" LOC = "P10" ;
NET "pkeyrow<3>" LOC = "P14" ;
# USE THIS FOR STEPPER OR DISPLAY MUX
NET "pstpsig<0>" LOC = "P29";
NET "pstpsig<1>" LOC = "P30";
NET "pstpsig<2>" LOC = "P31";
NET "pstpsig<3>" LOC = "P33";
#PINLOCK_END

******end of stepper motor***********************


***** ELEVATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic
);
end TKBELE;

architecture behavioral of TKBELE is

signal scurflr,snxtflr,skeyflr : integer range 0 to 15;


signal sdir, skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(15 downto 0);
signal sflrclk,skeyclk : std_logic;

begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;

process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;

-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyflr <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyflr <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyflr <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyflr <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyflr <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyflr <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyflr <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyflr <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyflr <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyflr <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyflr <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyflr <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyflr <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyflr <= 15;
end if;
end if;
end process;

-- process clk divider


--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

skeyclk <= sclkdiv(6);


sflrclk <= sclkdiv(15);
end process;

-- process for key scan clkscan


process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
elsif skeyscn = "1011" then skeyscn <= "0111";
elsif skeyscn = "0111" then skeyscn <= "1110";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;

-- process floor motion


process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;

-- process display 7seg


process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","000011
1",
"11111
11","1101111","1110111","1111100","1011000","1011110","1111001","1110001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
end behavioral;

#PINLOCK_BEGIN

#Fri Oct 15 18:17:09 2004

NET "pclk100K" LOC = "p77" ;

NET "pkeyret<0>" LOC = "P3" ;


NET "pkeyret<1>" LOC = "P4" ;
NET "pkeyret<2>" LOC = "P5" ;
NET "pkeyret<3>" LOC = "P6" ;
NET "pkeyscn<0>" LOC = "P8" ;
NET "pkeyscn<1>" LOC = "P9" ;
NET "pkeyscn<2>" LOC = "P10";
NET "pkeyscn<3>" LOC = "P14" ;

NET "pdspmux<0>" LOC = "P29" ;


NET "pdspmux<1>" LOC = "P30" ;
NET "pdspmux<2>" LOC = "P31" ;
NET "pdspmux<3>" LOC = "P33" ;

NET "pdspseg<0>" LOC = "P34" ;


NET "pdspseg<1>" LOC = "P35" ;
NET "pdspseg<2>" LOC = "P36" ;
NET "pdspseg<3>" LOC = "P37" ;
NET "pdspseg<4>" LOC = "P41" ;
NET "pdspseg<5>" LOC = "P42" ;
NET "pdspseg<6>" LOC = "P43" ;

#PINLOCK_END

*****END OF ELEVATOR
******HEX KEY PAD

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
--pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic
);

end TKBHKY;

architecture behavioral of TKBHKY is

signal skeyval : integer range 0 to 15;


signal skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(15 downto 0);
signal skeyclk : std_logic;

begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;

process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;

-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyval <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyval <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyval <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyval <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyval <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyval <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyval <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyval <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyval <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyval <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyval <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyval <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyval <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyval <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyval <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyval <= 15;
end if;
end if;
end process;

-- process clk divider


--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

skeyclk <= sclkdiv(6);


end process;

-- process for key scan clkscan


process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
elsif skeyscn = "1011" then skeyscn <= "0111";
elsif skeyscn = "0111" then skeyscn <= "1110";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;

-- process display 7seg


process(skeyval)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","000011
1",
"11111
11","1101111","1110111","1111100","1011000","1011110","1111001","1110001");
begin
pdspseg <= segval(skeyval);
pdspmux <= "1110";
end process;

end behavioral;

*****ucf file

#PINLOCK_BEGIN

#Wed May 07 13:59:36 2008


NET "pkeyret<0>" LOC = "P3";
NET "pkeyret<1>" LOC = "P4";
NET "pkeyret<2>" LOC = "P5";
NET "pkeyret<3>" LOC = "P6";

NET "pkeyscn<0>" LOC = "P8";


NET "pkeyscn<1>" LOC = "P9";
NET "pkeyscn<2>" LOC = "P10";
NET "pkeyscn<3>" LOC = "P14";

NET "pdspmux<0>" LOC = "P29";


NET "pdspmux<1>" LOC = "P30";
NET "pdspmux<2>" LOC = "P31";
NET "pdspmux<3>" LOC = "P33";

NET "pdspseg<0>" LOC = "P34";


NET "pdspseg<1>" LOC = "P35";
NET "pdspseg<2>" LOC = "P36";
NET "pdspseg<3>" LOC = "P37";
NET "pdspseg<4>" LOC = "P41";
NET "pdspseg<5>" LOC = "P42";
NET "pdspseg<6>" LOC = "P43";

NET "pclk100K" LOC = "P77";


#PINLOCK_END

******ENDS HEX KEY PAD


*******DC MOTOR

-- ALS NIFC37 DC motor


-- connect J4-pin 26 to GND
-- connect J4-pin 25 to +5V
-- connect J4-pin 5 to CPLD pin 9 (pdcm)
-- connect tkbase clk 500khz to CPLD pin 20
-- CPLD Pin 1,2,3 as SW 0,1,2;
-- sw0 sw1 sw2
-- 0 0 0 = 500rpm
-- 1 0 0 = 800rpm
-- 0 1 0
--
-- 1 1 1 = 2500rpm

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic
);
end TKBDCM;

architecture behavioral of TKBDCM is


signal sclkdiv : std_logic_vector(11 downto 0);

begin

-- count upto 3000


process(p100k)
begin
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;

if(sclkdiv = "101110111000") then


sclkdiv <= "000000000000";
end if;
end process;
process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;

-- 1f4,320,44c,578,6a4,7d0,8fc,9c4
if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';
elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0';
end if;

if(vdcm = '1') then pdcm <= '1';


else pdcm <= '0';
end if;

end process;

end behavioral;

****UCF FILE

#PINLOCK_BEGIN

#Thu Apr 28 12:06:42 2005

NET "p100k" LOC = "P77";


NET "psw<0>" LOC = "P5";
NET "psw<1>" LOC = "P7";
NET "psw<2>" LOC = "P9";
NET "pdcm" LOC = "P10";
#PINLOCK_END

*****END OF DC MOTOR
********LCD DISPLAY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tkblcd is
Port (
plcddat : out std_logic_vector (7 downto 0);
plcdrs,plcdrw,plcden : out std_logic;
pclk100K : in std_logic
);
end tkblcd;

architecture behavioral of tkblcd is

signal sclkdiv : std_logic_vector(15 downto 0);


signal sdspclk : std_logic;
signal tchr1 : character;

constant mystr : string := "amctc";

begin

-- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

sdspclk <= sclkdiv(15);


plcden <= sclkdiv(15);
end process;

-- display
process(sdspclk)
variable vdspseq : integer range 0 to 15;
variable vdspnum : integer range 0 to 15;
variable i1 : integer;

type tlcdtyp is array(0 to 15) of std_logic_vector (7 downto 0);


constant tlcddat : tlcdtyp :=
("00111000","00001110","00000010","00000001",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000"
);

begin

if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if;

if(vdspseq < 4) then


plcddat <= tlcddat(vdspseq);
vdspnum := 0;
else

-- plcddat <= tlcddat(vdspseq);

tchr1 <= mystr(vdspnum);


plcddat <= std_logic_vector(to_unsigned(character'pos(tchr1),8));
end if;

plcdrw <= '0';


if(vdspseq < 4) then
plcdrs <= '0';
else
plcdrs <= '1';
end if;

end process;

end behavioral;

*******UCF FILE
#PINLOCK_BEGIN

#Fri Oct 15 18:04:12 2004

NET "pclk100K" LOC = "P77";

NET "plcdrs" LOC = "P57";


NET "plcdrw" LOC = "P58";
NET "plcden" LOC = "P59";

NET "plcddat<0>" LOC = "P61";


NET "plcddat<1>" LOC = "P62";
NET "plcddat<2>" LOC = "P63";
NET "plcddat<3>" LOC = "P67";
NET "plcddat<4>" LOC = "P68";
NET "plcddat<5>" LOC = "P69";
NET "plcddat<6>" LOC = "P70";
NET "plcddat<7>" LOC = "P71";

#PINLOCK_END

*****END OF LCD DISPLAY

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