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Cmos Four Quadrant Analog Multiplier

This document summarizes a research paper about a CMOS four-quadrant analog multiplier circuit with single-ended voltage output and improved temperature performance. The circuit uses MOS transistors as a transconductor to produce an output current proportional to the product of the two input voltages. To improve temperature stability, the design incorporates a MOS resistor that compensates for threshold voltage changes with temperature. Experimental results showed the circuit has good linearity and bandwidth with low noise and power consumption.

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Anurag Arora
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187 views15 pages

Cmos Four Quadrant Analog Multiplier

This document summarizes a research paper about a CMOS four-quadrant analog multiplier circuit with single-ended voltage output and improved temperature performance. The circuit uses MOS transistors as a transconductor to produce an output current proportional to the product of the two input voltages. To improve temperature stability, the design incorporates a MOS resistor that compensates for threshold voltage changes with temperature. Experimental results showed the circuit has good linearity and bandwidth with low noise and power consumption.

Uploaded by

Anurag Arora
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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A CMOS Four-Quadrant Analog Multiplier

with Single-Ended Voltage Output and


Improved Temperature Performance
• BY ZHENUA WANG
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 9,
SEPTEMBER 1991

PRESENTATION BY –

ABHISHEK ARORA

ROLL NO.- 4/EC/07


ANALOG MULTIPLIERS-WHY DO WE
NEED THEM?
ANALOG MULTIPLIERS FIND APPLICATIONS IN VARIOUS AREAS LIKE IN
• SIGNAL PROCESSING CIRCUITS SUCH AS IN CORRELATORS,CONVOLVERS,ADAPTIVE
FILTERS AND CURVE FITTING GENERATORS

• MODULATION ,FREQUENCY TRANSLATION,AUTOMATIC GAIN CONTROLLING

• IN SQUARING AND SQUARE ROOTING CIRCUITS

• IN FREQUENCY DOUBLING CIRCUITS

• IN NARROW BAND FM MODULATION


PRINCIPLE OF OPERATION
• BLOCK DIAGRAM OF THE PROPOSED MULTIPLIER
LINEAR MOS TRANSCONDUCTOR USED AS MULTIPLIER
THE EQUATIONS 1 AND 2 WHEN SUBTRACTED GIVE A TERM WHICH IS PROPOTIONAL TO
THE PRODUCT OF THE INPUT VOLTAGES

•THEREFORE THE OUTPUT CURRENT BECOMES PROPOTIONAL TO THE


PRODUCT OF THE VOLTAGES AND WITHOUT THE RESTRICTION AS IN BIPOLAR
CASE BECAUSE OF THE TAN HYPERBOLIC TERM IS PRESENT HERE THE
LINEARITY INCREASES.

•THE FLOATING INPUT VOLTAGE IS GIVEN BY USING LEVEL SHIFTERS.


THE (a) CIRCUIT IS USED WHEN WE HAVE TO PERFORM A TWO QUADRANT MULTIPLYING
OPERATION.IN CASE A FOUR QUADRANT MULTIPLYING OPERATION IS REQUIRED WE USE
THE SECOND CIRCUIT .

UPON APPLYING THE CONDITION OF SATURATION TO ALL THE TRANSISTORS THE REGION IN
WHICH THE MULTIPLYING EFFECT IS ACHIEVED IS RESTRICTED TO THE ELLIPTIC REGION AS
SHOWN BELOW
THIS IS THE SCALED VOLTAGE PAIR GENERATOR USED TO REALISE THE TWO BIAS INPUT
VOLTAGES FOR THE MOS TRANSCONDUCTOR.
THIS IS THE LINEAR MOS RESISTOR REALIZED BY USING 2 TRANSISTORS IN THE
SATURATION REGION.THE OUTPUT VOLTAGE IS TAKEN ACROSS THIS RESISTOR.THE
DIFFERENTIAL CURRENT IS FED TO THIS RESISTOR
THE COMPLETE FOUR QUADRANT
MULTIPLIER
TEMPERATURE PERFORMANCE OF
MULTIPLIER
• THE OUTPUT VOLTAGE EXPRESSION AS GIVEN BY THE PREVIOUS EQUATION IS HIGHLY
TEMPERATURE DEPENDENT BECAUSE IT IS RELATED TO MOBILITY AND THRESHOLD
VOLTAGE BOTH OF WHICH ARE FUNCTIONS OF TEMPERATURE.

• THRESHOLD VOLTAGE CHANGES BY 2.3MV/DEGREE CELCIUS.THE RELATION IS


EXPRESSED AS

THE CHANGE DUE TO TEMPERATURE DEPENDENCE OF MOBILITY IS

THE EXPONENT VARIES BETWEEN 1.5 AND 2.


CHANGES MADE TO MINIMISE
TEMPERATURE EFFECTS
• A NEW MOS RESISTOR IS REPLACED BY THE ONE SHOWN BEFORE TO COMPENSATE
FOR THRESHOLD VOLTAGE
DISCUSSION
• THE EXPERIMENTAL RESULTS CONFIRM THE GOOD PERFORMANCE OF THIS
MULTIPLIER.THE MAXIMUM NON LINEARITY ERRORS ARE WITHIN 1% FOR BOTH Vx AND
Vy IN THE RANGE OF -2.5V TO 2.5V.

• IT HAS A SMALL SIGNAL BANDWIDTH OF DC TO 1.2 MHZ AND OUTPUT NOISE 73DB
BELOW FULL SCALE HAVE BEEN MEASURED.

• POWER CONSUMPTION IS 6MW.

• A NEW APPROACH FOR BUILDING A TEMPERATURE INDEPENDENT MULTIPLIER HAS


BEEN DEVISED.
REFERENCES

• J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrant CMOS


• analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6,
• pp. 1158-1168, Dec. 1985.
• K. Bult, “Analog square-law circuits,” Ph.D. dissertation, Univ.
• Twente, The Netherlands, 1988.
• K. Bult and H. Wallinga, “A class of analog CMOS circuits based
• on the square-law characteristic of an MOS transistor in saturation,”
• IEEE J. Solid-state Circuits, vol. SC-22, no. 3, pp. 357-365, June
• 1987.
• K. Bult and H. Wallinga, “CMOS four-quadrant analog multiplier,”
• IEEE J. Solid-state Circuits, vol. SC-21, no. 3, pp. 430-435, June
• 1986.
• B. Gilbert, “A high-performance monolithic multiplier using active
Wang, Current-Mode Analog Integrated Circuits and
Linearization
Techniques in CMOS Technology, vol. 7, Series in
Microelectronics.
Konstanz, Germany: Hartung-Gome Verlag, 1990.
THANK YOU!!

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