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Implementing Precise Interrupts in Pipeline Processors

This paper discusses techniques for implementing precise interrupts in pipeline processors by saving the state of the processor whenever an interrupt occurs, including the program counter, registers, and memory. It evaluates different schemes like in-order completion, reorder buffers with and without bypass paths, and history buffers. The schemes are evaluated on a CRAY-1S simulation system for performance. The paper also describes how these techniques can be applied to handle additional state information from virtual memory, caches, pipelines, and vectors while providing architectural solutions for precise interrupts.

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rdxz12
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87 views

Implementing Precise Interrupts in Pipeline Processors

This paper discusses techniques for implementing precise interrupts in pipeline processors by saving the state of the processor whenever an interrupt occurs, including the program counter, registers, and memory. It evaluates different schemes like in-order completion, reorder buffers with and without bypass paths, and history buffers. The schemes are evaluated on a CRAY-1S simulation system for performance. The paper also describes how these techniques can be applied to handle additional state information from virtual memory, caches, pipelines, and vectors while providing architectural solutions for precise interrupts.

Uploaded by

rdxz12
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Implementing Precise Interrupts in Pipeline Processors

Review:-

This paper mainly talks about making precise interrupts in pipeline processors. Whenever
interrupt occur architecture saves the state of process (program counter registers and memory) , and if this
state is consistent with the sequential architecture then the interrupt is precise.
In this paper authors have explained various different schemes of precise interrupts namely
In order Instruction completion, reorder buffer (with and w/o bypass paths), History buffer and future file.
Then they have evaluated performance of these architectures on CRAY-1S simulation system. After
performance evaluation authors have described how to use these methods to handle addition state
information such as virtual memory, cache memory linear pipeline and vectors, while suggesting
architectural solutions for precise interrupts.

Strong Points:
1. All the architectures compared and their advantages are told over each other.
2. In precise interrupt, the additional information need to be stored apart from process state is alsom
mentioned very briefly.

Weak points:-
1) In the In-Order Instruction Completion the fast instructions without data dependence also waits for
other instructions to get complete, which decreases performance.
2) In case of reorder buffer method, we need bypass comparators for the multiple bypass checks, which
give additional hardware penalty.

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