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Computer Architecture: First Edition

SYLLABUS CS5101 COMPUTER Architecture Measuring and Reporting Performance. Classifying Instruction set Architecture - Memory Addressing - Addressing Modes - Type and Size of Operands - Operations in the Instruction Set.

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Thangavel Murugan
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1K views

Computer Architecture: First Edition

SYLLABUS CS5101 COMPUTER Architecture Measuring and Reporting Performance. Classifying Instruction set Architecture - Memory Addressing - Addressing Modes - Type and Size of Operands - Operations in the Instruction Set.

Uploaded by

Thangavel Murugan
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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COMPUTER ARCHITECTURE

First Edition

M. Thangavel B.E. (CSE), M.E. (CSE)

With the Guidance of,

S. Kalpana B.E. (CSE), M.E. (CSE)

S. Shanmuga Priya B.E. (CSE), M.E. (CSE)

Dedicated to,

M.E. Students,

Computer Science and Engineering Department,

J.J. College of Engineering & Technology, 


Ammapettai, Poolangulathupatti (Post), 
Tiruchirappalli - 620 009,
Tamil Nadu, 
India.
SYLLABUS

CS5101 COMPUTER ARCHITECTURE

UNIT I FUNDAMENTALS OF COMPUTER DESIGN


Measuring and Reporting Performance – Quantitative Principles of Computer Design –
Classifying Instruction set Architecture – Memory Addressing – Addressing Modes – Type and
Size of Operands – Operations in the Instruction Set – Operands and Operations for Media and
Signal Processing – Instructions for Control Flow – Encoding an Instruction Set – Example
Architecture – MIPS and TM32.
UNIT II INSTRUCTION LEVEL PARALLELISM
Pipelining and Hazards – Concepts of ILP – Dynamic Scheduling – Dynamic Hardware
Prediction – Multiple Issues – Hardware based Speculation – Limitations of ILP – Case Studies
– lP6 Micro Architecture
UNIT III INSTRUCTION LEVEL PARALLELISM WITH SOFTWARE APPROACH
Compiler Techniques for Exposing ILP – Static Branch Prediction – Static Multiple Issue. VLIW
– Advanced Compiler Support – Hardware Support for Exposing Parallelism – Hardware Vs
Software Speculation. Mechanism – IA 64 and Itanium Processor.
UNIT IV MEMORY AND I/O
Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main
Memory and Performance – Memory Technology – Types of Storage Devices – Buses – RAID –
Reliability– Availability and Dependability – I/O Performance Measures – Designing I/O
system.
UNIT V MULTIPROCESSORS AND THREAD LEVEL PARALLELISM
Symmetric and Distributed Shared Memory Architectures – Performance Issues –
Synchronization – Models of Memory Consistency – Multithreading.

TABLE OF CONTENTS
Unit 1 Fundamentals Of Computer Design

1.1 Introduction……………………………………………………….……………………. 001

1.2 The Changing Face Of Computing


And The Task Of The Computer Designer……………………….………………… 002

1.3 Technology Trends ……………………………………….…………………………… 007

1.4 Cost, Price And Their Trends ……………………………………………………….. 009

1.5 Measuring And Reporting Performance …………………………..……………… 013

1.6 Quantitative Principles Of Computer Design………………………………….… 020

1.7 Introduction…………………………………………………………………………….. 028

1.8 Classifying Instruction Set Architectures…………………………………………. 028

1.9 Memory Addressing…………………………………………………………………… 033

1.10 Addressing Modes For Signal Processing…………….………………..……….… 037

1.11 Type And Size Of Operands………………………………….…………..…………. 039

1.12 Operands For Media And Signal Processing………………….………..………… 041

1.13 Operations In The Instruction Set………………………………………………..… 042

1.14 Operations For Media And Signal Processing………………………………….…. 043

1.15 Instructions For Control Flow…………………………………………………….…. 045

1.16 Encoding An Instruction Set…………………………………………………………. 049

1.17 Crosscutting Issues: The Role Of Compilers ……………………………..…...…. 051

1.18 The MIPS Architecture………………..………………………….…………………… 055

1.19 The Trimedia TM32 CPU……………………………………….…………………….. 061

Unit 2 Instruction Level Parallelism

2.1 Pipelining And Hazards………………………………………………...….…….. 063


2.2 Instruction-Level Parallelism…………………………………………..….……. 095
2.3 Overcoming Data Hazards With Dynamic Scheduling…………..…….….………… 102
2.4 Dynamic Scheduling: Examples And The Algorithm…………...…………………… 108
2.5 Reducing Branch Costs With Dynamic Hardware Prediction……..…….…. 110
2.6 High Performance Instruction Delivery………………………….……….….... 116
2.7 Taking Advantage Of More ILP With Multiple Issue……...………….…….. 119
2.8 Hardware-Based Speculation……………………………………….………..….. 121
2.9 Studies Of The Limitations Of ILP……………………………………..………. 126
2.10 Limitations On ILP For Realizable Processors………………………….……. 136
2.11 The P6 Microarchitecture………………………………………………….……... 140

Unit 3 Instruction Level Parallelism With Software Approach

3.1 Basic Compiler Techniques For Exposing ILP…………………………………. 144


3.2 Static Branch Prediction………………………….………………………..…..…. 147
3.3 Static Multiple Issue: The VLIW Approach……………………………...…….. 149
3.4 Advanced Compiler Support For Exposing And
Exploiting ILP……………………………………………………………...……….. 152
3.5 Hardware Support For Exposing More Parallelism At Compiler Time ….. 172
3.6 Crosscutting Issues Hardware Versus Software
Speculation Mechanisms………………………………………………………..… 178
3.7 The Intel IA-64 Architecture And Itanium Processor………………………… 179

Unit 4 Memory-Hierarchy Design

4.1 Introduction……………………………………………………………….…………. 186


4.2 Cache Performance Review……………………………………………….……..... 188
4.3 Cache Performance………………………………………….……………….……... 194
4.4 Reducing Cache Miss Penalty……………………….…………………….…….. 197
4.5 Reducing Miss Rate………………………………………………………….……. 204
4.6 Reducing Cache Miss Penalty Or Miss Rate Via Parallelism………………. 210
4.7 Reducing Hit Time……………………………………………………………..….. 213
4.8 Main Memory And Organizations For Improving Performance…….……… 217
4.9 Memory Technology…………………………………………………………….…. 221
4.10 Virtual Memory……………………………………………………………………. 225
4.11 Protection And Examples Of Virtual Memory………………………………… 232
4.12 Types Of Storage Systems……………………………….……………………….. 239
4.13 Buses—Connecting I/O Devices To CPU/Memory….…………………………. 244
4.14 Reliability, Availability, And Dependability……………….………………….. 251
4.15 Raid: Redundant Arrays Of Inexpensive Disks……………………………….. 254
4.16 Errors And Failures In Real Systems……………………………………...…… 259
4.17 I/O Performance Measures……………………………………………………….. 264
4.17 Benchmarks Of Storage Performance And Availability……………………... 266
4.18 Design And I/O System In Five Easy Pieces…………………………………... 271

Unit 5 Multiprocessors And Thread-Level Parallelism

5.1 Introduction………………………………………………………………….…..…..… 274

5.2 Characteristics Of Application Domains………………………………………..….. 282

5.3 Symmetric Shared Memory Architectures……………………………….….…...... 284

5.4 Performance Of Symmetric Shared-Memory Multiprocessors…….…............. 293

5.5 Distributed Shared-Memory Architectures………………...…………................. 296


5.6 Performance Of Distributed Shared-Memory Multiprocessors………….…..… 302
5.7 Synchronization…………………………………………………….……………..….. 304
5.8 Models Of Memory Consistency: An Introduction……………..……..….…..….. 308
5.9 Multithreading: Exploiting Thread-Level Parallelism
311
Within A Processor …………………………………………………….……..….

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