Microprocessor and Applications (EC1303) - Question Bank

EC1303 – Microprocessor & Applications Question Bank
EC1303 – Microprocessor and Applications

2 Marks – Question & Answers
Unit I (8085):
1. What are machine language and assembly language programs?
The software developed using 1’s and 0’s are called machine language programs.
The software developed using mnemonics are called assembly language programs.
2. Why data bus is bi-directional?

The microprocessor has to fetch (read) the data from memory or input device for processing
and after processing, it has to store (write) the data to memory or output device. Hence the
data bus in microprocessor is bi-directional.
3. Why interfacing is needed for I/0 devices?

Generally I/O devices are slow devices. Therefore the speed of I/O devices does not match
with the speed of microprocessor. Therefore, an interface is provided between
microprocessor and I/O devices.
4. What is data size in a microprocessor?

The Data size is the size of the operand that can be processed by an ALU in a
microprocessor.
5. Why EPROM is mapped at the beginning of memory space in 8085 system?

In 8085 microprocessor, after a reset, the program counter will have the address 0000H. The
monitor program is a permanent program for Initialization and configuring of peripherals
and it is stored in the EPROM memory. If EPROM memory is mapped at the beginning of
memory space, i.e., at 0000H, then the monitor program will be executed automatically after
a reset of the processor. This is why EPROM is mapped at the beginning of memory space.
6. What is Tri-state logic?

A device can reside in three states, which are a) On-state b) Off-state and c) High
impedance-state. The high impedance state is a state in which the output of a device is
physically connected to a bus, but electrically isolated through high impedance.
7. Define Stack and Stack Pointer.

Stack is a portion of RAM memory which is used for temporary storage of register contents
using PUSH and POP instructions. Stack Pointer (SP) is a 16-bit register that holds the
memory address of the stack top. Stack pointer gets decremented by 2, for every push
operation and vice versa.
© NSS, 2008
8. Define Program Counter.

Program Counter (PC) is a 16-bit register which holds the memory address of the
instruction to be executed next. Program counter gets incremented by 1 for every execution
of the instruction.
9. What is the significance of IO/M pin?

IO/M pin is an I/O or Memory access indicator. It asserts to high level (1), when the
processor access the I/O device and it goes to low level (0), when the processor access the
memory for read/write operations.
10. State the function of HOLD and HLDA pins in 8085.

The HOLD and HLDA pins in 8085 are used in interfacing the 8257-DMA controller IC
with the processor.
A signal is sent by 8257 to HOLD pin in µP, to request the µP to stop its current process and
allocate the buses for DMA data transfer.
µP acknowledges the request for DMA data transfer by 8257, by sending a signal in HLDA
to 8257.
11. State the significance of X1 and X2 pins of 8085.

The clock signal is supplied to the microprocessor 8085 by connecting either LC, RC or
quartz crystal across the pins X1 and X2. Out of the three, quartz crystal is preferred because
of its high stability.
12. What is an Interrupt? How the interrupts are classified?

Interrupt is a signal send by an external device to the processor (or special instruction
executed in a program), to stop the execution of the current process in the microprocessor
and perform a particular task (ie., data transfer) between the processor and the called device.
They are three methods of classifying interrupts.
Method I : The interrupts are classified into Hardware and Software interrupts
Method II : The interrupts are classified into Vectored and Non-Vectored interrupts.
Method III : The interrupts are classified as Maskable and Non-maskable interrupts.
© NSS, 2008
13. Distinguish I/O mapped I/O and memory mapped I/O.

Mapping is the process by which the addresses are allocated to the I/O devices.
The two kinds of mapping are a) Memory mapped I/O
b) I/O mapped I/O
Memory mapped I/O Standard I/O mapped I/O

1. 16-bit address is allotted to each 1. 8-bit address is allotted to each I/O
I/O device. device.
2. The I/O devices are accessed by 2. The I/O devices are accessed by I/O
Memory Read or Memory Write Read or I/O write machine cycles
machine cycles.
3. All instructions related to memory 3. Only IN and OUT instructions can
can be used to access I/O devices. be used to access I/O devices.
4. Large number of I/O devices can 4. Only small number of I/O devices
be interfaced. can be interfaced.
5. Data transfer can be made between 5. Data transfer can be made only
all registers and I/O devices. between Accumulator and I/O
devices.
6. This scheme is used when memory 6. This scheme is used when complete
requirement is less. memory space is required.
14. Explain the concept of demultiplexing AD0-7 lines in 8085?

Demultiplexing is the process of separating the low byte Address (A0-7) and Data (D0-7) from
the multiplexed lines AD0-7 lines of 8085, using a latch and Address latch enable (ALE)
signal.
When low byte address (A0-7 ) comes out of AD0-7 lines, the processor asserts HIGH in the
ALE pin, enabling the latch to separate the low byte address.
© NSS, 2008
15. What is memory mapping?

The memory mapping is the process of interfacing memories to microprocessor and
allocating addresses to each memory locations.
16. Explain the execution of the instruction CMA instruction in 8085.

CMA instruction is used to perform 1’s complement of the contents of Accumulator in 8085.
17. What is the function performed by SIM and RIM instruction.

SIM Instruction:
The SIM instruction is used to mask the hardware interrupts RST7.5, RST6.5 and RST5.5. It
is also used to send data through SOD line.
RIM Instruction:
The RIM instruction is used to check whether an interrupt (RST7.5, RST6.5 and RST5.5) is
masked or not. It is also used to read data from SID line.
18. What will be the outcome, in execution of instructions LXI H, 4600H and LHLD 4600H?
When LXI H,4600 is executed, the number 4600 will be loaded into HL register pair.
When LHLD 4600 is executed, the contents of memory location 4600H and 4601H will be
transferred into HL register pair.
19. Explain the function of IN and OUT instructions.

Execution of an IN instruction will transfer one byte of data from an Input device to
Accumulator of microprocessor.
Execution of an OUT instruction will transfer one byte of data from Accumulator of
microprocessor to an Output device.
20. Compare System bus and CPU bus.

Bus is a set of conducting wires in a microprocessor based system, which helps to carry
various information like DATA, ADDRESS and CONTROL signals.
Bus
System Bus CPU Bus
Internal External It will not be
It will be directly
directly connected
connected to CPU
to CPU
There will be
The data and
separate data,
CPU bus System Bus address may be
address & control
multiplexed
buses
© NSS, 2008
21. List the various interrupts in 8085.
HARDWARE interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR (5 Nos)

SOFTWARE interrupts: RST0, RST1, RST2, …… RST7 (8 Nos)
22. What is meant by Vectored and Non-Vectored interrupt?

When an interrupt is accepted, if the processor control branches to a specific address defined
by the manufacturer then the interrupt is called vectored interrupt. All interrupts except
INTR are vectored interrupts.
In Non-vectored interrupt there is no specific address for storing the interrupt service
routine. Hence the interrupted device should give the address of the interrupt service routine.
INTR is a non-vectored interrupt.
23. When the 8085 processor accept hardware interrupt?

The processor keeps on checking the interrupt pins at the second T -state of last Machine
cycle of every instruction.
If the processor finds a valid interrupt signal and if the interrupt is unmasked and enabled
then the processor accepts the interrupt. The acceptance of the interrupt is acknowledged by
sending an INTA signal to the interrupted device.
24. What is masking and why it is required?

Masking is preventing the interrupt from disturbing the current program execution. When
the processor is performing an important job (process) and if the process should not be
interrupted then all the interrupts should be masked or disabled.
In processor with multiple 'interrupts, the lower priority interrupt can be masked so as to
prevent it from interrupting, the execution of interrupt service routine of higher priority
interrupt.
25. When the 8085 processor will disable the interrupt system?
The interrupts of 8085 except TRAP are disabled after anyone of the following operations
1. Executing EI instruction.
2. System or Processor reset.
3. After acceptance of an interrupt.
© NSS, 2008
26. Define T-State.

A T-State is the time period of the one complete cycle of the internal clock signal of the
processor. The time taken to execute a machine cycle is expressed in terms of T-states.
In 8085, if the external clock frequency applied through X1 & X2 pins are 6 MHz; then the
internal clock frequency is 3 MHz (since, Fint = Fext / 2).Therefore, one T-State equals to T =
1/F = 1/3MHz = 0.333µs.
27. What is Processor (machine) cycle? List the various machine cycles with its T-states.
The machine cycles are the basic operations performed by the processor, while instructions
are executed. The time taken for performing each machine cycle is expressed in terms of T-
states.
The various machine cycles are
1. Opcode fetch …………….. - 4/6T
2. Memory Read ……………. - 3T
3. Memory Write ……………. - 3T
4. I/O Read ………………….. - 3T
5. I/O Write …………………. - 3T
6. Interrupt Acknowledge …… - 6 / 12 T
7. Bus Idle …………………… - 2/3T
28. What is the need for timing diagram?

The timing diagram provides information regarding the status of various signals, when a
machine cycle is executed. The knowledge of timing diagram is essential for system
designer to select matched peripheral devices like memories, latches, ports, etc., to form a
microprocessor system.
29. Write an assembly language program to store the contents of the flag register in
memory location 2000H.
PUSH PSW - Stores the contents of Accumulator & Flag register in Stack
POP D - Restores the stored contents of stack to DE register pair
MOV A, E - Move the contents of E register to Accumulator
STA 2000H - Contents of Accumulator is now stored to memory location 2000H
HLT
© NSS, 2008
30. List the various addressing modes in 8085 with two examples in each.
Addressing is the method of specifying the location of data in an instruction.
The different types of addressing modes in 8085 are
a) Direct:
The data is stored in memory and 16 bit address of data in memory location is specified
in the instruction. Eg.: LDA 4500, LHLD 4200
b) Immediate:
The required data for processing is given next to the Opcode, in the instruction itself.
Eg.: MVI A, 55 CPI 64, ADI 0A
c) Register:
The data is placed in a register and the register name is given in the instruction to access
the data. Eg.: MOV A,B ADD B, SUB C
d) Register Indirect:
The data is stored in memory and the 16-bit address of the data location in memory is placed in a
register pair. This register pair holding the 16-bit address is given in the instruction to access the
data. Eg.: LXI, H 4250 MOV A, M
e) Implied:
The data location & the operation to be performed is given in the instruction itself.
Eg.: CMA, RAR, XCHG
31. Compare CALL and JMP instructions.

CALL Instruction:
Execution of a CALL instruction will transfer the program control from existing program to
another program. ie., Sub program specified by the 16-bit address in CALL instruction will
be executed. The called program should have RET – return instruction as its last instruction.
Time taken for its execution is 9 / 18 T.
Main _________ addr16:_________

_________ _________
_________ _________
_________
CALL addr16 _________
_________ _________
_________
_________ RET
© NSS, 2008
JMP Instruction
Execution of a JMP instruction will transfer the program control from one location to
another location within the same program. Time taken for its execution is 7 / 10 T
Main _________
_________
_________
JMP addr16
_________
_________
addr16:_________
_________
32. Write an ALP for time delay using a register pair available in 8085.
Main _________ Delay: LXI D, Data16
_________ loop: NOP ………………………. 4T
_________ NOP ………………………. 4T
NOP ………………………. 4T
CALL Delay DCX D ……………………. 6T
_________ JNZ loop ………………….. 10T
_________ RET
------
The register pair used is DE. 28T
The total time delay made is as follows.
One T-state = 1 / Finternal
Total T-States for delay = Delay time (in µs) / Time period for 1 T-state
T–states (in execution of loop – one time) = 4T + 4T + 4T + 6T + 10T = 28T
∴Data16 = Total T-States in delay program / 28T
33. Explain the Instruction format of 8085.

The 8085 have 74 basic instructions. The
size of 8085 instructions can be either 1 byte,
2 bytes or 3bytes.
1 Byte instruction has Opcode alone.
2 Bytes instructions have 1 byte
Opcode followed by 8 bit data.
3 Bytes instruction have 1 byte
Opcode followed by 16 bit data.
© NSS, 2008
34. Draw and label the flags in flag register of 8085.
35. Draw the flow chart of a counter.
The counter is an arrangement to keep track of a process. This consists of three operations
which are a) count initialization b) decrement count value and c) check whether count value
has reached zero.
The count operation can be either Up-count or Down-count. A Counter is used for repeated
processing, time delay generation, counting of events.
© NSS, 2008
36. Write an 8085 program to generate a time delay of 0.4sec; assuming crystal frequency
as 5MHz.
Internal frequency = 5MHz/2 = 2.5MHZ.
Time for one T-state = 1/ 2.5MHz = 0.4msec.
Number of T-states required for delay = Delay time / Time for 1T-state
= 0.4sec / 0.4msec
= 1 x 106 T-states
Delay program:
LXI B, Count ……………..….… 10T
Loop : MOV A, C …………….............. 4T
ORA B ……………………….… 4T
DCX B …………………….…… 6T
JNZ Loop …………………….… 10T
Total T-states needed = 10T + (Count*24T)

1 x 106 = 10 + (Count x 24)
∴Count = (1000000 – 10) / 24 = 41666.25D ≅ 41666D = A2C2H.
37. Identify the no. of address lines needed for interfacing 8KB memory.
Where, N is number of address lines. ∴The no. of address lines for 8 KB is equal to 13.
38. Why address bus is unidirectional?

The address is an identification number used by the microprocessor to identify or access a
memory location or I / O device. It is an output signal from the processor. Hence the address
bus is unidirectional.
39. How the microprocessor is synchronized with peripherals?

The timing and control unit synchronizes all the microprocessor operations with clock and
generates control signals necessary for communication between the microprocessor and
peripherals.
© NSS, 2008
Unit – II (Peripheral Devices)
8255 – PROGRAMMABLE PERIPHERAL INTERFACE (PPI)
1. What is a programmable peripheral device?

If the functions performed by a peripheral device can be altered or changed by a program
instruction then the peripheral device is called programmable device. Usually the programmable
devices will have control registers. The device can be programmed by sending control word in
the prescribed format to the control register.
2. What is the need for a Port?

The I/O devices are generally slow devices and their timing characteristics do not match with
processor timings. Hence the I/O devices are connected to system bus through the ports.
3. What is handshake port?

Explain the working of a handshake input port and output port.
In handshake port, signals are exchanged between I/O device and port or between port and
processor for checking or informing various condition of the device.
In handshake input operation, the input device will check whether the port is empty or not. If the
port is empty, then the data is loaded into the port. When the port receives the data, it will
inform the processor for read operation. Once the data have been read by the processor, the port
will signal the input device that it is empty. Now the input device can load another data to port
and the above process is repeated.
In handshake output operation, the processor will load a data to port. When the port receives the
data, it will inform the output device to collect the data. Once the output device accepts the data,
the port will inform the processor that it is empty. Now the processor can load another data to
port and the above process is repeated.
4. What are the internal devices of 8255?

The internal devices of 8255 are port-A, port-B, port-C and Control register.
The ports can be programmed for either input or output function in different operating modes.
5. What are the operating modes of port -A 8255?

The port-A of 8255 can be programmed to work in anyone of the following operating modes as
input or output port.
Mode-0 : Simple 1/0 port.
Mode-l : Handshake 1/0 port
Mode-2 : Bidirectional 1/0 port
© NSS, 2008
6. What are the functions performed by port-C of 8255?

1. The port-C pins are used for handshake signals.
2. Port-C can be used as an 8-bit parallel 1/0 port in mode-0.
3. It can be used as two numbers of 4-bit parallel port in mode-0.
4. The individual pins of port-C can be set or reset for various control applications.
7. Draw the control word format for I/O mode.
8. Draw the control word format for BSR (Bit Set Reset) Mode.
© NSS, 2008
8251 – USART:
9. What is baud rate?

The baud rate is the rate at which the serial data is transmitted (expressed as bits per second).
Baud rate is also defined as l/(Tb - time period for a symbol). In some systems, one data bit may
be represented through one symbol. Then, on such occasions, the baud rate and bits/sec are
same.
10. What is USART? What are the functions performed by INTEL 8251A?
The device which can be programmed to perform Synchronous or Asynchronous serial
communication is called USART (Universal Synchronous Asynchronous Receiver Transmitter).
The INTEL 8251A is an example of USART.
The INTEL 825lA is used for serial data transmission or reception either asynchronously or
synchronously. The 8251A can be used to interface MODEM for serial communication through
telephone lines.
11. What is asynchronous data transfer scheme?

In asynchronous data transfer scheme, first the processor sends a request to the device for
read/write operation. Then the processor keeps on polling the status of the device. Once the
device is ready, the processor executes a data transfer instruction to complete the process.
The frame format in Asynchronous data transfer is given below.
Start Parity Stop

Data (8-bits)
Bit Bit Bit(s)
Direction of Data Transfer
12. What is synchronous data transfer scheme?

For synchronous data transfer scheme, the processor does not check the readiness of the device
after a command has been issued for read/write operation. In this scheme, the processor will
request the device to get ready and then read/write to the device immediately after the request.
In some synchronous schemes a small delay is allowed after the request.
Data is sent continuously in blocks either without any time interval or in fixed time intervals.
© NSS, 2008
13. What are the control words of 8251A and what are its functions?
The control words of 8251A are Mode word and Command word. The mode word informs 8251
about the baud rate, character length, parity and stop bits. The command word can be send to
enable the data transmission and reception.
14. What are the functions performed by INTEL 8251A?

The INTEL 825lA is used for converting parallel data to serial or vice versa. The data
transmission or reception can be either asynchronously or synchronously. The 8251A can be
used to interface MODEM and establish serial communication through MODEM over telephone
lines.
15. What is the information that can be obtained from the status word of 8251?
The status word can be read by the CPU to check the readiness of the transmitter or receiver and
to check the character synchronization in synchronous reception. It also provides information
regarding various errors in the data received. The various error conditions that can be checked
from the status word are parity error, overrun error and framing error.
16. What are the different types of errors that can occur in asynchronous serial
communication?
1. Framming Error
2. Over run Error
3. Parity Error
_
17. What is the significance of C/D signal in 8251?
This pin is used to select either Control register for configuring or Data bus buffer for read /
write operations.
8279 – KEYBOARD & DISPLAY CONTROLLER:
18. What are the different scan modes of 8279?

The different scan modes of 8279 are Decoded scan and Encoded scan.
In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
In encoded scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output.
© NSS, 2008
19. What is debouncing?

When a key is pressed, it bounces after a short time. If a key code is generated immediately after
sensing a key actuation, then the processor will generate the same keycode a number of times.
(A key typically bounces for 10 to 20 msec). Hence the processor has to wait for the key
bounces to settle before reading the keycode. This process is called keyboard debouncing.
20. What is the difference in programming the 8279 for encoded scan and decoded scan?
If the 8279 is programmed for decoded scan then the output of scan lines will be decoded output
and if it is programmed for, encoded scan then the output of scan lines will be binary count. In
encoded mode, an external decoder should be used to decode the scan lines.
21. What is scanning in keyboard and what is scan time?

The process of sending a zero to each row of a keyboard matrix and reading the columns for key
actuation is called scanning. The scan time is the time taken by the processor to scan all the
rows one by one starting from first row and coming back to the first row again.
22. What are the tasks involved in keyboard interface?

The tasks involved in keyboard interfacing are sensing a key actuation, debouncing the key and
generating key codes (Decoding the key). These tasks are performed by software if the keyboard
is interfaced through ports and they are performed by hardware if the keyboard is interfaced
through 8279.
23. How a keyboard matrix is formed in keyboard interface using 8279?

The return lines, RLo to RL7 of 8279 are used to form the columns of keyboard matrix. In
decoded scan the scan lines SLo to SL3 of 8279 are used to form the rows of keyboard matrix.
In encoded scan mode, the output lines of external decoder are used as rows of keyboard matrix.
24. What is scanning in display and what is the scan time?

In display devices, the process of sending display codes to 7 –segment LEDs to display the
LEDs one by one is called scanning (or multiplexed display). The scan time is the time taken to
display all the 7-segment LEDs one by one, starting from first LED and coming back to the first
LED again.
25. What is meant by 2-key lockout and N-key rollover?

2-Key Lockout: When two keys are pressed simultaneously, one key pressed first will be
recognized and code will be generated.
N-Key Rollover: When a key is pressed continuously, the same key will be recognized several
times, after each debounce.
© NSS, 2008
26. List the functions performed by 8279.

a. Keyboard scanning.
b. Keyboard debouncing.
c. Keycode generation.
d. Intimating key pressing to CPU through Interrupt.
e. Storing display codes.
f. Output display codes to LED/LCDs.
g. Display refreshing.
ADC / DAC:
27. What are the different types of ADC?

The different types of ADC are successive approximation ADC, counter type ADC flash type
ADC, integrator converters and voltage-to-frequency converters.
28. What is settling or conversion time in DAC?

The time taken by the DAC to convert a given digital data to corresponding analog signal is
called conversion time.
29. What is most commonly employed circuit in DAC?

The most commonly employed circuit in DAC is R/2R ladder network.
30. What are the internal devices of typical DAC?

The internal devices of DAC are R/2R ladder network, an internal latch and Current to Voltage
converting amplifier.
31. What is the significance of address bus A0, A1 & A2 in ADC?

The analog input voltage may be taken for conversion into digital output from eight input
channels. A particular input channel is selected by providing appropriate signals in the three
address buses, A0, A1 & A2.
SERIAL COMMUNICATION STANDARDS:
32. How the RS -232C serial bus is interfaced to TTL logic device?
The RS-232C signal voltage levels are not compatible with TTL logic levels. Hence for
interfacing TTL devices to RS-232C serial bus, level converters are used. The popularly used
level converters are MC 1488 & MC 1489 or MAX 232.
© NSS, 2008
33. What is RS-232C Standard?

The RS232C is a serial bus consisting of a maximum of 25 signals, which are standardized by
EIA (Electronic Industry Association). The first 9 signals are sufficient for most of the serial
data transmission.
34. What is the voltage level used in RS232C standard?

The voltage levels are
Logic LOW (0) : –3V to –15V
Logic HIGH (1) : +3V to +15V
Commonly used voltage levels are +12V (logic HIGH) and –12V (logic LOW).
35. What is the importance of Level converters?

The RS-232C signal levels are not compatible with TTL logic levels. Hence for interfacing TTL
devices, level converters or RS-232C line drivers are employed. The popularly used level
converters are
• MCI488 - TTL to RS232C level converter
• MCI489 - RS232C to TTL level converter
• MAX 232 - Bi-directional level converter.
(Max 232 is equivalent to a combination of MC1488 and MC1489 in single IC)
36. What are two important lines in I2C Standard?

The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Both
lines are pulled high via a resistor [Rp]. Due to its two-wire nature (one clock, one data), it
provides only half-duplex communication.
37. What are the modes of data rate in I2C standard?

Three speed modes are specified: Standard; 100kbps [Bits per Second], Fast mode; 400kbps,
High speed mode 3.4Mbps.
38. What is BPIB?

GPIB stands for General Purpose Interface Bus. It is communication standard developed by
Hewlett Packard, for parallel data transfer between computers and instruments. Its IEEE
standard number is IEEE 488.1. It supports data rate of 1 Mbps with upto maximum of 15
devices.
© NSS, 2008
Unit-III (8086)
1. What are the modes in which 8086 can operate?

The 8086 can operate in two modes and they are minimum (or uniprocessor) mode and
maximum (or multiprocessor) mode.
2. What are the hardware interrupts of 8086?

The interrupts of 8085 are INTR and NMI. The INTR is general maskable interruput and NMI is
non-maskable interrupt.
3. How clock signal is generated in 8086? What is the maximum internal clock frequency of
8086?
The 8086 does not have on-chip clock generation circuit. Hence the clock generator chip, 8284
is connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three for
internal use. The maximum internal clock frequency of8086 is 5MHz.
4. What is pipelined architecture?

In pipelined architecture the processor will have number of functional units and the execution
time of functional units is overlapped. Each functional unit works independently most of the
time.
5. What are the functional units available in 8086 architecture?

The bus interface unit (BIU) and execution unit (EU) are the two functional units available in
8086 processor.
6. List the segment registers of 8086.

The segment registers of 8086 are, Code segment (CS), Data segment (DS), Stack segment (SS)
and Extra segment (ES) registers.
7. What is the difference between segment register and general purpose register?
The segment registers are used to store 16 bit segment base address of the four memory
segments. The general purpose registers are used as the source or destination register during
data transfer and computation, as pointers to memory and as counters.
8. What is queue? How queue is implemented in 8086?

A data structure which can be accessed on the basis of first in first out is called queue. The 8086
has six numbers of 8-bit FIFO registers, which is used for instruction queue.
© NSS, 2008
9. Write the special functions carried by the general purpose registers of 8086.
The special functions carried by the registers of 8086 are the following.
Register Special function

AX 16-bit Accumulator
AL 8-bit Accumulator
BX Base Register
CX Count Register
DX Data Register
10. Write the flags of 8086.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

- - - - O D I T S Z - Ac - P - Cy
The 8086 has nine flags and they are

1. Carry Flag (CF) 6. Overflow Flag (OF)
2. Parity Flag (PF) 7. Trace Flag (TF)
3. Auxiliary carry Flag (AF) 8. Interrupt Flag (IF)
4. Zero Flag (ZF) 9. Direction Flag (DF)
5. Sign Flag (SF)
11. What are processor control bits?

The flags TF, IF and DF of 8086 are used to control the processor operation and so they are
called control bits.
12. Describe the difference between the instructions MOV AX, 2437H and MOV AX,[2437H].
Difference between the instructions MOV AX, 2437H and MOV AX,[2437H] are former
instruction takes 2437 as 16-bit data and latter instruction takes 2437 as 16-bit address.
13. State the function of Direction flag in 8086.

Direction flag is used with string instructions. If DF= 0, the string is processed from its
beginning with the first element having the lowest address. Otherwise, the string is processed
from the high address towards the low address.
14. What happens in 8086 processor, when

a. overflow of sum occurs during addition of signed numbers. (Ans: Ov Flag is Set)
b. overflow of quotient occurs during division operation. (Ans: type0-divide by zero
interrupt is generated).
© NSS, 2008
15. In 8086 processor the code segment contains 4000H and instruction pointer contains
9F20H. Find the memory location addressed by the processor.
Segment address 4000 - 0100 0000 0000 0000

Shifted to left by four bits - 0100 0000 0000 0000 0000
(+) Offset address - 1001 1111 0010 0000
----------------------------------
Physical address - - 0100 1001 1111 0010 0000 = 49F20H
----------------------------------
∴The Calculated Physical address = 49F20H
16. Discuss the functions of the following prefixes: LOCK, ESCAPE

LOCK :
In a multiprocessor system each microprocessor has its own local buses and memory. The
individual microprocessors are connected together by a system bus so that each can access
system resources such as disk drives or memory. Each microprocessor only takes control of the
system bus when it needs to access some system resources.
The LOCK prefix allows a microprocessor to make sure that another processor does not take
control of the system bus while it is in the middle of a critical instruction which uses the system
bus.
ESCAPE:
This instruction is used to pass instructions to a coprocessor such as the 8087 math coprocessor
which shares the address and data bus with an 8086.
17. What are the flag manipulation instructions of 8086?

LAHF : Load AH from low byte of flag register.
SAHF : Store AH to low byte of flag register
PUSHF : Push content of flag to the stack.
POPF : Pop content of stack and load it in the flag register.
18.Give the contents of the flag register after execution of following addition.
0110 0101 1101 0001
+ 0010 0011 0101 1001
---------------------------
1000 1001 0010 1010
-----------------------------------
SF = 1, ZF = 0, PF = 1, CF = 0, AF = 0, OF=1.
© NSS, 2008
19. What are the three groups of signals in 8086?

The 8086 signals are categorized in three groups. They are :
i. The signals having common function in minimum and maximum mode.
ii. The signals having special functions for minimum mode,
iii. The signals having special functions for maximum mode.
20. What are the uses of AD0 – AD15 lines?

These are the time multiplexed memory 15 address and data lines. Address remains on the line
during T I state ,while data is available on the data bus during T2, T3, TW and T4. Here T1, T2,
T3, T4 and Tw are the clock states of a machine cycle. Tw is a wait state. These lines are active
high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.
21. What is the operation of RD signal?

Read signal RD when low, indicates the peripherals that the processor is performing a memory
(or) I/O read operation.
22. What is the function of READY signal?

This is the acknowledgment from the slow devices (or) memory that they have completed the
data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086. The signal is active high.
23.What is the function of INTR signal?

INTR- Interrupt Request: This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request, If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by
resetting he interrupt enable flag. This signal is active high and 1ternally synchronized.
24. What is the operation performed when TEST input pin is low?
If the TEST input goes low, execution will continue, else, the processor remains in an idle state.
The input is synchronized internally during each clock cycle on leading edge of clock.
25. What is the purpose of ALE signal in minimum mode?

ALE -Address Latch Enable: This output signal indicates the availability of the valid address on
the address / data lines, and is connected to latch enable input of latches. This signal is active
high and is never tristated.
© NSS, 2008
26. What is the function of RESET pin?

RESET input causes the processor to terminate the current activity and start execution from
FFFFOH. This signal is active high and must be active for at least four clock cycles. It restarts
execution when the RESET return low. RESET is also internally synchronized.
27. What is the function of DEN signal in minimum mode?

This signal indicates the availability of valid data over the address / data lines. It is used to
enable the Transceivers to separate the data from the multiplexed address / data signal. It is
active from the middle of T2 until the middle of T4 DEN is tristated during hold acknowledge
cycle.
___
28. What is the significance of MX/MN pin in 8086?
The above said pin is used for selecting the mode of the operation of the processor. HIGH in
that pin declares that the system comprises of uni-processor (Minimum Mode) and LOW
declares that the system comprises of multi-processor (Maximum Mode).
29. What are the differences between maximum mode and minimum mode?
30. What is multi micro-processor architecture?

The maximum clock frequency at which a system operate may be considered as one of the
measure of the processor capability of the system. An appropriate system involving several
microprocessors connected using a certain topology may provide high processing capacity. The
study of such a system known as multi micro processor architecture.
© NSS, 2008
31. What is meant by numeric processor?

The numeric processor 8087 is a coprocessor which has been designed to work under the control
of the processor 8086 and offer it additional numeric processing capabilities.
32. Explain the tightly coupled (closely coupled) system.

In a tightly coupled system, the microprocessor (either coprocessor or independent processors)
may share a common clock & bus control logic The two processors in a closely coupled system
may communicate using a common system bus or common memory The microprocessor in a
closely coupled system either uses a status bit in memory / interrupt the host to inform it about
the completion of the task allotted to it.
33. Explain the loosely coupled multiprocessor system.

In a loosely coupled multiprocessor system, each CPU may have its own bus control logic. The
bus arbitration is handled by an external circuit. The loosely coupled system configurations like
LAN and WAN can be spreaded over a large area.
34. Give the advantage of loosely coupled system over the tightly coupled system.
The loosely coupled system has the following advantage over the tightly coupled system,
• More number of CPUs can be added in a loosely coupled system to improve the system
performance.
• The system structure is modular and hence easy to maintain and troubleshoot.
• A fault in a single module does not lead to a complete system breakdown.
• Due to the independent processing modules used in the system, it is more fault -tolerant.
• More suitable to parallel applications due to its modular organization.
35. List the features of 8086.
Features of 8086 are:

• 16-bit Data bus
• Can operate upon 16 bit / 32 bit data.
• 20-bit address bus.
• More memory addressing capability (220 = 1MB)
• 16 bit Flag register with 9 Flags
• Can be operated in Minimum mode and Maximum mode
• It has two stage pipelined architecture
• No internal clock generation
• 40 pin DIP IC - HMOS technology
• Operates on +5V supply voltage
• Has more powerful instruction set
© NSS, 2008
Unit – IV & V: (8051)
1. What is mean by microcontroller?

A device which contains the microprocessor with integrated peripherals like memory, serial
ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC,
DAC is called microcontroller.
CPU ROM RAM

Timers I/O Ports Serial Port
Internal blocks of Microcontroller
2. List the features of 8051.

Features of 8051 are:
• Data size is 8-bit
• Address lines is 16-bit (∴Memory capacity = 216 = 64 KB)
• Memory capacity of On-chip RAM is 128 Bytes
• Memory capacity of On-chip ROM is 4 KB
• Total program memory space is 64KB
• Total data memory space is 64KB
• No. of on-chip Timers is 2
• Four 8-bit I/O Ports
• One full duplex Serial port
• Six Interrupt sources (inclusive of two H/w interrupts – INT0, INT1)
3. What is the significance of DPTR?

DPTR is a 16-bit register which is used as Data Pointer for external data memory. It holds the
16-bit address of the data stored in the external data memory.
This can also be used as two numbers of 8-bit data pointer namely DPH and DPL. The 8-bit data
pointers are used for accessing internal RAM and SFR.
The contents of data pointer are programmable using instructions.
__
4. What is the significance of EA pin?
EA stands for External Access. By applying LOW to this pin, makes 8051 to omit internal 4KB
on-chip ROM and use only external memory for program storage. By applying HIGH to this
pin, makes 8051 to use internal 4KB on-chip ROM along with external memory for program
storage.
© NSS, 2008
5. Compare Microprocessor and Microcontroller.
S.No Microprocessor Microcontroller
1 The functional blocks of a The functional blocks of microcontroller

microprocessor are ALU, registers, includes a Microprocessor, Timers,
timing and control unit. Parallel I/O ports, Serial I/O port, and
internal RAM and ROM memory.
Some microcontrollers have even ADC

and/or DAC on-chip.
2 It involves rapid movement of code & It involves rapid movement of code &
data between µP and external memory. data between memory & CPU inside µC.
Hence MORE instructions are made Hence LESS instructions are available
available for data transfer with for data transfer with external memory.
external memory.
3 µP operates on byte/word data. µC operates on bit/byte data.

Hence, it has LESS bit manipulation Hence, it has MORE bit manipulation
instructions. instructions.
4 A µP based system requires large no. A µC based system can be formed

of peripherals and hence, its PCB will without using additional peripheral ICs.
be LARGE. Hence, its PCB will be SMALL.
5 A µP based system is used for General A µC based system is used for

purpose computing and Data application specific dedicated systems.
processing applications. Eg. Washing machines, Mobile phones,
Microwave oven, Elevators, etc.
6. List the alternate functions of Port3 in 8051.
© NSS, 2008
7. Draw the program memory organization in 8051.
8. Draw the data memory organization in 8051.
9. Define Stack Pointer.

The stack pointer is 8 bit register which points the stack top. It is incremented before data is
stored during PUSH and CALL instructions. After reset of the processor, the SP is 07H.
10. Define Program Counter.

Program counter is a 16 bit register which holds the 16-bit address of the program instruction
currently executed by the processor. PC is automatically incremented after every fetch of
instruction byte from the memory for its execution.
© NSS, 2008
11. What is Program Status Word?

PSW is another name for flag register. It holds various flags, which are useful for the
programmer to test the condition of the result and make decisions. The format of PSW of 8051
microcontroller is shown in fig below.
Program Status Word (Flag Register)
The PSW consists of four math flags and two register bank select bits. The math flags are Carry,
Auxiliary Carry, and Overflow and Parity flags.
The register bank select bits RS1 and RS0 are used to select any one of the four register banks
of the internal RAM. At any instant, the microcontroller can work with (or access) only one
register bank, which is selected by these bits.
12. State the function of RS1 and RS0 bits in the flag register of 8051.
13. List the addressing modes of 8051.

The 8051 has the following types of addressing.
• Immediate Addressing
• Direct Addressing
• Register Addressing
• Register Indirect Addressing
• Implied Addressing
• Relative Addressing
© NSS, 2008
14. List the Special Function Registers (SFRs) :

The SFRs includes 21 internal registers listed in table below. Each register of SFR has one byte
address (between 80H and FFH). Some of the registers are both byte and bit addressable (The
registers whose address ends with 0H or 8H are bit addressable). These registers can be
accessed either by their names or by their 8-bit address in direct addressing mode.
15. Explain why SJMP instruction is used in the place of HLT in 8051?
As we use microcontroller for a dedicated and repetitive application, there will not be a
situation in which the microcontroller is switched ‘ON’ and no program running in it. Hence,
there is no necessity to have HLT instruction in the instruction set of microcontroller.
At the same time, when we want to terminate the execution of a program in 8051, we use
SJMP to make the program execution remain in the same instruction.
Eg. Here: SJMP Here HLT
© NSS, 2008
16. Explain the operation of CJNE instruction.

CJNE stands for Compare and Jump, if Not Equal.
This instruction compares two 8-bit numbers and the program control branches to a specific
location if the numbers are not equal. The branching is done by relative addressing.
The different formats of CJNE instruction are
17. Explain the operation of DJNZ instruction.

DJNZ stands for Decrement and Jump, if Not Zero.
This instruction decrements a 8-bit number stored in a register / memory location, and the
program control branches to a specific location if the resultant number after decrement is not
zero. The branching is done by relative addressing.
The different formats of DJNZ instruction are
18. Justify why the crystal oscillator frequency in 8051 is chosen as 11.0592Mhz.
When an 8051 microcontroller based system is connected to an external device for serial
communication between them, the speed at which the data transfer should take place must be in
standard baud rates such as 4800, 9600, etc.
Only XTAL of 11.0592 Mhz can provide such standard baud rates, after down scaling by 12, by
32 at UART and by a factor set in timer register.
© NSS, 2008
19. Draw the structure of a pin in port 1.
20. Draw the format of TMOD register of 8051.
21. List the modes of Timer in 8051.
The modes of timer in 8051 are chosen with the help of two bits, viz., M0 & M1, in TMOD
register. The different modes of timer are as follows.
M1 M0 Mode Operation of the timer

0 0 0 13 bit timer
0 1 1 16-bit timer
1 0 2 8-bit timer with auto reload
1 1 3 split timer
© NSS, 2008
22. Explain the Timer operation of 8051.
In this mode, the timer register is used to generate the time delay using the clock signal applied
to the processor. An initial count is loaded in the timer register. When the timer is started, the
timer register content gets incremented after every machine cycle. When the timer register
crosses (i.e., overflows) the count FFFFH and goes to 0000H, the timer overflow flag in TCON
register becomes set.
Hence, by loading appropriate value in the timer register, a specific time delay can be generated
using timer. One machine cycle consists of 12 clock signal periods and the delay is equal to
count value loaded * time period of one machine cycle.
23. Draw the format of TCON register of 8051.
© NSS, 2008
24. Draw the format of IE register.
25. Draw the format of IP register.
26. What is the default priority of the interrupts in 8051?
© NSS, 2008
27. Draw the format of SCON register of 8051.
28. What are the modes of asynchronous serial communication in 8051?

The mode of serial communication is decided by two bits SM0 & SM1 in SCON register. The
details of the various modes are described in the table given below.
SM0, SM1 Mode Serial Mode Description Baud rate

00 0 8-bit Shift register FOsc / 12
01 1 8-bit UART Variable
10 2 9-bit UART FOsc / 32 or 64
11 3 9-bit UART Variable
Out of all modes, Mode-1 is commonly used mode for serial data transfer in 8051.
29. What is the significance of C/T bit in TMOD register of 8051?

The C/T bit in the TMOD register is a selector bit for the type of operation we want to perform
in the timer register.
HIGH in that bit indicates Counter operation and LOW in that bit indicates Timer operation.
0 Timer operation
1 Counter operation
30. What is the significance of TRx bit in TCON register of 8051?

TRx bit in the TCON register is used to Start / Stop the timer register for both timer and counter
operation.
© NSS, 2008
31. Draw the format of PCON register in 8051.
32. Explain how baud rate is set in 8051 for serial data transfer using timer register?
Based on the baud rate needed for serial communication, the timer register TH1 is loaded with
values as per the following calculation.
External XTAL oscillator frequency is chosen as 11.0592 MHz is to make the UART output as
28800 Hz, so that the various baud rates are obtained by dividing this common frequency 28800
Hz with different values set in TH1 register.
For an example baud rate of 9600;

Divisor is 03H (because 28800 / 03 = 9600)
∴Value loaded in TH1 register = 00H – 03H = FDH
© NSS, 2008
Following are the sample values loaded in TH1 register for different baud rates.
Hex value loaded in

Baud rate Frequency Divisor
TH1 register
9600 03 FD
4800 06 FA
2400 12 EE
1200 24 DC
General Expression for setting variable baud rates using TH1 register is given below.
|
|
|
33. Write a program using 8051 assembly language to change the data 55H stored in the
lower byte of the data pointer register to AAH using rotate instruction.
MOV DPL, #55H

MOV A, DPL
RL A
Here: SJMP Here
34. Specify the single instruction, which clears the most significant bit of B register of 8051,
without affecting the remaining bits.
Single instruction, which clears the most significant bit of B register of 8051, without affecting
the remaining bits, is CLR B.7
© NSS, 2008
Part-B Questions:
UNIT-I
1. With neat sketch explain the architecture of 8085 Processor

-Block Diagram
-Explanation about all blocks in the block diagram
-Registers Available
2. Draw the Pin Diagram of 8085 and explain the function of various signals.
-Pin Diagram
-Explanation about all signals
3. List the various Instruction available in 8085 processor.

-Data Transfer Instructions
-Arithmetic Instructions
-Logical Instructions
-Branch Instructions
-Machine Control Instructions
4. Explain the Addressing modes in 8085.

- List all addressing modes and explain atleast with one example for each machine cycle.
5. Draw and explain the timing diagram for each machine cycle.
6. Draw the timing diagram for any one Instruction.

- Example: STA 4600
LDA 4500
MVI A, FF
IN C8
7. Programming Exercises.
-Example: a) Write a program to multiply two 8-bit numbers.
b) Write a program to sort an array in ascending order.
-Also refer to the exercises given in chapter 8 of book authored by Ramesh N. Goankar
© NSS, 2008
UNIT - II
1. With neat sketch explain the operation of 8255 PPI.

-Purpose of the IC 8255
-Signal flow diagram with pin description
-Explanation about all the ports available.
-Explanation about the modes of data transfer.
-Internal architecture block diagram
-Explain the working of 8255
-Explain the control word for I/O and BSR mode.
2. With neat sketch explain the operation of 8251.

-Purpose of the IC 8251
-Explanation the types of serial communication.
-Explain the control word for Mode, Command and Status word.
3. With neat sketch explain the operation of Keyboard and display controller 8279.
-List the functions of the IC 8279.
-List the eight command words and shortly brief them.
4. With neat sketch, explain the function of A/D converter.

-A/D conversion principle
-Types of techniques available
-R/2R ladder network & its working
-Typical A/D converter – ADC0801
-Interfacing diagram of ADC with 8085 and its explanation.
5. With neat sketch explain the function of D/A converter.

-D/A conversion principle
-Types of techniques available
-Successive approximation & its working
-Typical D/A converter – DAC0808
-Interfacing diagram of DAC with 8085 and its explanation.
6. Short notes on the following.

-RS232
-I2C
-GPIB
© NSS, 2008
UNIT - III
1. With neat sketch, explain the architecture of 8086 processor.

-Features of 8086
-Architecture block diagram
-Register organization (all registers including Flag register)
-Memory segmentation and Physical address calculation
-Pin Diagram
3. List the various Instruction available in 8086 processor.

-Bit Manipulation Instructions
-String Instructions
-Program Execution Transfer Instructions
-Processor Control Instructions
4. Describe the interrupt system of 8086 processor.
5. Explain the addressing modes of 8086 processor.
6. With neat sketch, explain the architecture of 8086 in minimum mode.

-Block Diagram
7. With neat sketch, explain the architecture of 8086 in maximum mode.

-Block Diagram
© NSS, 2008
UNIT – IV & V:
1. With neat sketch, explain the architecture of 8051 microcontroller.

-Block Diagram
-Pin Diagram
3. List the various Instruction available in 8051 microcontroller.

-Logical Instructions
-Boolean variable Manipulation Instructions
-Program and Machine Control Instructions
4. With neat sketch explain the pin structure of I/O ports.

-Diagram for Port 0 & Port1, 2, 3
-Explanation about all diagrams
5. List the Special Function Registers and explain them briefly.
6. List and explain the addressing modes of 8051.
7. Explain the operation of Timer/counters in 8051.
8. Explain the operation of serial communication in 8051.
9. Explain the interrupt system & its management in 8051.
10. With neat sketch, explain the interfacing of 8051 with external memory.
11. With neat sketch, explain the interfacing of 8051 with Stepper motor.
12. With neat sketch, explain the interfacing of 8051 with LCD display.
13. With neat sketch, explain the interfacing of 8051 with ADC.
14. With neat sketch, explain the interfacing of 8051 with DAC.
15. Programming exercises: Refer to examples given in the text book
© NSS, 2008

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What are machine language and assembly language programs?

What are machine language and assembly language programs?

Why is interfacing needed for I/O devices?

Why is interfacing needed for I/O devices?

EC1303 – Microprocessor & Applications Question Bank

EC1303 – Microprocessor and Applications

2. Why data bus is bi-directional?

3. Why interfacing is needed for I/0 devices?

4. What is data size in a microprocessor?

5. Why EPROM is mapped at the beginning of memory space in 8085 system?

6. What is Tri-state logic?

7. Define Stack and Stack Pointer.

8. Define Program Counter.

9. What is the significance of IO/M pin?

10. State the function of HOLD and HLDA pins in 8085.

11. State the significance of X1 and X2 pins of 8085.

12. What is an Interrupt? How the interrupts are classified?

13. Distinguish I/O mapped I/O and memory mapped I/O.

Memory mapped I/O Standard I/O mapped I/O

14. Explain the concept of demultiplexing AD0-7 lines in 8085?

15. What is memory mapping?

16. Explain the execution of the instruction CMA instruction in 8085.

17. What is the function performed by SIM and RIM instruction.

19. Explain the function of IN and OUT instructions.

20. Compare System bus and CPU bus.

21. List the various interrupts in 8085.

HARDWARE interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR (5 Nos)

22. What is meant by Vectored and Non-Vectored interrupt?

23. When the 8085 processor accept hardware interrupt?

24. What is masking and why it is required?

26. Define T-State.

28. What is the need for timing diagram?

31. Compare CALL and JMP instructions.

Main _________ addr16:_________

∴Data16 = Total T-States in delay program / 28T

33. Explain the Instruction format of 8085.

34. Draw and label the flags in flag register of 8085.

35. Draw the flow chart of a counter.

Total T-states needed = 10T + (Count*24T)

38. Why address bus is unidirectional?

39. How the microprocessor is synchronized with peripherals?

Unit – II (Peripheral Devices)

8255 – PROGRAMMABLE PERIPHERAL INTERFACE (PPI)

1. What is a programmable peripheral device?

2. What is the need for a Port?

3. What is handshake port?

4. What are the internal devices of 8255?

5. What are the operating modes of port -A 8255?

6. What are the functions performed by port-C of 8255?

7. Draw the control word format for I/O mode.

9. What is baud rate?

11. What is asynchronous data transfer scheme?

The frame format in Asynchronous data transfer is given below.

Start Parity Stop

Direction of Data Transfer

12. What is synchronous data transfer scheme?

14. What are the functions performed by INTEL 8251A?

8279 – KEYBOARD & DISPLAY CONTROLLER:

18. What are the different scan modes of 8279?

19. What is debouncing?

Main _ addr16:_