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Output Constraints Rev2

This document discusses output constraints for connecting an FPGA to other devices. It outlines the maximum and minimum clock and data delays that must be met. Specifically: 1) The FPGA output delay constraints are defined by Max_Tco, the latest time data is valid, and Min_Tco, the earliest time new data arrives. 2) When connecting to another device, the FPGA output delays must ensure the receiving device's setup and hold times (Tsu and Th) are met. 3) The output delay constraints are calculated based on the clock and data delays between the devices, to make sure valid data is provided within the receiving device's timing windows.

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jasonkee111
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© Attribution Non-Commercial (BY-NC)
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71 views

Output Constraints Rev2

This document discusses output constraints for connecting an FPGA to other devices. It outlines the maximum and minimum clock and data delays that must be met. Specifically: 1) The FPGA output delay constraints are defined by Max_Tco, the latest time data is valid, and Min_Tco, the earliest time new data arrives. 2) When connecting to another device, the FPGA output delays must ensure the receiving device's setup and hold times (Tsu and Th) are met. 3) The output delay constraints are calculated based on the clock and data delays between the devices, to make sure valid data is provided within the receiving device's timing windows.

Uploaded by

jasonkee111
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Output Constraints from FPGA Spec

CLK
Target CLK delay(max) Other
DATA CLK delay(min)
FPGA Device
DATA delay(max)
DATA delay(min)
Max_Tco Tsu
Min_Tco Th

CLK

Fastest Min_Tco : The earliest time when new data arrives and the data becomes invalid
DATA
Slowest
Max_Tco : The latest time when the data becomes valid

Default setup data required time (launch-to-latch edge)


set_output_delay specifies data required time outside

Then new setup data required time becomes as shown


This must be same as Max_Tco requirement, therefore
Output_delay(max) = Tck – Max_Tco

Default hold data required time (launch-to-latch edge)


set_output_delay specifies data required time outside

Then new hold data required time becomes as shown


This must be same as Min_Tco requirement except for a minus sign, therefore
Output_delay(min) = – Min_Tco
Output Constraints from Other Device Spec

CLK
Target CLK delay(max) Other
DATA CLK delay(min)
FPGA Device
DATA delay(max)
DATA delay(min)
Max_Tco Tsu
Min_Tco Th

CLK
At other device
Fastest
input pin DATA
Slowest

Tsu Th

CLK delay
(max or min) DATA delay As looking from the chart
(max or min) Max_Tco + DATA delay –CLK delay = Tck - Tsu
Min_Tco + DATA delay – CLK delay = Th
CLK
At FPGA Then
Min_Tco
onput pin Fastest Tck - Max_Tco = Tsu + DATA delay - CLK delay
DATA - Min_Tco = -Th + DATA delay - CLK delay
Slowest
Max_Tco
From the result in the previous page
Output_delay(max) = Tsu + DATA delay – CLK delay
Output_delay(min) = -Th + DATA delay – CLK delay

Considering maximum and minimum


Output_delay(max) = Tsu + DATA delay(max) – CLK delay(min)
Output_delay(min) = -Th + DATA delay(min) – CLK delay(max)

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