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Entity And1 Is Port (A, B:in STD - Logic Z:out STD - Logic) End Entity And1 Architecture AN - 1 of AND1 Is Begin Z A and B End An - 1

The document defines the architecture and ports for 7 logic gate entities: AND, XOR, XNOR, OR, NOT, NAND, and NOR. Each entity specifies inputs A and B and output Z, and defines the output Z using the corresponding logic operation.

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Harshit Agarwal
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41 views11 pages

Entity And1 Is Port (A, B:in STD - Logic Z:out STD - Logic) End Entity And1 Architecture AN - 1 of AND1 Is Begin Z A and B End An - 1

The document defines the architecture and ports for 7 logic gate entities: AND, XOR, XNOR, OR, NOT, NAND, and NOR. Each entity specifies inputs A and B and output Z, and defines the output Z using the corresponding logic operation.

Uploaded by

Harshit Agarwal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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ENTITY and1 IS

port(A,B:in std_logic;Z:out std_logic);


END ENTITY and1;
architecture AN_1 of AND1 is
begin
Z<= A and B;
end An_1;

ENTITY xor6 IS
port(A,B:in std_logic;Z:out std_logic);
END ENTITY xor6;
architecture xor_6 of xor6 is
begin
Z<=A xor B;
END xor_6;
ENTITY xnor7 IS
port(A,B:in std_logic;Z:out std_logic);
END ENTITY xnor7;
architecture xnor_7 of xnor7 is
begin
Z<=A xnor B;
END xnor_7;
ENTITY or2 IS
port(A,B: in std_logic;Z:out std_logic);
END ENTITY or2;
architecture or_2 of or2 is
begin
Z<=A or B;
end or_2;
ENTITY not3 IS
port(A:in std_logic;Z:out std_logic);
END ENTITY not3;
architecture not_3 of not3 is
begin
Z<=not A;
END not_3;
ENTITY nand4 IS
port(A,B:in std_logic;Z:out std_logic);
END ENTITY nand4;
architecture nand_4 of nand4 is
begin
Z<=not(A and B);
END nand_4;
ENTITY nor5 IS
port(A,B:in std_logic;Z:out std_logic);
END ENTITY nor5;
architecture nor_5 of nor5 is
begin
Z<=not(A and B);
END nor_5;

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