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RISC and CISC Processor Differences

This PPT gives the differences in between RISC and CISC Processors in detail

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mukesh_sonu
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3K views

RISC and CISC Processor Differences

This PPT gives the differences in between RISC and CISC Processors in detail

Uploaded by

mukesh_sonu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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CISC and RISC architecture Microcontrollers Differences: CISC Processors RISC Processors Complex Instruction Set Computer Reduced Instruction Set Computer When an MCU supports many addressing modes for arithmetic and logical instructions and for memory accesses and data transfer instructions, the MCU is said to of CISC architecture. When an MCU has an instruction set that supports one or two addressing modes for arithmetic and logical instructions and few for memory accesses and data transfer instructions, the MCU is said to of RISC architecture Large number of complex instructions Small number of instructions Instructions are of variable number of bytes Instructions are of fixed number of bytes Instructions take varying amounts of time for execution Instructions take fixed amount of time for execution CISC Processors RISC Processors Emphasis on hardware Emphasis on software CISC provides flexibility in choosing various ways of performing the data transfer and arithmetic and other operations RISC provides no flexibility in choosing the many different ways of performing the data transfer and arithmetic and other operations CISC implements each instruction in a one or more clock cycles resulting in more amount of circuitry and more amount of power dissipation because of its complex instruction set. RISC implements each instruction in a single clock cycle using a distinct hard-wired control at lesser amount of circuitry and lesser amount of power dissipation because of its reduced instruction set. Small amount of cache and very few registers to allow more instruction with memory Large cache and large number of registers to prevent lore interaction with memory Small code sizes Large code sizes Less transistors for memory storage More transistors for memory storage

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