High frequency DPWM controller IC for ac-dc converter

 
 
  

Internal guide
  R.Valarmathi M.E.,
Lecturer,
Department of EEE,
DSEC,
Perambalur. By
K.Senthilnathan
D.Balamurali
S.Appandairaj
S.Raja
ABSTRACT
This paper deals with the implementation of high frequency digitally controlled PWM
pulse generation using VLSI technology. The rapid progress in motor control and
microelectronics has made the DC drives a major field of interest. The existing control
schemes have many drawbacks. In phase angle control, extinction angle control,
symmetrical angle control schemes, the lowest order harmonic is third, and is very
difficult to filter out the lower order harmonics. Also input power factor of phase
controlled converter decreases as firing angle increases. Lower order harmonics can be
eliminated or reduced by selecting type of modulation for pulse width and number of
pulses per half cycles. Though lower order harmonics are eliminated by PWM control
schemes. The analog or microprocessor based PWM control schemes have their own
drawbacks. The analog control methods have various drawbacks such as temperature
drift, ageing effect of components, more components count for the system, necessity for
making physical parts and susceptibility to electro magnetic interference.
Some digital control methods also had many drawbacks. Firstly, discrete
principally RAM and counter are combined together switching times are calculated and
stored in RAM, resulting in simple circuit. However the frequency of motor speed is
difficult to control and is not compact. Secondly, to obtain higher switching frequency, a
fast processor such as DSP is necessary resulting in high cost and also a long time is
required to develop software in a new processor structure. Moreover, processor control by
software is not suitable for switching circuit, which generates lot of noise, resulting in
high risk of collapse.
Dynamic and ever progressing change in VLSI has radically affected the design
process cheap, reliable and time saving. Moreover the FPGA based design is more
reliable than microprocessor based system and they don’t need any control software.
A single chip for the implementation of modulator, rather than a system consisting
of microprocessor and external memory, as many advantage including less use of
power and space, short design time, greater speed, reliability and less electromagnetic
interference.
The conventional implementation of this technique, which had some shortcoming.
In the existing control scheme work, a DPWM converter is implemented using power
transistor. This converter is tested with R and DC motor load. The AC input is rectified
using uncontrolled bridge rectifier; power transistors obtain DPWM. High frequency
DPWM controller IC designed by VLSI technology generates driving pulses required
by power transistors. The average value of output voltage is varied by varying width of
pulses, which is done by varying width of driving pulses from DPWM. Since firing
angle is not changed in this method, power factor is maintained unity.
PWM CONVERTER FED D.C DRIVE
Block diagram of DPWM converter fed D.C drive using minimum hardware is shown in
fig 8.1. This circuit has minimum hardware since it uses single transistor. The PWM
pulses are generated using a high frequency DPWM controller IC. The pulses from
high frequency DPWM controller IC cannot drive the transistor directly. These pulses
are amplified using a driver circuit. The amplified pulses are given to he base of power
transistor. The DPWM converter converts fixed A.C in to Variable D.C. This variable
D.C voltage is given to the D.C motor. Varying the width of the pulses varies the speed
of the D.C motor.

PWM CONVERTER FED DC DRIVE CIRCUIT

 REFERENCE CLOCK SYSTEM CLOCK

RING COUNTER
2-bit
counter
Q0 Q1 Q2 Q3 Out

nc bit
0 1 2 Comparator
nd 3 MUX
4:1
1
Out

nc

nc bit
Q
nc Comparator
2
S

OUT
00H
 EXPERT SYSTEMS AND SOLUTIONS
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Call For Research Projects Final
year students of B.E in EEE, ECE,
EI, M.E (Power Systems), M.E
(Applied Electronics), M.E (Power
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Ph.D Electrical and Electronics.
Students can assemble their hardware in our
Research labs. Experts will be guiding the
projects.
POWER SUPPLY CIRCUIT
5 V POWER SUPPLY
The power supply used for driver circuit is shown in fig 8.4 is given to
PAL22V10 IC, BUFFER & TIMER. The 230 V ac supply is stepped down to 6v
using 230 V / 6 v transformer. The low voltage a.c is rectified using a diode
rectifier. The output of rectifier is filtered using 1000-microfarad electrolyte
capacitor filter. This unregulated D.C is given to the voltage regulator 7805. The
output of 7805 is given to another filter capacitor 1 microfarad to reduce the ripple.
A bleeder resistor is connected in parallel with capacitor. This provides a path for
the capacitor to discharge.

POWER SUPPLY (+5V)

12 V POWER SUPPLY
The power supply used for driver circuit is shown in fig 8.5 is given to
optocoupler. The 230 V ac supply is stepped down to 15v using 230 V / 15 v
transformer. The low voltage a.c is rectified using a diode rectifier. The
output of rectifier is filtered using 1000-microfarad electrolyte capacitor filter.
This unregulated D.C is given to the voltage regulator 7812. The output of
7805 is given to another filter capacitor 1 microfarad to reduce the ripple. A
bleeder resistor is connected in parallel with capacitor. This provides a path
for the capacitor to discharge.

POWER SUPPLY (+12V)

BASE DRIVE CIRCUIT
The pulses from the high frequency DPWM controller IC are given to the optocoupler
through the buffer 74244.The clock to PAL22VT10 IC is given through 555 TIMER
This buffer provides protection for high frequency DPWM controller IC. The 68-ohm
resistance in the input side of optocoupler reduces current drawn by optocoupler.
The opto coupler provides isolation between power circuit and control circuit. When a
pulse is applied to the input of MCT2E, the LED conducts. Light falls on the base of
transistor and the transistor conducts. When the transistor in the opto coupler
conducts, the input voltage to the transistor T2 is made zero. T2 does not conduct
and the output of T2 is high.
When the input to the MCT2E is low, the diode does not conduct. The potentiometer
does not conduct. The input to the transistor T2 is made high. Transistor T2
conducts and the output is low. Thus the output f driver circuit is in phase with input.
 24 VCC (5 V)
CLK 1
J2
2
10k
20
3 VCC (5 V)
10k
Gref
10k 4 1
18 2 68 ohm
5 18
10k
PAL22V10 74LS244
6
RESET
0
10

12
GND

J3

GND 1 8

6.6 K
2 7
+12V
3
IC555 1k
6
CLK
0.1uf
4 5 0 MCT2E 10k
VCC 0.1uf
0 220 ohm
0

TO GATE
LIbrary IEEE;
use ieee.std_logic_1164.all;
entity dpwm is
Port (clk,reset:in std_logic;
Din:in std_logic_vector(3 downto 0);
Ct:inout std_logic);
End;
Architecture x of dpwm is
Component ringcounter
Port(clk, reset:in std_logic;
q:out std_logic_vector(3 downto 0);
end component;
component counter
Port(clk, reset:in std_logic;
q:inout std_logic_vector(1 downto 0);
end component
component comparator
port(a,b:in std_logic_vector(1 downto 0);
DOUT: out std_logic);
End component;
Component mux41
Port(a,b,c,d:in std_logic;
S:in std_logic_vector(1 downto 0);
Y:out std_logic);
End component;
Component rsff
Port(r,s,clk:in std_logic;
Q:inout std_logic);
End component;
Signal ringout:std_logic_vector(3 downto 0);
Signal muxout:std_logic;
Signal counterout,gnd:std_logic_vector(1 downto 0);
Signal comp1 out,comp2out:std_logic;
Signal reset1,set1:std_logic;
Begin
Ring:ringcounter port map(clk,reset,ringout);
Mux:mux41 port
Map(ringout(3), ringout(2), ringout(1), ringout(0),din(1 downto 0),muxout);
Counter1:counter port map(ringout(3),reset,counterout);
Compar1:comparator port map(counterout,din(3downto 2),comp1 out);
Compar2:comparator port map(counterout,gnd,comp2out);
Rsff:rsff port map(reset,set1,clk,ct);
Gnd<=”00”;
Reset1<=comp1out and muxout;
Set1<=ring out(3) and comp2out;
End;
 CONCULSION
 
This paper describes as complete controller IC
for high frequency AC/DC switching converter.
Novel controller architecture and configuration of
the key building block: the digital pulse-width
modulator is introduced to meet the requirements of
high speed dynamic response, tight output voltage
regulation and programmability without external
passive components. The DPWM has 4-bit
resolution and generates the switching frequency of
1 MHZ and a system clock frequency of 4 MHZ. The
complete chip design is based in hardware
description language (HDL).
The hybrid digital PWM circuit was simulated using
PSPICE and the output waveforms for the various
values of duty ratio are obtained. The simulated
DPWM output was applied to the AC-DC converter
with Resistive and Permanent Magnet DC motor load.
The speed of Permanent Magnet DC motor was varied
by varying the width of the pulses. The converter
implemented in this project has better power factor
since it uses symmetric PWM. Driver circuit and
DPWM converter are initially tested on a breadboard.
Later they are fabricated using a printed circuit board
(PCB).
 BIBLIOGRAPHY
 
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