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Transmission line effects are evident in all interconnections, but are more pronounced with devices possessing extremely fast rise and fall times. Delays or ringing along an interconnection, can cause unpredictable behavior. To minimize these events, additional care is required during the design of interconnections and termination.
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0% found this document useful (0 votes)
513 views69 pagesPCB Layout AN1051
Transmission line effects are evident in all interconnections, but are more pronounced with devices possessing extremely fast rise and fall times. Delays or ringing along an interconnection, can cause unpredictable behavior. To minimize these events, additional care is required during the design of interconnections and termination.
Uploaded by
bourby68Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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/ 69
MOTOROLA
Order this document
by ANIOS10
= SEMICONDUCTOR EEE
AN1051
— ©MOTOROLA INC., 1990
APPLICATION NOTE
TRANSMISSION LINE EFFECTS IN PCB
APPLICATIONS
A thorough digital design must transcend the "1" and "0" scope of strictly digital
considerations and venture into the traditionally analog world of transmission
lines. The effects of transmission lines are evident in all interconnections.
However, with the advent of devices possessing extremely fast rise and fall
times, these effects are more pronounced. The results of these effects, delays or
ringing along an interconnection, can cause unpredictable behavior. To minimize
these undesirable events, additional care is required during the design of
interconnections and termination. Figure 1 illustrates stair-stepping delays and
ringing.
The basic guideline used to determine if a printed circuit board (PCB) trace
needs to be examined for transmission line effects is that, if the smaller of the
driving device's tise or fall time is less than the twice the time required for a
switching wave to propagate through a trace, the transmission line effects are not
masked during the rise or fall time of the driving device. The factor of twice the
propagation time through a trace is not as arbitrary as it might seem; this factor
allows for the switching wave to be transmitted from the driving device, travel
through the PCB trace to the receiving device, reflect off the receiving device,
and return to the driving device. With this guideline established, the rise and fall
times and propagation times of a:trace become paramount in transmission line
analysis.
1. QUAD DESIGN's Transmission Line Calculator (TLC) 1985 Del Norte Rd. Camarilo, Caltornia
2. PARASITIC PARAMETERS is a registered trademark of Paciic Numerix Comp, 1200 Prospect St, Suite 300, La
‘Jolla, California.
1. Viewsim System Development (View/SD) isa subset of Workview Series ll which are registered trademarks of
\Viewlogic Systems inc, 293 Boston Post Rd. West, Marlborough, MA.
44. Green field i a registered trademark of Quantic Laboratories inc. Suite 200, 281 McDermot Ave., Winnipeg,
Canada,
5, Saberis a tradematk of Analogy, ne. 9205 S. W. Gemini Drive, Beaverton, Oregon and CADAT is a trademark of
RacalRedac, Inc, 100 Wychott Ave., Mahwah, New Jersey.
@) mororo.a mm
AN1051 ‘STAR STEPPING VOLTAGE WAVE
eceno:
= ioeAL GATE nour
Au atte nrsr mom ce race
Figure 1. Transmission Line Effects
‘As devices have been designed to run at higher speeds, their rise and fall times
have diminished. Propagation times through a PCB trace depend on the PCB
materials and the routing and loading of the trace. Conventional PCB materials
have not changed to sustain performance at the faster rise and fall times of
driving devices. This situation, as well as the fact that routing and loading can
vary greatly from trace to trace, has elevated the importance of investigating PCB
traces for transmission line effects.
The lumped capacitive load model shown in many data books is not sufficient for
detailed examination of transmission line effects in PCBs.
Two key elements to consider in transmission line analysis are the PCB traces’
characteristic impedance, Zo, and propagation delay, Tpp. The characteristic
impedance is the ratio of the voltage to the current in a circuit; thus it describes
what current and voltage parameters the driving and receiving devices connected
to a trace will experience. Mismatches in impedance between segments of the
trace and devices connected to the trace cause reflections, which result in
performance-limiting ringing and delays. The propagation delay is important
ANtO51/D MOTOROLA because it predicts if the effects of these reflections will be hidden during the rise
and fall times of a circuit. To account for these elements, more detailed hand-
e analysis methods, such as the lattice diagram and the Bergeron plot methods
presented in this document, are required. The lattice diagram requires the
following information: the rise and fall times of the driving devices, the output
impedances of the driving devices, the input impedances of the receiving
devices, and the capacitive loading values of the receiving devices. The
Bergeron plot method requires the output voltage versus current curves for the
driving devices and the input voltage versus current curves and the capacitive
loading values of the receiving devices. A complete study also requires
information about the PCB, such as the dielectric constant for the insulating
materials used, the cross-section trace geometry, and the trace length.
Transmission line effects need to be examined prior to final PCB layout. Not all
scenarios can be improved by adding termination. Occasionally, a trace with
several segments and loads will have too much delay associated with the
reflections and the characteristics of the driving device. In some cases,
termination may absorb the reflections, but in other cases, it may overload the
driving device, preventing it trom operating at its prescribed rate. Hand analysis
helps to highlight potential problem areas and can provide general rules used in
PCB layout once a system designer gains expertise with an output driver type,
but, to account for complex routing patterns, computer programs with
a transmission line and layout emphasis provide more detailed solutions than hand
analysis. More comprehensive solutions using computer programs that provide
graphical analysis are available, such as QUAD DESIGN's TLCt, Pacific
Numerix's PARASITIC EXTRACTOR™®, Viewlogic's Viewsim/SD™3, Quantic
Laboratories Greenfield@* and Rlacal-Redac’s Saber/CADAT™S, The Simulation
Program with integrated Circuit Emphasis (SPICE) also has provisions tor
transmission line analysis. it is important that the designer knows basic
transmission line theory to evaluate these programs’ limitations and features.
Motorola understands the importance and complexity of this issue and is
developing a solution that includes a tutorial on basic transmission line theory, a
set of enhanced input and output electrical characteristics , and the release of
models of the M88000 Family output buffers for use in transmission line
programs. Solutions, from hand-analysis methods to results of transmission line
programs, are useful in predicting transmission fine effects, which need to be
correlated with the hardware to verify the basic observations from the Paper
calculations and simulations. This application note serves as the tutorial
tended to emphasize the importance of understanding transmission line effects
in the application of PCBs. It covers the following subjects: PCB traces as
transmission lines, transmission line analysis methods, termination schemes,
general notes concerning layout, and examples for loaded waves and
MOTOROLA ANt051/D 3 termination. Discussions of termination and examples are presented for exercise
only and do not imply behavior of any Motorola devices. e
Some techniques promoted in this document have been in practice over 20
years in ECL designs. The premier source for ECL designs is the MECL Design
Handbook ( see Reference 1). Since the techniques presented there are
designed for ECL applications, they do not automatically work for all CMOS and
TTL applications. CMOS and TTL outputs are different from ECL outputs in that i
ECL has similar output impedances for the low-to-high-driven and the high-to-
low-driven cases; whereas, CMOS and TTL output impedances often vary by an
order of magnitude from their low-to-high-driven and high-to-low-driven cases.
Also, many CMOS and TTL outputs drive 5-V swings in less than 2 ns (some |
actually reach down into the 500-ps range for rise and fall times). ECL outputs :
drive a 1-V swing in roughly 1 ns. These differences require close examination
of the basic, entrenched termination schemes for ECL before they are used with
CMOS and TTL.
PCB TRACES
The following paragraphs discuss PCB traces as transmission lines, the four
trace types, and device loading.
PCB Traces as Transmission Lines e
rather than a lumped load is the relationship between the driving device's rise or
fall time and the propagation delay of the signal through the trace. Specifically.
the trace should be analyzed as a transmission line if
1
‘The key factor in determining if a trace should be treated as a transmission line |
2x Tpp x trace length > Tr or Tr (minimum of the two) (1) !
Tp is the unit propagation delay of the signal, usually given in nanoseconds per
unit length. Tp and Tr are the rise and fall times of the driving device. Note that
the fastest of the rise and fall time values should be used. The high-level
interpretation of Equation (1) is that, if the round-trip time for the switching
waveform is greater than the rise oF fall time of the driving device, the settling of
the transmission line effects are not hidden during the rise and fall times of the
driving device.
PCB traces have resistive, inductive, and capacitive effects distributed
throughout them. These characteristics are used to develop transmission fine '
models, and the basic means for approximating the distributed effects
4 AN1051/—D MOTOROLA lumped load model. Figure 2 shows a transmission line modeled in lumped,
constant terms, using the intrinsic resistance, inductance, and capacitance of a
trace. This representation is reduced to a transmission line circuit that uses the
characteristic impedance (Zo) and propagation delay (Tpp) values to describe
the trace. Referring to Figure 2, the effects of the intrinsic resistance (fq) on Zo
are negligible, leaving only the effects of Lo and Co to be considered in the
calculation of the characteristic impedance and propagation delay per unit length:
Zo = V(Lo/Co) 2 @)
Tpp = V(Lo x Co)nsslength (3)
Roto Fo te Fo le
Zeoaee
4) Hes
nove
sane = SWITCHING VOLTAGE SUPPLY
_Zecmct “OUTPUT MPEOANCE OF VOLTAGE SUPPLY
Ro -LNTAINSIC RESISTANCE OF TRANSMESION UNE
UG INTAINSIC NOUCTANCE OF TRANSMESSION UNE
(65 = INTANSIC CAPACITANCE OF TRANSMISSION UNE
2oap “LOAD IMPEDANCE
Figure 2. Lumped Transmission Line Approximation
If the intrinsic capacitance and inductance are known, they can be used in
Equations (2) and (3). Usually, the propagation delay and the characteristic
impedance ate calculated from cross-section geometries and dielectric materials
used in the PCB traces. The equations using the geometries and materials are
based on Equations (2) and (3), but then require considerations that treat the
traces as if they are operating in the transverse electromagnetic mode. If more
information is desired for that derivation, see Reference 1. For this discussion,
only multilayer board types (microstrip and stripline) are analyzed. For wire-
wrapped applications, consult Reference 1
MOTOROLA ‘AN1051/D 5 ¥
e
PCB Trace Types
The two basic trace types are the microstrip and stripline. Each type can be
modified to form derivatives such as the embedded microstrip and the dual
stripline configurations. Cross-section diagrams of these trace types are shown
in Figure 3.
6 AN1051/0 MOTOROLA
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-1017 URE ‘INO PONERGROUNO PUNE
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{b) Embedded Microstrip
Figure 3. PCB Trace Types (Sheet 1 of 3)
MOTOROLA ANI051/0 LILLIE
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Figure 3. PCB Trace Types (Sheet 2 of 3)
AN1051/D MOTOROLA. MOTOROLA
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Figure 3. PCB Trace Types (Sheet 3 of 3)
AN1051/D The most frequently used types of dielectrics are glass-epoxy (G-10) and one of,
its derivatives (FR-4). The dielectric constants (or more specifically in relation to
its derivation, relative permittivity) for G-10 can be characterized generally as 4.5,
to 5.0, and the dielectric constant for FR-4 can be characterized as 4.5 to 5.2,
although PCB manufacturers have seen values as low as 4.0 for both constants.
The dielectric constant varies with frequency; Reference 2 provides a discussion
on this. Trace dimensions can vary greatly depending on their applications. For
multilayer boards with overall board thicknesses of 0.062 in, dielectric
thicknesses of layers range from 0.005-0.016 in. Controlled impedance boards,
in which all traces on the board have characteristic impedances within a specified
range of several ohms, usually have the controlled characteristic impedance in
the range of 55-75 ohms due to constraints on manufacturing PCB traces, such
as maximum dielectric thicknesses and minimum trace widths.
Device Loading
10
When a trace is loaded with devices, inductance and capacitance from the
devices add to the trace's inductance and capacitance. Figure 4 illustrates the
loading down the line. This loading alters propagation delay and characteristic
impedance values as shown in Equations (4) and (5):
Teo! = Ten x ¥1+(Cp/ Co) nsiength 4
Zo! = Zo/ Vix{Cp/ Co) 2 6)
where Cp is the distributed capacitance of the receiving devices (i.e, total load
‘capacitancertrace length) and Co is intrinsic capacitance of the trace. Sockets
and vias also add to the distributed capacitance (sockets ~ 2 pF and vias ~ 0.3-
0.8 pF). Since Tpp = VLoxCo and Zo = VLo/Co, Co can be calculated as
follow:
Co = 1000 x (Tpp / Zo) pF/length (6)
This loaded propagation delay value must be used when deciding whether a
trace should be considered a transmission line (2 x Tpp’ x trace length > TR or
Tr).
AN1051/—0 MOTOROLA Voyr = NOLTAGE SOURCE, Voy AND Vox 1 ~ RECEIVING END OF TRACE
2p OUTPUT MPEDANCE OF DANG DEMICE 2g = LOADED CHARACTERSTICMPEDAACE
2, = LOAD MPEDANCE (59, “REFLECTED VOLTAGE aT Lo#D
vgs ICIDENT YOLTAGE {AN; “ERECTED VOLTAGE AT DANG DEVICE
‘alg MEDENT CURRENT ‘it REFLECTED CURRENT ATLOAD
"A= ORV END OF TRACE Bl “REFLECTED CURRENT AT RING Dec
(@) Transmission Line Representation with Zo’ and Load Resistance
> Zo’, then the reflected wave is positive; if Z, of Zp
<< Zo’, then the reflected wave is negative. See Figure 5(a) for this
representation of the lattice diagram.
The two basic types of transmission line effects are ringing and stair-stepped
switching events. When CMOS and TTL devices are the receiving devices
because they have large input impedances (p, = 1), indicating that the full
incident wave from the driving device is reflected back to the driving device. The
ringing or stair-stepping events depend on pg which is calculated from the driving
device's output impedance and the trace's loaded characteristic impedance.
Specifically, whan p, = 1, ringing is caused when the loaded characteristic
impedance is greater than the driving device's output impedance, resulting in a
negative source reflection coefficient and a large initial voltage step; stair-
AN10517D MOTOROLA stepping is present when the loaded characteristic impedance is less than the
driving device's output impedance, resulting in a positive source reflection
coefficient and a small initial voltage step. Some CMOS or TTL devices have
grossly differant output impedances for the low-to-high-driven and high-to-low-
driven states, which produce ringing in high-to-low switching and stair-stepping
delays in low-to-high switching. Termination often reduces ringing while
increasing the stair-stepping, requiring the designer to choose which effect is
worse and to terminate appropriately. Examples 3-5 in APPENDIX A
TRANSMISSION LINE EXAMPLES illustrate the effects of loading and
termination for transmission line effects.
This derivation of the lattice diagram methed illustrates several details concerning
transmission line effects. If the load impedance matches the loaded
characteristic impedance, there are no reflections after the incident wave arrives
at the load, which is the goal of most termination schemes. Also, this derivation
uses a single transmission line with discontinuities at the load and driving device
only. Often, a loaded trace connected to several devices is approximated in this
manner rather than using a separate discontinuity for each device input. This
approximate transmission line representation is accurate if the stubs off the main
trace are very short (< 1 in) or if the trace is laid out using a daisy-chain tormat. 1
the designer is not afraid of a lattice diagram that looks like random molecules
bouncing off various surfaces, then the nonapproximate method is
straightforward, because the derivation for reflection coefficients at each
discontinuity is identical to the derivation of the reflection coefficients at the
driving device and receiving device. An example of this multiple discontinuity
situation is shown on page 222 of Reference 1. Reference 2 provides an
explanation of different layout and loading configurations.
The detailed mathematical representation of the lattice diagram is described as
follows:
V(t) = AVo(t) x { Ult- Te) + pL x Uft - Tpp(2l - X)] +
PL X Pg X Ult- Trp(2! + X)] + pr? x ps x Ult - Tpp(4! - X)] + (9)
2.2 x pg? x Ult- Tep(4l + X)] +...) + VINITIAL,
wher
AVo{t) = voltage at driving device from the voltage divider equation
AVott)
Vout x [Zo' / (Zo' + Zp))
MOTOROLA ‘AN1051/0 15 where AVour is the voltage output swing of the driving device, Zp is the output
impedance of the driving device, and Zo’ is the loaded characteristic impedance
of the PCB trace.
Tpo = propagation delay of the line
U() = unit step function
t = length of trace
x = any point along the trace
pL = load reflection coefficient
Ps = source reflection coefficient
ViniTiaL = quiescent voltage throughout the trace prior to switching
The derivation of this representation is found on page 123 of Reference 1. The
simplified representation, complete with equations, is given in Figure 5(a), which
shows how to compute the voltages at the driving and receiving ends of a
transmission line using reflection coefficients. The vertical line on the left
represents the starting position (X = 0) of the incident wave (driving device);
whereas, the vertical line on the right represents the end position (X ~ L) of the
incident wave and the point of the first reflected wave (receiving device). The
voltages and currents at each endpoint are equal to the voltages and currents
flowing into and out of them. The time required to travel the length of the
transmission line (PCB trace) is equal to Tpo’, which are the units of the vertical
scale. Units of length are used for the horizontal scale.
ANTO51/D MOTOROLA Vee Nee
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os a
NOTE: p and p, ae relecton cotciens and Vary. iste steady-state volage pir tthe switching ofthe
‘die Each TD a propagation Seay Trg) cwaton, A and Bindcat the diving and recotng enc
‘ofthe race, respecte,
(@) Lattice Diagram
Figure 5. Lattice Diagram Representation (Sheet 1 of 2)
MOTOROLA AN1051/D 7 8
poececeecnee
4
epee ra vera terrae eee rote Oates
PROPAGATION DELAYS (ns)
LEceNw:
= = = VOLTAGE Ar oan DEVICE
— votTace aT RECEWRNG DEVE
(b) Voltage Versus Time Plat
Figure 5. Lattice Diagram Representations (Sheet 2 of 2)
The lattice diagram method does make an important assumption in that unless
the Zp and Z; are specifically given by a data sheet, they have to be calculated
‘over the particular voltage of interest. Not all devices behave linearly over the
range of interest. For instance, it a high-to-low transition is to be analyzed,
Votllot is used to calculate Zp for the driving device; for a low-to-high transition,
Vow/lon is used. Frequently, these voltage and current values are given as test
conditions or worst-case numbers in a device's specification and do not represent
the typical or best-case performance of the device. It is also difficult to find input
voltage and current curves, but they are usually approximated by using Schottky
diode clamps for CMOS and TTL devices. If the device does not respond linearly
and the Vour/lour curves for the driving device and if the Vin/Iin curves for the
receiving device are available, then the Bergeron plot method is advised.
The lattice diagram is translated into a voltage versus time plot to show the
response at each end of the transmission line (see Figure 5(b)). The time
required for each voltage wave to travel through the trace is Tro’; therefore, cach
AN1051/ MOTOROLA voltage level is plotted versus Tpp’ directly from the lattice diagram. In general,
a the voltage changes at the driving device at time 2n x Tpp’; the voltage changes
at the receiving device at time (2n + 1) x Tpp’.
Bergeron Plot
The Bergeron plot provides the same basic information as the lattice diagram
(voltage and current versus time) but with fewer calculations. It relies on a
graphic means of describing the reflections on the trace.
The current versus voltage curves for the devices connected to the trace and the
loaded characteristic impedance of the trace itself are required for this method.
‘The axes are the voltage and current ranges for the driving device and receiving
device. The curves plotted on the graph are the Vou/loH and VoL/lot of the
driving device and the Vin/liy of the receiving device. See Figure 6 for a basic
representation.
MOTOROLA AN1051/D 9 29
Yt
en ulescen Pont
a
vous
= ° 7 x0
(CURRENT)
NOTE: Vouica a Vouon are cutput cures forthe diving device: Villy # the MPU eUve for
‘he receiv Seve,
Figure 6. Bergeron Plot
‘The starting point for a transition depends on the quiescent values of the circuit,
which are determined by the intersections of the output curves of the driving
device with the input curves of the receiving device. These points are the voltage
and current values to which the circuit settles in a stable high or low state prior to
the transition. In tracking either a high-to-low or a low-to-high transition, a line of
slope + Zo’ is drawn between the curves. The means for calculating Zo’ is
presented in Equation (5).
For the low-to-high transition, the first line is drawn starting at the logic low
quiescent point (intersection of Volo. and Vin/lin) and has a slope of +Zo' (see
Figure 7). The line ends at the Vou/lox line, with the intersection indicating the
AN1051/0 MOTOROLA voltage and current values at the output of the driving device and the input of the
transmission line.
vous
20D ° aw 100 “0
(CURRENT ay
NOTE: Vovog and Vo oy are ouput cures forthe drving device: Vly isthe input curve or the recevng
eves, and 2g i he loaded characte impedance of the vace
Figure 7. Bergeron Plot with Transitions
‘The second line drawn has a -Zo' slope from this second intersection point to the
Vin/lin line. This point indicates the current and voltage at the input of the
receiving device and the end of the transmission line after one propagation delay
since the signal has traveled one trace length.
The third line is drawn from this point to the Von/lo# line at a slope of +Zo’. This
Point is the voltage and current at the driving device after two propagation delays
since the signal is reflected back to the driving device from the receiving device.
MOTOROLA, ‘ANIO51/D 2 The fourth line on the plot has a slope of -Zo' and ends at the Vin/lin. This
procedure continues until the logic-high quiescent point is reached.
The high-to-low transition is handled similarly. The starting point is at the logic-
high quiescent point. The first line has a -Zo' slope drawn to tne VoL/loL ne.
‘The second line has a +Zo' slope drawn from the intersection to the Vin/In line.
In either case, intersection points that fie on a VoHlloH oF Vow/lot line are values,
at the driving device; those on the Viv/ki line are values at the receiving device.
The Bergeron plot results are easily transferred to a voltage versus time plot .
The first intersection in the plot gives voltage at time To, which is the instant that
the driving device switches. The second intersection marks the voltage and
current at the receiving device, which occurs at time T; (Tpp’ after To}. The next
change at the driving device occurs at 2Tpp’. In general, the voltage switches at
the driving device at time 2n x Tpp’; whereas, the voltage switches at the
receiving device at time (2n + 1) x Tpp'. The two graphs can be superimposed if
desired, See Figure 5(b) from the lattice diagram illustration.
Basic Bergeron plot exercises are shown in Examples 6 and 7 (see APPENDIX
A TRANSMISSION LINE EXAMPLES). Examples 8-10 (see APPENDIX A
‘TRANSMISSION LINE EXAMPLES) step through series and parallel termination
results for various values.
TERMINATIONS
To dissipate the undesired effects of unmatched traces and loads, termination of
traces may be utilized. No standard termination works universally due to the
complexities of layout geometries, power considerations, component count, and
other factors that are discussed in the following paragraphs. In some cases, a
combination of these schemes works best. In cases in which a driving device is
overloaded, termination adds to the loading of the circuit, further degrading the
performance. When the effects of transmission lines rather than overloaded
driving devices are dominant, termination may improve performance.
Five of the most fraquently used terminations are as follows:
Series Termination Resistor
Parallel Termination Resistor
Thevenin Network
RC Network
5. Diode Network
eee
22 AN1051/0 MOTOROLA Figure 8 and Table 1 provide a synopsis of these implementations.
s 3 - Z 2
oe
snes Pres
“v
t 2 . E 3
oo
rT
oo
even fc newer
7
>>
bo0e
Notes:
1. A-civing device; 8 rosivng device
2, Termination near A shoud be atthe crvng device's output, and tose near B should be te coking device's input
Figure 8. Termination Types
MOTOROLA ANO51/D Table 1. Termination Types and Their Properties
Termination | Added | Delay | Power
va Mate | ey, | meguirea | Parts Values ‘Comments
Series 7 Yes Tow [Rg Zo". Rp | SBE NOSE MaraIA
Parallel 7 ‘Sma | High ReZo | Panes Consumin
Theverin 2 | Smat | Heh | Roaxzo | ManPowertoroMOs
RENetwore | 2 Sma [“Wedum | RaZo\_ | ones Banawain and
C =300 pF cea
Diode 2 | Smat [tow = Tita Unsertoct
Diodes
The series termination resistor is preferred when the load is lumped at the end of
the trace, when the driving device's output impedance (Zp) is less than the
loaded characteristic impedance of the trace (Z'), or when a minimum number
gf components is required. It is placed near the driving device, and its value is
equal to (Zo' - Zp). When the series resistance and output impedance equal Zo’,
as prescribed, the voltage wave is split evenly, causing half of the voltage to be
transmitted to the receiving device. A receiving device with a very high input
impedance sees the full waveform immediately (due to the reflection at its end of
the trace), but the driving device does not see the full waveform until 2 x Trp’
(see Example 4). Because devices often have different output impedance values
for their high and low cases, choosing a series resistance value is not always
straightforward.
Parallel Termination Resistor
24
‘The parallel termination resistor utilizes a single resistor whose value equals Zo’
tied to ground, VCC, or +3 V. It adds some delay because the RC time-constant
effects of the trace are increased when the termination resistance is included.
Its major disadvantage is that it dissipates much de power since its value is small
(60-150 ohms). Examples 5 and 6 illustrate these considerations concerning
parallel termination,
AN1051/D MOTOROLA 9
Thevenin Network
The Thevenin network connects one resistor to ground and a second resistor to
Vee. Te avoid cotting of the voltage at a point between the high and low logic
levels that causes reduced noise margins, careful consideration of the ratio of
resistors is required. This technique works well with TTL families, but care is
required when using CMOS devices because the switching voltage is at 50% of
the waveform. A balanced level near the threshold causes greater power
dissipation and potential crossings of the threshold, resulting in unreliable output
Because this method serves as a pullup and a pulldown termination
it works well for clock signals.
RC Network
The RC network performs well in CMOS and TTL systems. The resistor serves
to match the impedance of the trace; the capacitor holds the de signal
‘component, allowing the ac current to flow to the ground during the switching of
logic states. Some delay is presented, but the power dissipation is much less
than the parallel scheme. The resistor equals Zo’, and the capacitor is very small
(200-600 pF). Their RC time constant must be greater than twice the loaded line
propagation delay. This scheme is highly recommended for buses that have
similar layouts for all lines (and similar Zos) because RC termination networks
are available in single-in-line packages (SIPs), which require much less space
than a two-discrete-component solution.
Diode Network
The diode termination network is used frequently for termination on differential
networks. It limits overshoot to approximately 1 V and has low power dissipation,
but the diodes' response at the switching frequency needs to be verified. An
important observation is that the energy is not absorbed in this method.
‘Overshoot is limited at each receiver that has these diodes at their inputs, but the
overall energy is not absorbed as it is in the resistive terminations; thus,
reflections occur throughout the trace
MISCELLANEOUS FACTORS
Supply voltage, temperature, processes, crosstalk, and layout are factors
affecting PCBs. The following paragraphs describe the factors involved.
MOTOROLA AN051/ 25 Supply Voltage
The supply voltage to the devices affects their rise and fall times. Specifically, a
highor cupply voltage creates taster rise and fall times because the output
transistors are being driven by a higher-than-nominal voltage.
Temperature
Temperature alters the performance of the output devices. A higher temperature
adds to CMOS devices’ propagation delay times, siowing the rise and fall times.
Process
‘The best-case and worst-case processes can have a large effect on the devices.
Generally, best-case factors speed up the switching, and worst-case factors
delay the switching. Since devices with best-case processes have faster rise and
fall times, they may cause more transmission line situations than typical devices
and become the worst-case devices for system designers.
Crosstalk
To reduce transmission line effects, the most compact layout with short traces is
advised. However, traces that run close to each other for several inches are
suspect to crosstalk problems. To avoid this problem, increased spacing or
shielding between traces must be implemented. Increasing space between
traces is difficult in dense layouts, which causes crosstalk to be another
complicated issue. References 1, 7, 8, and 9 discuss this subject in detail.
Layout
The following general comments relate to PCB layout and components:
1. Evenly distributed devices along a trace are preferred to lumped loads
because there are fewer large disvuntinuilies in impedances.
2. Avoid stubs and T's in layout for critical signals, which cause impedance
discontinuities. A daisy-chain method is preferred.
3. Sockets and vias add small amounts of capacitance (less than 2 pF and
0.5 pF, respectively). This amount can be added into calculations for
distributed capacitance, if desired.
26 AN1051/D MOTOROLA 9
4, One package type of the future is tape-automated bonding (TAB). The pin
orientation and package size require less interconnect area, potentially
reducing trace lengths and transmission line effects. Another method
used for layout is the multichip module, which mounts several devices
together on silicon substrates to reduce interconnect area.
5. Although exotic materials are available, they are not normally used in
digital PCB construction. Generally, they have lower dielectric constants,
meaning their traces have smaller propagation delays. Reference 10
provides a list of these materials.
6. Controlled-impedance PCBs give a predictable environment for
transmission line behavior. They can be expensive, but they are
recommended for high-performance or prototype applications.
7. Bidirectional signals often use parallel, RC, or Thevenin terminations at
both ends of the PCB trace.
Multiwire configurations for PCBs have applications in this high-speed
world of digital designs. They have lower dielectric constants, providing
faster unloaded propagation delay times.
9. A detailed means of accounting for all types of signal integrity issues is
described in Reference 11. It focuses on noise budgets that examine
powerdrops and tolerances throughout a system
TIME-DOMAIN REFLECTOMETER
Reference 1 promotes a means of lab verification using a time-domain
reflectometer (TDR), which is basically a step generator that stimulates a PCB
trace for an oscilloscope display to monitor. The TDR is recommended for
designers who desire to observe transmission lines on a PCB. Because it has a
1-V swing and uses an unpopulated PCB, some expertise is necessary to
translate the resuits to the CMOS and TTL world.
CONCLUSION
PCB layout is not trivial. A poor layout can prevent a weil-simulated conventional
design from working properly. With devices achieving faster rise and fall times
and PCB materials not improving, the transmission line effects must be resolved,
usually by using terminations. This solution involves more components and more
power consumed by the printed circuit assembly, but it provides improved
pertormance and greater rellability.
MOTOROLA AN1051/0 7 The discussions presented in this document are designed to give a background
into transmis
line effects. To fully understand these effects, predicted results,
whether from hand analysis or computer-aided programs, need to be correlated
with actual hardware. This complete investigation reduces the unpredictability
associated with transmission line effects.
REFERENCES
10.
W.
Blood, William R., MECL System Design Handbook, Motorola Inc.,1983.
IPC-D-317., Design Guidelines for Electronic Packaging Utilizing High-
Speed Techniques, Lincolnwood, ll: 1989
Seshadri, S. R., Fundamentals of Transmission Lines and Electromagnetic
Fields, Reading, MA: Addison-Wesley Publishing Co., Inc., 1971
Morris, Robert L. and Miller, John R., Designing with TTL Integrated Circuits,
New York, NY: McGraw-Hill Book Company, 1971.
Stehlin, Robert A., “Bergeron Plots Predict Delays in Iligh-Speed TTL
Circuits,” EDN, vol. 41, no. 22, Nov. 1984, pp. 293-298.
Singleton, Robert S., "No Need to Juggle Equations to Find Reflection~-Just
Draw Three Lines,” Electronics, vol. 41, no. 22 Oct. 1968, pp. 93-99.
‘Motorola FACT Data, Motorola Inc., 1988.
Wakeman, Larry, “Transmnission-Line Effects Influence High-Speed CMOS,”
EDN, vol. 29, no. 12, June, 1984, pp. 171-177.
DeFalco, John A., "Reflection and Crosstalk in Logic Circuit
Interconnections,” IEEE Spectrum, vol. 7, no. 7, July 1970, pp. 44-50.
Ritchey, Lee W., “Controlled Impedance PCB Design’, Printed Circuit
Design, vol. 6, no. 6, June/July.1989, pp. 23-28; (Errata, vol. 6, no.8, Aug.
1989, pp 78 ).
Tummala and Kymaszewski, Microelectronics Packaging Handbook, NY,
NY: Van Nostrand Reinhold, 1989.
AN1051/D MOTOROLA q
9
ADDITIONAL READING
1:
MOTOROLA
Pace, Charles, "Terminate Bus Lines to Avoid Overshoot and Ringing,” EDN,
vol. 22, no. 10, Sept. 17, 1987, pp. 227-34.
Burton, Edward, "Transmission-Line Methods Aid Memory-Board Design”,
Electronic Design, vol. 36, no. 27, Dec. 1988, pp. 87-91.
Cutler, R. D., "Your Logic Simulation Is Only As Good As Your Board
Layout,” VLSI Systems Design, vol. 8, no. 8, July 1987, pp. 40-42.
Royle, Dave, “Designer's Guide to Transmission Lines and
Interconnections,” EDN, vol. 33, no. 13, June 23, 1988, pp. 131-160.
AN1051/ 29 APPENDIX A
? TRANSMISSION LINE EXAMPLES
EXAMPLE 1: LOADED MICROSTRIP
An MC68030 with 3-ns rise and fall times drives a unidirectional 4-in surtace
microstrip trace with six devices (e.g., FAST family) distributed along the trace
Is termination necessary for transmission line effects?
Microstrip Geometry
Given as W = 0.010 in, T = 0.002 in, H = 0.012 in, and ER = 4.7.
Calculate Characteristic Impedance and Propagation Delay:
Using the surface microstrip equations in Figure 3(a):
oe n(x) 87 x nfS28 x12
=o" 0-8xW+T) * ere aat 0.8 x 10 + 3)
69.49
Tpp = 1.017 x V.475 x Ep + 0.67 = 1.73 nsift = 0.144 nsfin
Consider Loading
Cp is the distributed capacitance per length of the load, which is the total input
capacitance of the receiving devices divided by the length of the trace. The
loading of each device is given in its specifications For this case, each C, = 7
PF. Since there are six devices distributed along the 4-in trace, Cp = 6 x
Ci/Trace Length = 42 pF/4 in = 10.5 pF/in.
Cos the intrinsic capacitance of the trace. Co = Tpo/Zo = 0.0250 nFit =
25.0 pFitt = 2.08 prin.
Teo’ = Trp x V1 + 10.5/2.08 = 4.26 ns/ft. This is the new one-way propagation
time for the signal from the MC68030.
J
MOTOROLA AN1051/D At If 2x Tpp’ x Trace Length < Ta or Tr, then the ringing and other transmission
line effects are masked during the rise and fall times, and no termination will be
needed.
2x Tpp' x Trace Length = 2 x 4.25 nsitt x 1/3 ft = 2.83 ns.
Tr and Tr = 3 ns; since 2.83 < 3, no termination is required, but this is a
marginal case. Note that, if the guideline promoted by some device
manufacturers of 3 x Tpp' x Trace Length is used, then termination would be
required.
For comparison, if a 69-Q stripline was used instead of a 69-2 microstrip, would
termination be required?
Tpp = 1.017 x VER = 2.20 nsitt.
Co=Tpp/Zo = 35 pFit = 2.91 pFiin.
Cp is same as above
10.5 pFiin)
Teo’ = Te x V1 + CpiCo = 4.72 nsitt.
2x Tpp' x Trace Length = 2 x 4.72 nsift x 1/3 ft = 3.14 ns.
The rise and fall times are 3 ns. Since 3.14 > 3 ns, termination is needed for the
69-Q stripline case.
In comparison, note that Co is greater for the stripline, which tends to lessen the
effect of loading in the Tpp’ equation. However, the unloaded Tpp is
substantially greater for the stripline than the microstrip, and this factor prevents
the transmission line effects from being masked during the rise and fall times,
according to these equations. Notice that the unloaded propagation delay
calculations depend only on Ep, the dielectric constant, and not on the trace
geometries.
‘AN1O51/D MOTOROLA EXAMPLE 2: LOADED STRIPLINE
a ‘An MC88100 with rise and fall times of 2 ns drives four MC88200s distributed
over an 8-in stripline trace.
Stripline Geometry
Assume a stripline with B = 0.020 in, W = 0.006 in, T = 0.0014 in, and E,= 4.6.
From Figure 3(¢), the equations for Zo and Tpp for a stripline are:
teOu tT 4xB
70= fe, *i0.67RW x (0.8 + Ti}
60 4x20
fae inf O7eX6x (08> rae} =50.79
Tpp = 1.017 x VER = 2.18 nsift = 0.182 nsiin.
Calculate the intrinsic capacitance of the trace:
Co = Tpp/Zo = 0.043 nFift = 43.0 pF/tt = 3.58 pFiin.
Consider Loading
Each MC88200 has a capacitive load of 15 pF. The total load is 60 pF for the
four MC88200e. Cp is the distributed load per length for the trace: Cp ~ 60 pF/
8 in =7.5 pFiin
Tpo' = Teo x V1 + CoCo = 2.18 x V1 + 7.50/3.58 = 3.84 ns/t.
Transmission Line Effects
2x Tpp' x Trace Length < Tr or Tr is the condition of interest.
2 x 3.84 ns/ft x 2/3 ft = 5.10 ns. Since this is not less than Tr or Tr (2 ns),
termination is recommended to absorb transmission lines effects.
Look at a 0.7-2 microstrip line loaded similarly.
Tpp = 1.017 x ¥0.475En + 0.67 = 1.72 nsitt.
MOTOROLA AN1051/D ey Co = Tpo/Zo = 2.83 pFiin.
Teo! = Ten x V1 + CoCo = 3.29 nsitt.
Is this a transmission ine? 2 x Tpp’ x Traca Length = 2 x 3.29 ns/ft x 2/3 ft = 4.38
ns. Since this is greater than Tp or Tr, termination is recommended.
For a trace this long, the rise and fall times are too fast to handle without
termination. Trace length does not directly figure into the calculations for Tpp or
Zo, but it is an important factor in the relationship that determines if a trace is a
transmission line.
As AN1051/D. MOTOROLA EXAMPLE 3: LATTICE DIAGRAM
é Chip A is driving an 8-in 90-Q stripline trace on a glass-epoxy PCB (Er = 4.7)
loaded with four devices (chip 8) of 15:pF load capacitance each. Chip A has
an output low impedance of 20 2 and an output high Impedance of 120.92. Chip
B has a very large input impedance (100 kO). Examine voltages at each end of
the trace by using a lattice diagram.
Calculate Zo' and Tpp’
20'=Zo/ V1 + Cp/Co
Tro = Teo x V1 + Cp/Co
Cp = (4 devices x (15 pF/device)) / 8 in of trace = 7.5 pFiin.
To calculate Co, first calculate Tpp for a stripline of ER = 4.7 using the equations
in Figure 3(c). Tpp = 2.20 nsit.
Calculate intrinsic capacitance: Co = Tep/Zo = 2.04 pFiin.
1.6 2. and Tpo
Inserting the Co and Co values yields: Zo’ 76 nit
The following procedure is outlined in LATTICE DIAGRAM (see Figure 5(a)).
Switching Levels
VoH = 4.75 V, VoL = 0.25 V.
Output High to Output Low
AVout = Vrinat - ViniTiaL = Vow - Vox = -4.50 V.
Use Zp = 20 © because the final value is the driven low case.
The voltage divider at the driving end of the trace for Zp = 20 Q and Zo' = 41.6.2
gives: AVo = AVour x mee = 3.04,
MOTOROLA AN1051/0 ee Calculate Reflection Coefficients
= Z0-Zo" _20- 41.6 |
Pg= Zp Zor 20+ 41.6 095!
Zu =Zo' _ 100k - 41.6
PL= Zi + Zor” 100k + 41.6 ~ | (0-999)
The voltages and currents down the trace are modified proportionally with the
reflection coefficients. ViniTiat. = VoH = 4.75 V.
Vo = Vo + Vinurrial = 1.71 V.
V1 =AVo x (1 +p.) + Vinmiat = -1.33 V.
V2 = AV x pL Xx (1+ Pg) + Vo = -0.261 V.
V3 = AVo x pL x Pg x (1 +91) +Vi = 0.803 V.
Va = AVo x p12 X pg x (1 + pg) + V2 = 0.490 V.
V5 = AVo x py2 x Pg? x (1+ pi) + V3 = 0.058 V.
Ve = AV0 x p12 x pe2x (1+ pg) + Va = 0.188 V.
V/ = AVo x pL2x pg x (1+ py) + V5 = 0.319 V.
From Figure 5(a), Veiwat is calculated:
Vena = AVourx z-2hg5 + Visa. =-45x FOC nag + 475 = 0.251 V.
Notice that the voltages are settling towards 0.251 V, which is the final value in
this transition.
The voltage versus time plots are shown in Figure A-1:
AN1051/D MOTOROLA 1
’ ee |
+ | 5 i
et} gy |
eT g 1
7 t
at
i
at
| errereeny
rroscaTouoe rrercsonTENsie
(a) Driving Device {b) Receiving Device
Figure A-1. Example 3 Unterminated High-to-Low Switching Results
Output Low to Output High
f Vout = Veinat - ViniTiat = Von Vo. = 4.50 V.
For this case, Zp = 120 Q, since the final state is the high-driving state.
The voltage divider at the driving end of the trace for Zp = 120 Q and Zo’
= Zo
= 41.8 Qgives: AVo = AVOUI XZ 6°§ Zp = VEY.
Calculate Reflection Coefficients
_Zp- Zo" _ 120 - 41.6
°S=Zp + Zo’ 120 + 41.6
= 0.485
Z-ZoQ' _ 100k - 41
PL™ Zo + Zo ~ 100k + 41.6
The voltages and currents down the trace are modified proportionally with the
rellection coefficients. The initial voltage is the logic-low state = 0.25 V.
MOTOROLA AN1051/0 AT Vo = AVo + VinimiaL = 1.41 V.
V4 = AVo x (1 + py) + ViniTiaL =2.57 V.
Ve ~ AVo x pL (14 9g) + Vo = 3 1
V3 = AVo x PX Pg X (1 +p.) + V1 = 3.69 V.
Vg = AVo x p2 x pg x (1 + pg) + Vo= 3.96 V.
Vs = AVo x py? x pg? x (1 + py) + Va = 4.23 V.
Ve = AVo x pi? x pg? x (1 + pg) + Va = 4.36 V.
V7 = AVo x p.3 x pg3x (1 +p.) +VE= 4.50 V.
zy 100k
Veal = Vout x ze 75 + Vinal = 45x TOK + Bo +025=4.75V.
In thie case, the voltage creeps up toward the final value of 4.75 V. The ringing *
effects are not as severe as the high-to-low case, but the high-voltage value is,
not reached until several propagation delays have transpired. The stair-
stepping occurs because the loaded characteristic impedance is lower than the
output impedance of the driving device. In the first case, ringing occurs
because the output impedance of the driving device is lower than the loaded
characteristic impedance of the trace.
The voltage versus lime plots are shown in Figure A-2.
AN1051/D MOTOROLA iy ee nn pO eee ee Jee ee
7 oT RD ow 7 ee
PACEAGATIN LAYS) PROPAGATION DELAYS (rs
{a) Driving Device (b) Receiving Device
Figure A-2. Example 3 Unterminated Low-to-High Switching Results
MOTOROLA AN1051/0 Ao EXAMPLE 4: LATTICE DIAGRAM WITH SERIES TERMINATION
‘The conditions are the same as Example 3. A series termination resistor of 25
Q is inserted to reduce ringing in the high-to-low switching state. The lattice
diagram analysis for both states is performed to show the series termination
tradeoffs in this situation.
Series Termination
For series termination, a resistor is placed in series at the driving device's
output, altering the output impedance value used in the calculations.
Zp' = Zp + Ag, where Rg is the series resistor and Zy' is the new output
impedance value used in calculations,
Output-High to Output-Low Switching
Choose Rs = 25 Q. Now Zp = Zp + Rs = 25 +20 = 452.
Zo! remains the same (41.6 Q).
Recalculate ps
Zp-Zp' _ 45 - 41.6
PS=Zpe Zo 7454 41.6 = 0.0393
Zy-Zo' 100k - 41.6.
9L= 24 Zur" 100k + 41.6 ~ 1 (=0.999)
Calculate Voltages
‘Output voltage levels are Vox = 4.75 V, Voi = 0.25 V.
For the high-to-low case, AVout = Veinat - Vinmiat = Vou - Vou = -4.5 V.
The voltage divider at the driving end of the trace yields
AVo = AVour x “2.16 V.
eco
Zo" +Zp=
The voltages and currents down the trace are modified proportionally with the
reflection coefficients. Use initial voltage of high case (= 4.75 V).
A10 ANIO51/0 MOTOROLA Vo = AVo + ViniriaL = 2.59 V-
V4 = AVo x (1 + py) + VinrmiaL = 0.429 V.
V2 = SVo x py x (14 ps) + Vo = R44 V.
Va = AVo x py X pg x (1 + py) + V1 = 0.259 V.
Va = AVo x p12 x pg x (1 + Pg) + Vo= 0.256 V.
Vs = AVo x p_2 x pg? x (1+ pL) + Vs = 0.252 V.
Vo = AVo x p3 x pg2 x (1+ pg) + Va = 0.252 V.
V7 = AVo x p_3 x pg3 x (1+ py) + Vs = 0.252 V.
The termination reduces the ringing as the voltage settles to its final voltage
level of 0.252 V. It is important to note that the first waveform (Vo) is a halt-
voltage waveform. This places the output in the region between logic levels in
which noise on the trace may cause receiving devices lu swilch unpredictably,
but only for a short time (2 x Tp). Also, the devices at the receiving end of
trace see the full waveform after one propagation delay; whereas, the driving
device (and devices near it) see it after two propagation delays.
The voltage versus time plots are shown in Figure A-3:
MOTOROLA AN1051/D Att vous
1
1
1
gs 1
nae 8 1
| 1
1
‘| 1
1
=
eee es ree [ee vr eee
Tosa ears ose TH ere Hvar ne ae
PROPAGATION DELAYS PROPAGATION DELAYS)
(a) Driving De (b) Receiving Device
Figure A-3. Example 4 Series Terminated High-to-Low Switching Results
This is a good fix for the ringing in the high-to-low switching event. To get a
complete idea of the impact of the series resistor, the low-to-high event must be
examined.
Output-Low to Output-High Switching
AVouT = VFiNAL - VINITIAL = VoH - Voi = 4.5 V.
For this case, Z, Zp + Rs = 120 2 + 25 Q = 145 Q, since the final state is the
high-driving state and Zox = 120 9.
The voltage divider at the driving end of the trace for Zp’ = 145 Q and Zo!
Z
= 41.6 Qyields: AV9 = AVOUT x 75°75 = 1.00 V.
Calculate Reflection Coefficients
45 = 41.6
Zp-Zo'
45 + 41.6
Zp + Zo
PL= Zpe Zo'= 100k + 41.6 ~ 1 (-0.999)
= 0.554
AN1081/D MOTOROLA ‘The voltages and currents down the trace are modified proportionally with the
reflection coefficients. The initial voltage is the logic-low state = 0.25 V.
Vo = AVo + ViniTIAL = 1.25 V.
V4 = AVo x (1 + pi) + VINITIAL = 2.25 V.
V2= AVo x p_ x (1+ pg) + Vo = 2.81 V.
Vg = AVo x p X Pg X (1 +P) + V1 = 3.37 V.
Va = AVo x 2 pg x (1 + Dg) + Vo= 3.67 V.
V5 = AVo x py? x pg? x (1+ py) + Va = 3.98 V.
Ve = AVo x p,3 x pg? x (1+ Pg) + V4 = 4.15 V.
ee 100k
Veal = AVOUT x Zp Zp + VINMAL = 45% 799K 4 145 t025=4.74V.
The series termination exaggerates the low-to-high stair-stepping from the
unterminated state because the output impedance of the driving device is larger
than the unterminated state (Zp’ = 145 ; Zp = 120 9), which is exaggerated
when the termination is added. This illustrates one of the sequences involved
in terminating lines—one undesirable effect is reduced while another is
exaggerated.
‘The voltage versus time plots are shown in Figure A-4:
MOTOROLA AN1051/0 A138 yours
ee
Tare ere sera senre Teg
PROPAGATION DELAYS (es) ‘PROPAGATION DELAYS es)
[eee [ae (senna [entree |
7 NR fe Sm
(a) Driving Device (b) Receiving Device
Figure A-. Example 4 Series Terminated Low-to-High Switching Results
cory AN1051/D MOTOROLA EXAMPLE 5: LATTICE DIAGRAM WITH PARALLEL TERMINATION
¢ ‘The trace characteristics are identical to the previous two examples. Now a
parallel resistor is placed at the end of the trace to absorb the energy of the
Switching wave. This implementation also represents the ac switching events
that occur when a RC network is not changed when the voltage initially
‘switches.
In the parallel termination scheme, a resistor of value Zo’ is placed at the
receiving device's end of the trace. Since Zo’ = 41.6 ©, choose Z,' = 40.2.
Output High to Output Low
Zp = 20 Qin the low-driving case. Zo’
1.6 2.
Recalculate Reflection Coefficients
Zp-Zo' _20- 41.6
PS=2p 4 Zo'~20 + 41.6 ~ 0-951
_2u+Zo' 40-416 _
PL= ZF Zo" 740+ 47.6 = 00196
This is the same source reflection coefficient as the unterminated case. The
change in reflection coefficients due to the parallel termination is seen in py:
Calculate Voltages
‘AVouT = Veinat - ViniTiat = VoL - Vox = -4.5 V.
The voltage divider at the driving end of the trace gives:
A uO ue naa Loni
V9 = AVOUT x FSS 7p 45K a7 4 BO = OF.
Using Vinrriat = 4.75 V, the voltages are:
Vo = AVo + Vinimiat = 1.71 V.
V4 = AVo x (1 + py) + Vina = 1.65 V.
Ve=
Vo x pL x (1+ Pg) + Vo = 1.67 V.
MOTOROLA AN1O51/D Vg = AVo x py x Pg X (1 +p) + V1 = 1.67 V.
The effect of driving the line low is not achieved because of the relationship
between Zp and Zi’. The final value depends on the voltage divider at the load
whwre ZL is the value of the parallel impedance of the tormination recictor and
the load impedance. Since the termination resistor (Rr) is much smaller than
the load impedance (Rr = 40 ©, 2, = 100 kQ), it is effectively the parallel
impedance value. (Recall calculations for parallel resistance from circuit theory:
+ Bx Zn
ZU sR z= 400).
Veal = AVour 7 At ZS + VINA =-45x Gg ag $475 =1.75V
Most driving devices can drive to the low-logic state because the output
impedance of the driving device changes as additional current is pumped into
the circuit. With the nondynamic impedances used in the lattice diagram
method, the final output low value is not reached, which is a limitation of this
hand-analysis method.
For illustration of the parallel method, choose a larger 2.’ that allows the final
‘output low value to be reached. For this case, choose Z1' = 300 2. Check final
Zz 300
voltage: VeInaL = AVOUT XZ y Zp + VINITIAL = "45309420 +475 =
0.531 V. This is an acceptable final voltage because it is less than the
maximum input logic-low level (0.8 V).
Recalculate Reflection Coefficients
_Zp-Zo' _20- 41.6
PS= Zp + Zo" 204 41.6
=-0.351
The voltage divider at the dnving end ot the trace yields
e eee ann
Vo = AVOUT x 754 Zp = 304V.
Using Vinrriat = 4.75 V, the voltages at each end are:
Vo
Vo + VinrmiaL = 1.71 V.
At6 AN1051/0 MOTOROLA ~
vouts
V4 = AVo x (1 + p,) + ViviTiaL = -0.588 V.
V2 = Vo x px (1+ ps) + Vo = 0.218 V.
V3 = AVO x pL x pg (1 + pL) + V1 = 0.828 V.
Va = AVo x p,2 x pig X (1 + Pig) + Vax 0.614 V.
Vs = AVo x p,2 x ps2 x (1+ py) + Vo = 0.453 V.
Ve = AVo x py 3x pg? x (1+ pg) + V4 = 0.509 V.
V7 = AVo x pL3 x pg3 x (1+ py) + V5 = 0.552 V.
The voltage versus time plots are shown in Figure A-5:
poco
se ene ek enone fa ey Ua
oh eo ow % 6 7 ooh Roe ow oS we
PROPAGATION DELAYS rs) PROPAGATION DELAYS (1)
(a) Driving Device (b) Receiving Device
Figure A-5. Example 5 Parallel Terminated High-to-Low Switching Results
As shown earlier, the final voltage is 0.531. In this case, notice that the first
voltage (Vo = 1.71 V) at the driving device falls in the intermediate zone
between logic states because Zo’ and Zp are close in value (41.6 and 20.0 0's,
respectively), similarly to the unterminated case. The ringing is reduced at the
MOTOROLA AN1051/0 ANT load but still exists. As with the series termination, this reduces the ringing in
the high-to-low-switching event. The low-to-high-switching event must be
examined, too, @
Output-Low to Output-High Switching
AVour = VrINAL- VinmmaL = VoH - Vot = 4.5 V.
For this case, Zp = 120 9, since the final state is the high-driving state. The
voltage divider at the driving end of the trace for Zp = 120 @ and Zo' = 41.6 2:
No * Wourx gare ge = 18V.
Zo +Z
Calculate Reflection Coefficients
Zp-Zo' _120- 41.6
Ps=ZyeZo7 120+ 41.6 = 0485
Zi -Zo" _300_41.6
PL= Zp + Zo’ ~ 300 + 41.6
= 0.756
‘The initial voltage is the logic-low state = 0.25 V.
Vo = AVo + VinTiaL = 1.41 V. 6
V4 = AVo x (1 + py) + Vinias. = 2.29 V.
Ve = AVo x px (1+ pg) + Vo=2.71V.
Vg = AVo x PL x Pg x (1 + pL) +V1 = 3.04 V.
Va= AVo x p,2 x pg X (1 + pg) + V2= 3.19 V.
V5 = AVo x pL? x pg? x (14 py) + Va = 3.31 V
Zz 300
Vena = AVourx zh zp AVINMAL = 45%359 4 729 +025 = 346 V.
‘The voltage versus time plots are shown in Figure A-6:
AB AN1051/D MOTOROLA vous
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PROPAGATION DELAYS (os), PROPAGATION DELAYS (ns)
(a) Driving Device (0) Receiving Device
Figure A-6. Example 5 Parallel Terminated Low-to-High Switching Results
The final voltage predicted (3.46 V) is not the final output high voltage desired
(4.75 V), but itis the new quiescent value, assuming the driving device does not
supply additional current. Since the output impedance of the driving device is
greater than the loaded characteristic impedance, stair-stepping occurs during
the switching. Any additional load exaggerates the stair-stepping, which is the
case when either parallel or series termination is added.
‘The major drawback with the parallel method of termination is the current
consumed. The de current for the high state would be:
AVour 45
IFINAL=Z >" x Zp * INTIAL = 399 + 14.9 MA = 28.9 mA
This de current requirement violates the drive capability of many devices.
To solve this de current drive issue, the RC termination scheme is
recommended. In the first switching events of the circuit, the capacitor is not
charged thus it acts identically as the parallel resistor tied to ground. After the
voltage settles, the capacitor charges to the final voltage level and no de current
flows. The capacitors value ranges between 200-600 pF, and the resistors
value is near Zo’. The RC time constant must be less than twice the loaded
propagation delay; otherwise, the RC network adds to the ringing.
MOTOROLA AN1051/0 A198 For this case, use Z1' = 300 9 and C = 300 pF. Since the time constant is 90 ns,
this scheme should be satisfactory. The voltage and current levels during
switching follow those given in the parallel termination resistor calculations for ®
Rr = 3002.
For designers who would like to experiment with various trace configurations
and termination schemes, a spreadsheet of the formulas provides quick
comparisons of the trade-offs involved in transmission line effects. Sample
spreadsheets for Examples 1-3 are as follows:
Calculations of Surface Microstrip PCB Traits (Example 1 Configuration)
Seat ae a aE
Ep [Drslocite Constant) 4.700 4.700
H (Dielectric Thickness) 72,000 in/4000, 72,000 in/000
T (Trace Thickness) 2,000 1n/1000 2,000 1n/4000,
W (Trace Width) 710.000 in/1000, 710.000 in/t000
Zo (Characteristic impedance) 69.963 2. 69.963 2
TP (Unit Propagation Delay) 7.733 nei 1.7.33 asi
Co (intrinsic Capacitance) 2.082 prin 2.082 prin
LiLength of Trace) 4.000. 6.000 in.
'n (Number of Devices on Trak aaa “6.000 100.
i {Load Capacitance of Each Device] 7.000 pF, 7000 pF
‘Cp (Distributed Capacitance ) 70.500 pFAN_ 667 prin
Zo’ (Loaded Characteristic impedance) 28.214 2 38.524 2
TPD (Loaded Propagation Dela 4260 nsf 3.120 nsiit
Tar Te (Lessér of Fise and Fail Times) 3.000 _ns 5000 Fs
Round-Trip Time (2°T ep") 2.840 ns. 3.120 ns
‘Need Termination? (2Tpp" = TR oF 0.160 ns “O20 ns
Ge
TTretuts rom previous ine <0, then funheriwestaation is needed. __
A-20 AN1051/0 MOTOROLA Calculations of Surface Microstrip PCB Traits (Example 2 Configuration)
Eq (Distecine Constant £600 500
B { Overal Dielactic THEE] 20,000 iw7000 20000 inv7000
“(Trace Thickness) 1.400 197000 400 1n/1000
[Wace wean 3800-11000 6.000 11000
20 (Charactenstic Impedance) 50.725 2 50.725 0
2 Formula Vaid for W/(6-T)<035 0.529 0.329
‘and 1820.25 0.070 0.070
"ap (Unit Propagation Day) Zeit ns ist ns
CQ (intrinsic Capactance) 3.583 prin 3.583 pFiin
T (Length of Trace) 8.000 in 4.000 in
(Number of Devices on 309 4,000 2.000
‘Ci (Load Capacitance of Each Device) 15.000 pF 18.000 pF
Cp (Distributed Capacitance ) 7.500 pF/in_ 7.500 prin
[ Zo" (Loaded Characteristic Impedance) BREST 2.845
Tpp'(Loaded Propagation Delay) 3.836 nsMt 3.836 nsift
TR or TF (Lesser of Rise and Fall Times) 3.000 ns. 3.000 ns
Round-Trip Time (2°TPD') 5.115 ns 2.557 1S
‘Need Termination? (2°Tpp”
