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National Yunlin University of Science A ND Technology: Parallel Master Port (PMP)

The Parallel Master Port (PMP) module is an 8-bit parallel I/O module designed to communicate with various parallel devices. It contains registers like PMCON, PMMODE, PMADDR and PMAEN that control the module's operation mode, address, and pin functions. The PMP can operate in both master and slave modes to either send or receive data from external devices. Examples are provided to demonstrate how to initialize the PMP and transfer data using instructions like MOV.

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1K views24 pages

National Yunlin University of Science A ND Technology: Parallel Master Port (PMP)

The Parallel Master Port (PMP) module is an 8-bit parallel I/O module designed to communicate with various parallel devices. It contains registers like PMCON, PMMODE, PMADDR and PMAEN that control the module's operation mode, address, and pin functions. The PMP can operate in both master and slave modes to either send or receive data from external devices. Examples are provided to demonstrate how to initialize the PMP and transfer data using instructions like MOV.

Uploaded by

em330
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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National Yunlin University of Science a

nd Technology

Parallel Master Port


(PMP)
04/12
蔡宗穎
何謂 PMP
• The Parallel Master Port (PMP) module is a par
allel 8-bit I/O module, specifically designed to
communicate with a wide variety of parallel d
evices, such as communication peripherals, LC
Ds, external memory devices and microcontrol
lers.( 圖一 )
圖一
PMP MODULE OVERVIEW
PMCON Register
• A key bit is PMPEN, which is used to reset the
module as well as enable or disable the modul
e.
• When the module is disabled, all the associate
d I/O pins revert to their designated I/O functi
on.( 圖二 )
圖二
續
續
PMMODE Register
• The Parallel Master Port Mode register contain
s bits that control the operational
modes of the module. Master/Slave mode sele
ction, as well as configuration options for both
modes, are set by this register.( 圖三 )
圖三
續
PMADDR Register
• In Master modes, the register functions as PM
ADDR.( 圖四 )

• the Parallel Port Address register It contains th


e address to which outgoing data is to be writt
en to, as well as the chip select control
bits for addressing parallel slave devices.
圖四
PMAEN Register
• The Parallel Master Port Address Enable regist
er controls the operation of address and chip s
elect pins associated with this module.

• I/O or other peripheral modules associated wi


th the pins.( 圖五 )
圖五
SLAVE PORT MODES
• 8-bit data bus
• 2 address lines (Addressable mode only)
• 3 control lines (read, write and chip select)
• Selectable polarity on all control lines

• To use the PMP as a slave, the module must be e


nabled the mode must be set to one of the two p
ossible Slave modes (PMMODE<9:8> = 01 or 00).
Legacy PSP Mode
PMP Example
• PMP 程式中開啟 .LIST 的檔案
• 如:
• setup_pmp(PAR_ENABLE|PAR_STOP_IN_IDLE|
PAR_CS_00|PAR_PTRDEN_ENABLE|PAR_PTW
REN_ENABLE|PAR_MASTER_MODE_2, 0x00F
F);
顯示出
• 00248: MOV #A380,W4
• 0024A: MOV W4,600
• 0024C: MOV #200,W4
• 0024E: MOV W4,602
• 00250: MOV #FF,W4
• 00252: MOV W4,60C
從圖表找出對應的位置
解說
• A380 轉成二進位 1010 0011 1000 0000
• 200 轉成二進位 10 0000 0000
• FF 轉成二進位 1111 1111
PSP EXAMPLE
• PSP 程式中開啟 .LIST 的檔案
• 如:
• setup_pmp(PAR_ENABLE|PAR_STOP_IN_IDLE|
PAR_CS_00|PAR_PTRDEN_ENABLE|PAR_PTW
REN_ENABLE , 0x40FF);
顯示出
• 003BE: MOV #A380,W4
• 003C0: MOV W4,600
• 003C2: CLR 602
• 003C4: MOV #40FF,W4
• 003C6: MOV W4,60C
Goals
• 找出互相對應的腳位，並且啟動功能就可
以進行傳輸的目的。

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