A 32-bit ALU with Sleep Mode for Leakage Power Reduction

Abstract: during the inactive state. The

components are invoked again when
The work in this project is an attempt to any activity is detected. Power gating
design a 32-bit ALU circuit with sleep when combined with other techniques
mode to reduce leakage power such as RBB can achieve more than 100
consumption in the circuit. The project times less leakage power in sleep mode
uses a local sleep transistors network to [5].
achieve sleep mode. During sleep mode,
power savings of about 99% in Dynamic Further report is organized as
power and in Leakage power have been follows. Section 2 summarizes design
observed. A modified circuit with decisions; section 3 discusses a critical
constant inputs to combinational logic part of power gating i.e. sleep transistor
has been experimented and further design. Section 4 & 5 discuss
reduction in leakage and short circuit experimental setup and section 6
currents can be observed. summarizes results. Section 7 concludes
the work and talks about future
Keywords: Sleep Mode, Leakage power modifications or enhancements.
reduction, Sleep transistor design, min
leakage constant input vector.

1. Introduction 2. Header and Footer Designs

and other decisions
The market of portable, battery
operated computing devices has grown The sleep transistors can be
rapidly in recent years and so the need implemented in 2 ways called as Header
for Energy efficient design. The mobile and Footer types as shown in Figure 1.
computing devices are inactive for a Though both the types achieve the
long time and active only for a brief power gating, they have their pros and
amount of time. So during the inactive cons. We discuss these in this section.
state, the devices keep consuming
certain power which is dominated by the
leakage power consumption of all the
components. The designers should
provide a mechanism to reduce this
leakage power consumption. We are
considering the problem of reducing
leakage power consumption of ALU by
providing a Sleep Mode.

Various methods have been Figure 1: Header and Footer

proposed to reduce the leakage power implementations of power gating
like Reverse Body Bias, Dual-Vth domino [5]
logic [2], use of Multi Threshold CMOS
(MTCMOS)[6], Dynamic Voltage Scaling The header switch is implemented by
(DVS), Multi-Vth Cell swapping[1] and PMOS transistors to control Vdd supply.
MTCMOS power gating[5]. One of the PMOS transistor is less leaky than NMOS
most effective solutions is Power gating. transistor of a same size. The NBTI
This method enables the control logic to effect increases Vth over time and
turn off selected components in design makes PMOS transistor even less leaky.
Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
Header switches turn off VDD and keep be isolated from the next stage of logic
VSS on. As the result, it allows a simple as the crowbar currents may create
design of a pull-down transistor to excessive power consumption in next
isolate power-off cells and clamp output stage. This is done by using a simple
signals in “0” state. The “0” state circuits like a isolation cells made by
isolation is complied with reset state AND or OR. Also, clamped pull-up or
requirement in most designs. The pull-down transistors can be used. A
disadvantage of the header switch is level shifter approach is also discussed
that PMOS has lower drive current than in [7]. The ALU circuit under
NMOS of a same size, though difference experimentation is an isolated block
is reduced by strained silicon with buffers at SUM output to provide
technology. As a result, a header switch output capacitances so we have not
implementation usually consumes more implemented the current isolation
area than a footer switch circuit.
implementation.
3. Sleep Transistor Design[6]
The footer switch is implemented by
NMOS transistor to control VSS supply. One of the most critical decisions in
The advantage of footer switch is the power gating is the design of Sleep
high drive and hence smaller area. Transistor. In this work we have
However, NMOS is leakier than PMOS considered a worst case scenario of
and application designs become more current through the sleep transistor as a
sensitive to ground noise on the virtual design criterion. The Sleep transistor
ground (VVSS) coupled through the resistance should be large enough in
footer switch. The isolation on “0” state sleep mode to produce a considerable
becomes complex due to loss of the voltage drop, almost equal to VDD,
virtual ground in sleep mode and between GND and Virtual GND. Also the
necessity of bypassing footer switch to on resistance should be as small as
reach permanent VSS. In the following possible as it will have the least effect
part of the paper, we shall focus on on discharge path delay and hence on
header switch design and the speed of the circuit. But these
implementations. requirements always contradict each
other because a smaller resistance
This work has many transistors to use in means wider area of transistor which
the sleep transistor network so causes more power consumption so
considering the area penalty; it is there is always a tradeoff between
decided to use a footer type of leakage power saving and speed of the
transistor structure. circuit.

Also some other design decisions made Considering above worst case current
are discussed here. A Local sleep scenario, a Sleep transistor is designed
transistor network is used as opposed to as follows.
Global or cell level transistors. As the
gate count of original circuit is about Delay of a single gate without sleep
1450, a cell based design would require mode is given as
equal number of sleep transistors which
is a high area overhead. As this circuit is …….
a pure combinational logic, no data (1)
retention technique has been used. The
output of a power gated circuit needs to

Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
Where, VDD is the supply voltage, VtL is gives a value of (W/L) = 4774.7 ≈ 4800.
low level threshold voltages, α is This is incorporated in the design as a
Saturation Velocity Index and CL is the set of 80 parallel sleep transistors with
load capacitance. (W/L) of 60 each as shown in the figure
3.
If a sleep transistor of High Vt is
introduced, we get delay as

…….
(2)

Where, Vx is the drop across sleep

transistor while the circuit is in active
mode.

Allowing 5% overhead in the delay for

this design, we get

…….
(3) Figure 2: A 32-bit ALU with sleep
transistor network as a black box
Solving this equation for α=1.8 gives,
the voltage drop across sleep transistor
as

……. (4)

The current through the sleep transistor

is represented approx. by

……. (5)

Where, μn is mobility of electrons = 150 Figure 3: A 32-bit ALU with

cm2/V.s at 90oC, Cox is oxide capacitance calculated no. of sleep transistors
= 19.7 X 10-6 F/m for 45nm [4]. added to the network
So the width over length ratio of a sleep 4. Experimental Setup
transistor is given by
The experimental setup consists of a 32-
bit ALU circuit written originally in VHDL
and then synthesized to a transistor
level net list by using Leonardo
……. (6) Spectrum and Design Architect. The
design was synthesized to a 45 nm
Isleep is calculated by simulating the ALU
technology. This design has two 32-bit
circuit without sleep transistor network
operand inputs and a Add/Subtract input
and finding maximum current that flows
i.e 65 inputs in total and a 32-bit Sum
through ground. This equation for a
output port. A set of 200 random
45nm technology related parameters
vectors were applied to the circuit and it
Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
is simulated in HSPICE to get the input changes from one vector to other.
maximum current through sleep Leakage currents through the 80
transistor (Isleep) which we have used in parallel sleep transistor and short circuit
Equation (6). currents are some of the possible
reasons. A modification in the circuit is
Sleep transistor network is later added discussed which eliminates the change
to this circuit as shown in figure 3. at inputs of ALU and hence reduces
A set of experiments were carried out leakage and dynamic power even
on the circuit to find power savings and further.
response times of the circuit for A combinational logic is generally
transitions from sleep to active and sandwiched between two registers
active to sleep mode. Following is a list (clocked elements). Also, a sleep mode
of experiments which were carried out is accompanied by the clock gating of
a. Applied 200 vectors in Active these registers as their contents do not
mode i.e. Sleep = ‘0’ change during the sleep mode. So
during a sleep mode, a combinational
b. Applied 200 vectors in Sleep circuit practically has a constant input
mode i.e. Sleep = ‘1’ vector at its inputs. This vector
determines the leakage power
c. Applied 200 vectors when Sleep consumed by the circuit. To minimize
signal is changing from 1 to 0 after this leakage power, we can modify the
100 vectors circuit such that it will have a constant
and min. leakage power consuming
d. Applied 200 vectors when Sleep
vector at its input.
signal is changing from 0 to 1 after
100 vectors

Part a gives an estimation of circuit’s

Dynamic and Leakage energy in Active
mode while part b for the sleep mode. In
Part c, circuit changes from Active mode
to Sleep mode and we can calculate
sleep time while in part d we can
calculate wake up time. During the
sleep mode, it was observed that a
certain vector of 65 inputs has minimum
leakage power consumption for a given
set. This input vector is recorded for
Figure 4: Modified circuit to provide
future circuit modification.
a constant input vector during
sleep mode

During the sleep mode, it was observed

that certain input pair causes least
5. Modified circuit (with leakage power in the circuit. As the
multiplexers) exhaustive set combinations (265 = 36.9
X 1018) cannot be tested, a minimum
As we will discuss section 6, the
leakage vector out of the chosen
simulations in sleep mode show
random vectors is found out. This vector
considerable fluctuations in the power
can be used as a constant vector at the
consumption of the circuit when the
Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
input of the circuit and the modification to ‘0’ and the Virtual ground
in the circuit to accommodate this (bottom) changes from ‘0’ to
feature is as shown in the figure 4. approximately VDD after sleep time.

6. Results

Results of some of the experiments are

shown below.

Figure 7: Recording of Wake Up

time. Sleep signal (top) changes
from ‘0’ to ‘1’ and the Virtual
Figure 5: Active to sleep mode ground (bottom) changes from
transition of ALU. The sleep signal approximately VDD to ‘0’ after wake
is activated at 5us for this 10us up time.
simulation.
Figure 6 and 7 show results of the
As can be seen in figure 5, the dynamic experiments which are used to record
and leakage power consumption in ALU sleep time and wake-up time given in
during active mode (0 to 5us) is Table 2. After modifying the circuit with
considerably high as compared to that 2 additional multiplexers to hold
in sleep mode (5 to 10 us). The sleep minimum leakage power vectors at the
mode power consumption though low in input of ALU, we ran the same set of
average value contains some switching 200 vectors from active to sleep mode.
power or short circuit power when the The result is as shown in figure 8.
input vectors change. This also pulls Comparing it to the results in figure 5,
down the virtual ground from 1.1 V to after 5us the power consumed in ALU is
1.0 volts. Large number of sleep only leakage power and equal to the
transistors allowing a leakage current minimum possible leakage power out of
and short circuit currents can be some all the 200 vectors.
of the dominant reasons of these power
peaks. Another set of experiments of power
gating a single logic gate like EXNOR
was performed. Effect of sleep transistor
sizing and no. of sleep transistors on
Dynamic & Leakage power as well as on
virtual ground was observed. It was
observed that Dynamic and Leakage
power increases with increase in sleep
transistor size and no of sleep
transistors. Also droop in virtual ground
during sleep mode and ground bounce
Figure 6: Recording of Sleep time. during active mode decrease with
Sleep signal (top) changes from ‘1’
Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
increase in sleep transistor size and no compared to normal mode
of sleep transistors. operation

Table 1 summarizes the dynamic and in

Leakage power savings in sleep mode
and sleep mode with constant input Sleep 14 nS
vector. Time

Wakeup 0.4 nS
Time

Area 45.5%
Overhead
1456 à 1456 + 80 (CMOS
with W/L = 60 )

Table 2: Summary of overheads

caused due to implementation of
sleep mode.

7. Conclusion & future work

Figure 8: Active to sleep mode
transition of ALU with constant According to the no. of experiments
input vector during sleep mode. carried out, we can see that Power
The sleep signal is activated at 5us gating is an effective technique to
for this 10us simulation. reduce leakage power consumption of a
combinational logic block like ALU
Norm Sleep Powe Sleep Pow during inactive state. Savings can be as
al r Mode er much as 99% of the total power
Mode Savin with Savi
( uW) g ng
consumption with only proper sleep
(nW)
Const transistor network. The switching
(%) ant (%) currents/ fluctuations can be further
Input
reduced by applying a constant low
Vector
leakage vector at the input of the circuit
Avg. during sleep mode.
Dyna
302.2
mic 660.0 99.95 0 nW 100 As discussed in the results section,
04
Power we still observe some dynamic power
Avg. consumed in the ALU during sleep mode
Leaka
241.3 127.4 99.6
with the change in input due to possible
ge 34.01 99.29
2 nW 1 high leakage current or short circuit
Power
currents. The investigation of these
Peak currents is required and is part of future
5040. 1361. 127.4 99.9
Power 99.79 work. The problem can be solved using
5 13 nW 9
Min. constant low leakage vector at the
29.25 127.4 99.5
Power 127.4 99.56 input. Also the area overhead is quite
49 nW 6
high which can be reduced with
Table 1: Summary of power savings selective clustering of transistors in the
in Sleep mode and in Sleep mode ALU which is also a part of future work.
with constant input vector as
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Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009
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Manish Kulkarni Low Power Design of Electronic circuits (ELEC 6270) April , 2009