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Vlsi Prog

The document describes Verilog code for implementing a traffic light controller and real time clock on an FPGA board. The traffic light controller module uses a case statement to sequence the states of 4 lights (red, yellow, green) over time. The real time clock module uses counters and decoding to display the current time on a 7-segment display. Both modules are designed to be implemented on specific locations on the FPGA as indicated by a user constraint file.

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Saravan Visvam
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35 views19 pages

Vlsi Prog

The document describes Verilog code for implementing a traffic light controller and real time clock on an FPGA board. The traffic light controller module uses a case statement to sequence the states of 4 lights (red, yellow, green) over time. The real time clock module uses counters and decoding to display the current time on a 7-segment display. Both modules are designed to be implemented on specific locations on the FPGA as indicated by a user constraint file.

Uploaded by

Saravan Visvam
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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7.

TRAFFIC LIGHT CONTROLLER IN VERILOG HDL

module tlc(clk,reset,p1,p2,p3,p4,pl);

input clk;

input reset;

output[4:0]p1;

output[4:0]p2;

output[4:0]p3;

output[4:0]p4;

output[3:0]pl;

reg[4:0]p1;

reg[4:0]p2;

reg[4:0]p3;

reg[4:0]p4;

reg[3:0]pl;

reg[5:0]sig;

always @(posedge clk or negedge reset)

begin

if(reset==1'b0)

begin

p1<=5'b00100;
p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

sig<=6'b000000;

end

else

begin

sig<=sig+1;

case(sig[5:0])

6'b000000:

begin

p1<=5'b10011;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b000100:

begin

p1<=5'b01000;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;
end

6'b001000:

begin

p1<=5'b00100;

p2<=5'b10011;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b001100:

begin

p1<=5'b00100;

p2<=5'b01000;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b010000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b10011;

p4<=5'b00100;

pl<=4'b1111;

end
6'b010100:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b01000;

p4<=5'b00100;

pl<=4'b1111;

end

6'b011000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b10011;

pl<=4'b1111;

end

6'b011100:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b01000;

pl<=4'b1111;

end

6'b100000:
begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b0000;

end

6'b100100:sig<=6'b000000;

default:begin

end

endcase

end

end

endmodule

9. TRAFFIC LIGHT CONTROLLER IN FPGA BOARD

module tlc(clk,reset,p1,p2,p3,p4,p);

input clk;

input reset;

output[4:0]p1;

output[4:0]p2;

output[4:0]p3;
output[4:0]p4;

output[3:0]p;

reg[4:0]p1;

reg[4:0]p2;

reg[4:0]p3;

reg[4:0]p4;

reg[3:0]p;

reg[31:0]sig;

always @(posedge clk or negedge reset)

begin

if(reset==1'b0)

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b1111;

sig<=8'h0;

end

else

begin

sig<=sig+1;

case(sig[29:24])
6'b000000:

begin

p1<=5'b10011;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b1111;

end

6'b000100:

begin

p1<=5'b01000;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b1111;

end

6'b001000:

begin

p1<=5'b00100;

p2<=5'b10011;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b1111;

end

6'b001100:
begin

p1<=5'b00100;

p2<=5'b01000;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b1111;

end

6'b010000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b10011;

p4<=5'b00100;

p<=4'b1111;

end

6'b010100:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b01000;

p4<=5'b00100;

p<=4'b1111;

end

6'b011000:

begin
p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b10011;

p<=4'b1111;

end

6'b011100:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b01000;

p<=4'b1111;

end

6'b100000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

p<=4'b0000;

end

6'b100100:sig<=8'h0;

default:begin
end

endcase

end

end

endmodule

USER CONSTRIANT FILE

NET "clk" LOC = "a8";

NET "reset" LOC = "j6";

NET "p1<0>" LOC = "b14";

NET "p1<1>" LOC = "c16";

NET "p1<2>" LOC = "d15";

NET "p1<3>" LOC = "f14";

NET "p1<4>" LOC = "g14";

NET "p2<0>" LOC = "g16";

NET "p2<1>" LOC = "h15";

NET "p2<2>" LOC = "k15";

NET "p2<3>" LOC = "f15";

NET "p2<4>" LOC = "g15";

NET "p3<0>" LOC = "h14";

NET "p3<1>" LOC = "j16";

NET "p3<2>" LOC = "k16";


NET "p3<3>" LOC = "m16";

NET "p3<4>" LOC = "n16";

NET "p4<0>" LOC = "p16";

NET "p4<1>" LOC = "r16";

NET "p4<2>" LOC = "c15";

NET "p4<3>" LOC = "d14";

NET "p4<4>" LOC = "e16";

NET "p<0>" LOC = "l15";

NET "p<1>" LOC = "n15";

NET "p<2>" LOC = "p15";

NET "p<3>" LOC = "r15";

10. REAL TIME CLOCK ON FPGA

module realtimelock(clk,rst,sl,atoh);

input clk; // System Clock

input rst; // Reset(micro switch)

output[5:0] sl; // Segment Selection

output[7:0] atoh; // Segment Display Control Data

reg[5:0] sl;

reg[7:0] atoh;

reg[26:0] sig2;
reg[19:1] sig3;

reg[7:0] ssdigit1;

reg[7:0] ssdigit2;

reg[7:0] ssdigit3;

reg[7:0] ssdigit4;

reg[7:0] ssdigit5;

reg[7:0] ssdigit6;

integer digit1;

integer digit2;

integer digit3;

integer digit4;

integer digit5;

integer digit6;

always @ (posedge clk or negedge rst)

begin

if (rst == 1'b0) begin

sig2 = 0;

sig3 = 0;

digit1 = 0;

digit2 = 0;

digit3 = 0;

digit4 = 0;

digit5 = 0;

digit6 = 0;
end

else begin

sig2 = sig2 + 1;

case (sig2[24:23]) //RTC Function

2'b00 : begin

digit6 = digit6 + 1;

if (digit6 > 9) begin

digit6 = 0;

digit5 = digit5 + 1;

if (digit5 > 5) begin

digit5 =0;

digit4 = digit4 + 1;

if (digit4 >9 ) begin

digit4 = 0;

digit3 = digit3 + 1;

if (digit3 > 5) begin

digit3 = 0;

digit2 = digit2 + 1;

if (digit2 >9) begin

digit2 = 0;

digit1 = digit1 + 1; if ((digit1 >= 2) & (digit2 >= 4)) begin digit1 = 0;

digit2 = 0;

end

end
end

end

end

end

sig2[24:23] = 2'b01;

end

2'b11 : begin

if (sig2[22:19] == 4'b1001)

sig2 = 0;

end

default : begin

end

endcase

end

// Display Settings

sig3 = sig3 + 1;

case (sig3[17:15])

3'b000 : begin

sl = 6'b111110;

case (digit1)

0 : ssdigit1 = 8'b00111111;

1 : ssdigit1 = 8'b00000110;

2 : ssdigit1 = 8'b01011011;

default : ssdigit1 = 8'b00000000;


endcase

atoh = ssdigit1;

end

3'b001 : begin

sl = 6'b111101;

case (digit2)

0 : ssdigit2 = 8'b00111111;

1 : ssdigit2 = 8'b00000110;

2 : ssdigit2 = 8'b01011011;

3 : ssdigit2 = 8'b01001111;

4 : ssdigit2 = 8'b01100110;

5 : ssdigit2 = 8'b01101101;

6 : ssdigit2 = 8'b01111101;

7 : ssdigit2 = 8'b00000111;

8 : ssdigit2 = 8'b01111111;

9 : ssdigit2 = 8'b01101111;

default : ssdigit2 = 8'b00000000;

ndcase

atoh = ssdigit2;

end

3'b011 : begin

sl = 6'b111011;

case (digit3)

0 : ssdigit3 = 8'b00111111;

1 : ssdigit3 = 8'b00000110;
2 : ssdigit3 = 8'b01011011;

3 : ssdigit3 = 8'b01001111;

4 : ssdigit3 = 8'b01100110;

5 : ssdigit3 = 8'b01101101;

default : ssdigit3 = 8'b00000000;

endcase

atoh = ssdigit3;

end

3'b100 : begin

sl = 6'b110111;

case (digit4)

0 : ssdigit4 = 8'b00111111;

1 : ssdigit4 = 8'b00000110;

2 : ssdigit4 = 8'b01011011;

3 : ssdigit4 = 8'b01001111;

4 : ssdigit4 = 8'b01100110;

5 : ssdigit4 = 8'b01101101;

6 : ssdigit4 = 8'b01111101;

7 : ssdigit4 = 8'b00000111;

8 : ssdigit4 = 8'b01111111;

9 : ssdigit4 = 8'b01101111;

default : ssdigit4 = 8'b00000000;

endcase

atoh = ssdigit4;

end
3'b110 : begin

sl = 6'b101111;

case (digit5)

0 : ssdigit5 = 8'b00111111;

1 : ssdigit5 = 8'b00000110;

2 : ssdigit5 = 8'b01011011;

3 : ssdigit5 = 8'b01001111;

4 : ssdigit5 = 8'b01100110;

5 : ssdigit5 = 8'b01101101;

default : ssdigit5 = 8'b00000000;

endcase

atoh = ssdigit5;

end

3'b111 : begin

sl = 6'b011111;

case (digit6)

0 : ssdigit6 = 8'b00111111;

1 : ssdigit6 = 8'b00000110;

2 : ssdigit6 = 8'b01011011;

3 : ssdigit6 = 8'b01001111;

4 : ssdigit6 = 8'b01100110;

5 : ssdigit6 = 8'b01101101;

6 : ssdigit6 = 8'b01111101;

7 : ssdigit6 = 8'b00000111;

8 : ssdigit6 = 8'b01111111; 9 : ssdigit6 = 8'b01101111;


default : ssdigit6 = 8'b00000000;

endcase

atoh = ssdigit6;

end

endcase

end

end

endmodule

USER CONSTRIANT FILE

NET "clk" LOC = "a8";

NET "rst" LOC = "j6";

NET "atoh<0>" LOC = "p8" ;

NET "atoh<1>" LOC = "p10" ;

NET "atoh<2>" LOC = "p9" ;

NET "atoh<3>" LOC = "p6" ;

NET "atoh<4>" LOC = "p4" ;

NET "atoh<5>" LOC = "p5" ;

NET "atoh<6>" LOC = "p3" ;

NET "atoh<7>" LOC = "p11" ;

NET "sl<0>" LOC = "p1" ;

NET "sl<1>" LOC = "p2" ;

NET "sl<2>" LOC = "p7" ;


NET "sl<3>" LOC = "r4" ;

NET "sl<4>" LOC = "r11" ;

NET "sl<5>" LOC = "n14" ;

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