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VHDL Code for Digital Circuits

The document describes several digital logic components including: 1. A binary adder that adds two 4-bit inputs and outputs a 5-bit sum. 2. A BCD adder that adds two 4-bit BCD numbers and outputs a 5-bit BCD sum using a binary adder component. 3. A 4 to 16 decoder that decodes 4 input bits into 16 output bits using 3-8 decoder components.

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344 views9 pages

VHDL Code for Digital Circuits

The document describes several digital logic components including: 1. A binary adder that adds two 4-bit inputs and outputs a 5-bit sum. 2. A BCD adder that adds two 4-bit BCD numbers and outputs a 5-bit BCD sum using a binary adder component. 3. A 4 to 16 decoder that decodes 4 input bits into 16 output bits using 3-8 decoder components.

Uploaded by

GRANDHIRIA
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd

BINARY ADDER

entity badd is
port(a,b:in bit_vector(3 downto 0 );
c:out bit_vector(4 downto 0));
end badd;
architecture b1 of badd is
component fulla is
port(x,y,z:in bit;s,c:out bit);
end component;
signal x0,x1,x2:bit;
begin
y1:fulla port map(a(0),b(0),'0',c(0),x0);
y2:fulla port map(a(1),b(1),x0,c(1),x1);
y3:fulla port map(a(2),b(2),x1,c(2),x2);
y4:fulla port map(a(3),b(3),x2,c(3),c(4));
end architecture b1;
.....................................................
BCD ADDER
entity bcdd is
port(m,n:in bit_vector(3 downto 0 );
o:out bit_vector(4 downto 0));
end bcdd;
architecture b1 of bcdd is
component badd is
port(a,b:in bit_vector(3 downto 0 );
c:out bit_vector(4 downto 0));
end component;
signal x0:bit;
signal p:bit_vector(4 downto 0);
signal s,r:bit_vector(3 downto 0);
begin
z1:badd port map(m,n,p);
x0<=(p(2) and p(3)) or (p(1) and p(3));
s(0)<=p(0);
s(1)<=p(1);
s(2)<=p(2);
s(3)<=p(3);
r(0)<='0';
r(1)<=x0;
r(2)<=x0;
r(3)<='0';
z2:badd port map(s,r,o);
end ;
...................................................................
BCD ADDER
entity bcdd is
port(m,n:in bit_vector(3 downto 0 );
o:out bit_vector(4 downto 0));
end bcdd;
architecture b1 of bcdd is
component badd is
port(a,b:in bit_vector(3 downto 0 );
c:out bit_vector(4 downto 0));
end component;
signal x0:bit;
signal p:bit_vector(4 downto 0);
signal s,r:bit_vector(3 downto 0);
begin
z1:badd port map(m,n,p);
x0<=(p(2) and p(3)) or (p(1) and p(3));
s(0)<=p(0);
s(1)<=p(1);
s(2)<=p(2);
s(3)<=p(3);
r(0)<='0';
r(1)<=x0;
r(2)<=x0;
r(3)<='0';
z2:badd port map(s,r,o);
end ;
....................................................................
DECODER 4 : 16
entity dec416 is
port(a,b,c,d:in bit;s:out bit_vector(15 downto 0));
end dec416;
architecture dec4 of dec416 is
component dec38 is
port(a,b,c,e:in bit;s:out bit_vector(7 downto 0));
end component;
signal x,y,z:bit;
signal p,q:bit_vector(7 downto 0);
begin
y<=not d;
y1:dec38 port map(c,b,a,y,p);
y2:dec38 port map(c,b,a,d,q);
s(0)<=p(0);
s(1)<=p(1);
s(2)<=p(2);
s(3)<=p(3);
s(4)<=p(4);
s(5)<=p(5);
s(6)<=p(6);
s(7)<=p(7);
s(8)<=q(0);
s(9)<=q(1);
s(10)<=q(2);
s(11)<=q(3);
s(12)<=q(4);
s(13)<=q(5);
s(14)<=q(6);
s(15)<=q(7);
end;
............................................
DECODER 4 : 16
entity dec416 is
port(a,b,c,d:in bit;s:out bit_vector(15 downto 0));
end dec416;
architecture dec4 of dec416 is
component dec38 is
port(a,b,c,e:in bit;s:out bit_vector(7 downto 0));
end component;
signal x,y,z:bit;
signal p,q:bit_vector(7 downto 0);
begin
y<=not d;
y1:dec38 port map(c,b,a,y,p);
y2:dec38 port map(c,b,a,d,q);
s(0)<=p(0);
s(1)<=p(1);
s(2)<=p(2);
s(3)<=p(3);
s(4)<=p(4);
s(5)<=p(5);
s(6)<=p(6);
s(7)<=p(7);
s(8)<=q(0);
s(9)<=q(1);
s(10)<=q(2);
s(11)<=q(3);
s(12)<=q(4);
s(13)<=q(5);
s(14)<=q(6);
s(15)<=q(7);
end;
......................................................
ENCODER 3 : 8
entity enc83 is
port(i:in bit_vector(7 downto 0);o:out bit_vector(2 downto 0));
end enc83;
architecture enc of enc83 is
begin
process(i)
begin
if i(7)='1' then o<="111";
elsif i(6)='1' then o<="110";
elsif i(5)='1' then o<="101";
elsif i(4)='1' then o<="100";
elsif i(3)='1' then o<="011";
elsif i(2)='1' then o<="010";
elsif i(1)='1' then o<="001";
else o<="000";
end if;
end process;
end;

..........................................................
FULL SUBTRACTOR USING NOR
entity fsnor is
port(a,b,c: in bit;d,br: out bit);
end fsnor;
architecture g1 of fsnor is
signal x0,x1,x2,x3,x4,x5,x6,x7,f:bit;
begin
x0<=(b nor b)nor c;
x1<=(c nor c)nor b;
x2<=x0 nor x1;
f<=x2 nor x2;
x3<=(f nor f) nor a;
x4<=(a nor a) nor f;
x5<=x3 nor x4;
d<=x5 nor x5;
x6<=((b nor b) nor (c nor c));
x7<=x3 nor x6;
br<=x7 nor x7;
end;
..................................................
HALF ADDER
entity half is
port(a,b:in bit;s,c:out bit);
end half;
architecture half1 of half is
begin
s<=a xor b;
c<=a and b;
end;

...............
FULL SUBTRACTOR
entity fulls is
port(x,y,z:in bit;d,br:out bit);
end fulls;
architecture fulls1 of fulls is
component halfs is
port(a,b:in bit;d,br:out bit);
end component;
signal x0,x1,x2:bit;
begin
y1:halfs port map(x,y,x0,x1);
y2:halfs port map(x0,z,d,x2);
br<=x2 xor x1;
end architecture fulls1;
.............................
FULL ADDER
entity fulla is
port(x,y,z:in bit;s,c:out bit);
end fulla;
architecture fulla1 of fulla is
component half is
port(a,b:in bit;s,c:out bit);
end component;
signal x0,x1,x2:bit;
begin
y1:half port map(x,y,x0,x1);
y2:half port map(x0,z,s,x2);
c<=x2 or x1;
end architecture fulla1;
........................
HALF SUBTRACTOR
entity halfs is
port(a,b:in bit;d,br:out bit);
end halfs;
architecture halfs1 of halfs is
begin
d<=a xor b;
br<=(not a) and b;
end;
..............................
3 BIT MULTIPLIER
entity mul3b is
port(a:in bit_vector(2 downto 0);b:in bit_vector(2 downto 0);c:out bit_vecto
r(5 downto 0));
end mul3b;
architecture ml3b of mul3b is
component badd is
port(a,b:in bit_vector(3 downto 0 );
c:out bit_vector(4 downto 0));
end component;
signal p,q,s,t:bit_vector(3 downto 0);
signal r,u:bit_vector(4 downto 0);
begin
c(0)<=a(0) and b(0);
p(0)<=a(0) and b(1);
q(0)<=a(1) and b(0);
p(1)<=a(0) and b(2);
q(1)<=a(1) and b(1);
s(1)<=a(2) and b(0);
q(2)<=a(1) and b(2);
s(2)<=a(2) and b(1);
s(3)<=a(2) and b(2);
p(2)<='0';
p(3)<='0';
q(3)<='0';
s(0)<='0';
t(0)<=r(0);t(1)<=r(1);t(2)<=r(2);t(3)<=r(3);
y1:badd port map(p,q,r);
y2:badd port map(t,s,u);
c(1)<=u(0);c(2)<=u(1);c(3)<=u(2);c(4)<=u(3);
c(5)<=r(4) xor u(4);
end;
..........................
4 BIT MULTIPLIER
entity mul4b is
port(a:in bit_vector(3 downto 0);b:in bit_vector(3 downto 0);c:out bit_vecto
r(7 downto 0));
end mul4b;
architecture ml4b of mul4b is
component badd is
port(a,b:in bit_vector(3 downto 0 );
c:out bit_vector(4 downto 0));
end component;
signal k,l,m,n,o,p:bit_vector(3 downto 0);
signal q,r,s:bit_vector(4 downto 0);
begin
c(0)<=a(0) and b(0);
k(0)<=a(0) and b(1);
k(1)<=a(0) and b(2);
k(2)<=a(0) and b(3);
k(3)<='0';
l(0)<=a(1) and b(0);
l(1)<=a(1) and b(1);
l(2)<=a(1) and b(2);
l(3)<=a(1) and b(3);
m(0)<=a(2) and b(0);
m(1)<=a(2) and b(1);
m(2)<=a(2) and b(2);
m(3)<=a(2) and b(3);
n(0)<=a(3) and b(0);
n(1)<=a(3) and b(1);
n(2)<=a(3) and b(2);
n(3)<=a(3) and b(3);
y1:badd port map(k,l,q);
c(1)<=q(0);
o(0)<=q(1);
o(1)<=q(2);
o(2)<=q(3);
o(3)<=q(4);
y2:badd port map(m,o,r);
c(2)<=r(0);
p(0)<=r(1);
p(1)<=r(2);
p(2)<=r(3);
p(3)<=r(4);
y3:badd port map(n,p,s);
c(3)<=s(0);
c(4)<=s(1);
c(5)<=s(2);
c(6)<=s(3);
c(7)<=s(4);
end;
........................................................
2 : 1 MUX
entity mux21 is
port(a,b,s:in bit;p:out bit);
end mux21;
architecture mux21a of mux21 is
begin
process(a,b,s)
begin
if s='0' then
p<=a;
else
p<=b;
end if;
end process;
end;
...........................
4 : 1 MUX
entity mux41 is
port(a,b,c,d,s0,s1:in bit;x:out bit);
end mux41;
architecture mx41 of mux41 is
begin
process(a,b,c,d,s0,s1)
begin
if (s1&s0="00") then
x<=a;
elsif (s1&s0="01") then
x<=b;
elsif (s1&s0="10") then
x<=c;
else
x<=d;
end if;
end process;
end;
...................
ADDER USING MUX
entity mx2add is
port(a0,a1,b0,b1:in bit;c0,c1,c2:out bit);
end mx2add;
architecture m2bd of mx2add is
component mux41 is
port(a,b,c,d,s0,s1:in bit;x:out bit);
end component;
signal y0,y1,y2,y3,y4:bit;
begin
y0<=b1 xor b0;
y1<=((not b1) and (not b0)) or (b1 and b0);
y2<=not b1;
y3<= b1 and b0;
y4<=not b0;
x1:mux41 port map(b0,y4,b0,y4,a0,a1,c0);
x2:mux41 port map(b1,y0,y2,y1,a0,a1,c1);
x3:mux41 port map('0',y3,b1,b1,a0,a1,c2);
end;
..........................
MUX USING GATES
entity mxgates is
port(p,q,s:in bit;a,r,nt,na,nr,xr:out bit);
end mxgates;
architecture gatesmx of mxgates is
component mux21 is
port(a,b,s:in bit;p:out bit);
end component;
signal x:bit;
begin
x<=not q;
y1:mux21 port map('0',q,p,a);
y2:mux21 port map(q,'1',p,r);
y3:mux21 port map('1','0',p,nt);
y4:mux21 port map('1',x,p,na);
y5:mux21 port map(x,'0',p,nr);
y6:mux21 port map(q,x,p,xr);
end;
.......................................

entity y is
port(a:in bit_vector(3 downto 0);y:out bit);
end y;
architecture y1 of y is
component mux41 is
port(a,b,c,d,s0,s1:in bit;x:out bit);
end component;
signal y0,y1,y2,y3:bit;
begin
y0<=(not a(2));
y1<=(not a(2) and not a(3)) or (a(2) xor a(3));
y2<=a(3) and (not a(2));
y3<=(not a(2)) and (not a(3));
z1:mux41 port map(y0,y1,y2,y3,a(0),a(1),y);
end;

..........................................
8 : 1 MUX
entity mux81 is
port(i:in bit_vector(7 downto 0);
s:in bit_vector(2 downto 0);o:out bit);
end mux81;
architecture amux81 of mux81 is
signal y:bit_vector(2 downto 0);
begin
y<=s(2)&s(1)&s(0);
o<=i(0) when y="000" else
i(1) when y="001" else
i(2) when y="010" else
i(3) when y="011" else
i(4) when y="100" else
i(5) when y="101" else
i(6) when y="110" else
i(7) when y="111" else
'0';
end;
.........................................
FULL ADDER USING NAND
entity fanand is
port(a,b,c:in bit;s,ca:out bit);
end fanand;
architecture faanand of fanand is
signal x0,x1,x2,x3,x4,x5,x6,x7,x8,y0,y1,y2,y3,y4:bit;
begin
x0<=a nand a;
x1<=b nand b;
x2<=x0 nand b;
x3<=a nand x1;
x4<=x2 nand x3;
x5<=x4 nand x4;
x6<=c nand c;
x7<=x5 nand c;
x8<=x6 nand x4;
s<=x8 nand x7;
y0<=a nand b;
y1<=b nand c;
y2<=a nand c;
y3<=y0 nand y1;
y4<=y3 nand y3;
ca<=y4 nand y2;
end;
.........................................

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