Test Bench For Multiplexer
Test Bench For Multiplexer
Test Bench For Multiplexer
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
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architecture TB of Mux_TB is
component Mux
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end component;
begin
U_Mux: Mux port map (T_I3, T_I2, T_I1, T_I0, T_S, T_O);
process
begin
wait;
end process;
end TB;
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configuration CFG_TB of Mux_TB is
for TB
end for;
end CFG_TB;
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