Programmable Array Logic VHDL Enotes
Programmable Array Logic VHDL Enotes
ARRAY LOGIC
By:
Prof K R Shobha,
M S Ramiah Institute of Technology, Bangalore
The figure 1 below shows a segment of an unprogrammed PAL. The input buffer
with non inverted and inverted outputs is used, since each PAL must drive many AND
Gates inputs. When the PAL is programmed, the fusible links (F1, F2, F3…F8) are
selectively blown to leave the desired connections to the AND Gate inputs. Connections
to the AND Gate inputs in a PAL are represented by Xs, as shown here:
Input
buffer
As an example, we will use the PAL segment of figure 1 to realize the function
I1I2’+I1I2. the Xs indicate that the I1 and I2’ lines are connected to the first AND Gate, and
the I1’ and I2 lines are connected to the other Gate.
Q+ = D = A’BQ’ + AB’Q
The flip-flop output is connected to an inverting tristate buffer, which is enabled when
EN = 1
Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4.
This PAL has an AND gate array with 16 input variables, and it has 4 D flip-flops. Each
flip-flop output goes through a tristate-inverting buffer (output pins 14-17). One input
(pin 11) is used to enable these buffers. The rising edge of a common clock (pin 1) causes
the flip-flops to change the state. Each D flip-flop input is driven from an OR gate, and
each OR gate is fed from 8 AND gates. The AND gate inputs can come from the external
PAL inputs (pins2-9) or from the flip-flop outputs, which are fed back internally. In
addition there are four input/output (i/o) terminals (pins 12,13,18 and 19), which can be
used as either network outputs or as inputs to the AND gates. Thus each AND gate can
have a maximum of 16 inputs (8 external inputs, 4 inputs fed back from the flip-flop
outputs, and 4 inputs from the i/o terminals). When used as an output, each I/O terminal
is driven from an inverting tristate buffer. Each of these buffers is fed from an OR gate
and each OR gate is fed from 7 AND gates. An eighth AND gate is used to enable the
buffer.
When the 16R4 PAL is used to realize a sequential network, the I/O terminals are
normally used for the z outputs. Thus, a single 16R4 with no additional logic could
realize a sequential network with up to 8 inputs, 4 outputs, and 16 states. Each next state
equation could contain up to 8 terms, and each output equation could contain up to 7
terms. As an example, we will realize the BCD to Excess-3 code converter using three
flip-flops to store Q1,Q2 and Q3, and the array logic that drives these flip-flops is
programmed to realize D1, D2 and D3, as shown in figure 3 .The Xs on the diagram
indicate the connections to the AND-gate inputs. An X inside an AND gate indicates that
the gate is not used. For D3, three AND gates are used, and the function realized is
The flip-flop outputs are not used externally, so the output buffers are disabled. Since the
Z output comes through the inverting buffer, the array logic must realize
The z output buffer is permanently enabled in this example, so there are no connections
to the AND gate that drives the enable input, in which case the AND gate output is
logic1.
When designing with PALS, we must simplify our logic equations and try to fit them in
one or more PALs. Unlike the more general PLA, the AND terms cannot be shared
among two or more OR gates; therefore, each function to be realized can be simplified by
itself without regard to common terms. For a given type of PAL the number of AND
terms that feed each output OR gate is fixed and limited. If the number of AND terms in
a simplified function is too large, we may be forced to choose a PAL with more OR-gate
inputs and fewer outputs.
Computer aided design programs for PAL s are widely available. Such programs accept
logic equations, truth tables, state graphs, or state tables as inputs and automatically
generate the required fused patterns. These patterns can then be downloaded into a PLD
programmer, which will blow the required, fuses and verify the operation of the PAL.
The 22CEV10 is a CMOS electrically erasable PLD that can be used to realize both
combinational and sequential networks. It has 12 dedicated input pins and 10 pins that
can be programmed as either inputs or outputs. It contains 10 d flip-flops and 10 OR
gates. The number of AND gates that feed each OR gate ranges from 8 to 16. Each OR
gate drives an output logic macrocell. Each macrocell contains one of the 10 D flip-flops.
The flip-flops have the common clock , a common asynchronous reset (AR) input and a
common synchronous preset (SP) input. The name 22V10 indicates a versatile PAL with
a total of 22 input and output pins, 10 of which are bi-directional I/O (input/output) pins.
For any further details regarding 22CEV10 please visit the site
(http://www.anachip.com/downloads/datasheets/pld/PEEL22CV10AZ.pdf)s
Figure 7 shows the Moore state graph for the controller. For timing purposes, the
sequential network is driven by a clock with a 10 second period. Thus, a state change can
occur at most once every 10 seconds. The following notation is used: GaRb in a state
means that Ga=Rb=1 and all other output variables are 0. Sa’Sb on an arc implies that
Sa=0 and sb=1 will cause a transition along that arc. An arc without a label implies that a
state transition will occur when clock occurs, independent of the input variables. Thus,
the green “A” light will stay on for 6 clock cycles (60 seconds) and then changes to
yellow if a car is waiting on “B” street.
The vhdl code for the traffic light controller given below represents the state
machine by two processes. Whenever the state , Sa, or Sb changes, the first processes
updates the outputs and next state. Whenever the rising edge of the clock occurs, the
second process updates the state register. The case statement illustrates use of a when
clause with a range.since state s0 through s4 have the same outputs, and the next states
are in numeric sequence, we use a when clause with a range instead of five separate when
clauses:
When 0 to 4 => Ga<= ‘1’; Rb <= ‘1’; nextstate <= state +1;
For each state, only the signals that are ‘1’ are listed within the case statement.
Since in VHDL a signal will hold its value until it is changed, we should turn off each
signal when the next state is reached. In state 6 we should set Ga to ‘0’, in state 7 we
should set Ya to ‘0’, etc..This could be accomplished by inserting appropriate statements
in the when clauses. for example, we could insert Ga < = ‘0’ in the when 6 => clause. An
easier way to turn off three outputs is to set them all to zero before the case statement. At
first, it seems that a glitch might occur in the output when we set as signal to zero that
should remain 1. however, this is not a problem because sequential statement within the
process execute instantaneously. For example, suppose that the time = 20 a state change
from S2 to S3 occurs. Ga and Rb are ‘1’, but as soon as the process starts executing, the
library ieee;
use ieee.std_logic_1164.all;
entity traffic_light is
port (clk, sa, sb: in bit;
ra, rb, ga, gb, ya, yb: inout bit);
end traffic_light;
architecture behave of traffic_light is
signal state, nextstate: integer range 0 to 12;
type light is (r, y, g);
signal lighta, lightb: light;
begin
process(state, sa, sb)
begin
ra <= '0'; rb <= '0'; ga <= '0'; gb <= '0'; ya <= '0'; yb <=
'0';
case state is
when 0 to 4 => ga <= '1'; rb <= '1'; nextstate <= state+1;
when 5 => ga <= '1'; rb <= '1'; if sb = '1'then nextstate
<= 6; end if;
when 6 => ya <= '1'; rb <= '1'; nextstate <= 7;
when 7 to 10 => ra <= '1'; gb <= '1'; nextstate <= state+1;
when 11 => ra <= '1'; gb <= '1';
if (sa='1'or sb='0') then nextstate <= 12; end if;
when 12 => ra <= '1'; yb <= '1'; nextstate <= 0;
end case;
end process;
process(clk)
begin
nagaswetha Page 10 13/04/2005
if clk = '1'then state <= nextstate; end if;
end process;
Figure 8:test results for traffic controller
To get the excitation table from the state table of the traffic controller we replace all the
state names with its equivalent binary values as shown in the figure 10.
The equations for D1, D2, D3 and D4 have six variables Q1, Q2, Q3, Q4, Sa and
Sb. So for different combinations of Sa Sb. The four variable K-map with Q1Q2Q3and
Q4 are solved the resulting four equations are ANDed with their respective Sa Sb values.
These expressions are then Ored together to get the desired expressions for D1 D2 D3
D4. the detailed procedure for D1 is shown in the figure 11.
AT SaSb=01
AT SaSb=00 D1= Q1Q2’ + Q2Q3Q4
D1= Q1Q2’ + Q2Q3Q4
Simplifying further
D1 = Q1Q2’ + Q2Q3Q4
Similarly the below equations can be solved and implemented using PAL.