What Are The Physical Addresses For The Following Logical Addresses

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Memory management techniques like paging and segmentation are used to map virtual to physical addresses. Page faults occur when a process references a page not currently in memory, requiring it to be fetched from disk.

a. 219 + 430 = 649 b. 2300 + 10 = 2310 c. illegal reference, trap to operating system d. 1327 + 400 = 1727 e. illegal reference, trap to operating system

When a memory load operation is performed, there are three memory operations that might be performed. One is to translate the position where the page table entry for the page could be found (since page tables themselves are paged). The second access is to access the page table entry itself, while the third access is the actual memory load operation.

1.

What are the physical addresses for the following logical addresses? Answer:
a. 0,430 a. 219 + 430 = 649
b. 1,10 b. 2300 + 10 = 2310
c. 2,500 c. illegal reference, trap to operating system
d. 3,400 d. 1327 + 400 = 1727
e. 4,112 e. illegal reference, trap to operating system

2. Consider the hierarchical paging scheme used by the VAX architecture. How many memory operations are performed
when an user program executes a memory load operation?
Answer:When a memory load operation is performed, there are three memory operations that might be performed. One is to
translate the position where the page table entry for the page could be found (since page tables themselves are paged). The
second access is to access the page table entry itself, while the third access is the actual memory load operation.

3. Consider a logical address space of eight pages of 1024 words each, mapped onto a physical memory of 32 frames.
a. How many bits are there in the logical address? a. Logical address: 13 bits
b. How many bits are there in the physical address? b. Physical address: 15 bits

4. In the IBM/370, memory protection is provided through the use of keys. A key is a 4-bit quantity. Each 2K block of
memory has a key (the storage key) associated with it. The CPU also has a key (the protection key) associated with it. A
store operation is allowed only if both keys are equal, or if either is zero. Which of the following memory-management
schemes could be used successfully with this hardware?
a. Bare machine a. Protection not necessary, set system key to 0.
b. Single-user system b. Set system key to 0 when in supervisor mode.
c. Multiprogramming with a fixed number of c. Region sizes must be fixed in increments of 2k bytes, allocate key
processes with memory blocks.
d. Multiprogramming with a variable number of d. Same as above.
processes e. Frame sizes must be in increments of 2k bytes, allocate key with
e. Paging pages.
f. Segmentation f. Segment sizes must be in increments of 2k bytes, allocate key with
segments.

5. Assume that you have a page-reference string for a process with m frames (initially all empty). The page-reference string
has length p; n distinct page numbers occur in it. Answer these questions for any page-replacement algorithms:
a. What is a lower bound on the number of page faults? a. n
b. What is an upper bound on the number of page faults? b. p

6. Which of the following programming techniques and structures are “good” for a demand-paged environment ? Which are
“not good”? Explain your answers.
a. Stack a. Stack—good.
b. Hashed symbol table b. Hashed symbol table—not good.
c. Sequential search c. Sequential search—good.
d. Binary search d. Binary search—not good.
e. Pure code e. Pure code—good.
f. Vector operations f. Vector operations—good.
g. Indirection g. Indirection—not good.

7. Consider the following page-replacement algorithms. Rank these algorithms on a five-point scale from “bad” to “perfect”
according to their page-fault rate. Separate those algorithms that suffer from Belady’s
anomaly from those that do not.

Rank Algorithm Suffer from Belady’s anomaly


a. LRU replacement 1 Optimal no
b. FIFO replacement 2 LRU no
c. Optimal replacement 3 Second-chance yes
d. Second-chance replacement 4 FIFO yes
8. An operating system supports a paged virtual memory, using a central processor with a cycle time of 1
microsecond. It costs an additional 1 microsecond to access a page other than the current one. Pages have
1000 words, and the paging device is a drum that rotates at 3000 revolutions per minute and transfers 1
million words per second. The following statistical measurements were obtained from the system:
• 1 percent of all instructions executed accessed a page other than the current page.
• Of the instructions that accessed another page, 80 percent accessed a page already in memory.
• When a new page was required, the replaced page was modified 50 percent of the time.
Calculate the effective instruction time on this system, assuming that the system is running one process only and that the
processor is idle during drum transfers.
Answer:
effective access time = 0.99 × (1 sec + 0.008 × (2 sec)
+ 0.002 × (10,000 sec + 1,000 sec) + 0.001 × (10,000 sec + 1,000 sec)
= (0.99 + 0.016 + 22.0 + 11.0) sec
= 34.0 sec

9. Consider the two-dimensional array A: int A[][] = new int[100][100]; where A[0][0] is at location 200, in a paged
memory system with pages of size 200. A small process is in page 0 (locations 0 to 199) for manipulating the matrix; thus,
every instruction fetch will be from page 0. For three page frames, how many page faults are generated by the following
array-initialization loops, using LRU replacement, and assuming page frame 1 has the process in it, and the other two are
initially empty?
a. for (int j = 0; j < 100; j++) b. for (int i = 0; i < 100; i++)
for (int i = 0; i < 100; i++) for (int j = 0; j < 100; j++)
A[i][j] = 0; A[i][j] = 0;
Answer:
a. 50 b. 5,000

10. Consider the following page reference string : 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6 How many page faults
would occur for the following replacement algorithms, assuming one, two, three, four, five, six, or seven frames? Remember
all frames are initially empty, so your first unique pages will all cost one fault each.
• LRU replacement
• FIFO replacement
• Optimal replacement
Answer:
Number of frames LRU FIFO Optimal
1 20 20 20
2 18 18 15
3 15 16 11
4 10 14 8
5 8 10 7
6 7 10 7
7 7 7 7

11. Consider a demand-paged computer system where the degree of multiprogramming is currently fixed at four. The system
was recently measured to determine utilization of CPU and the paging disk. The results are one of the following alternatives.
For each case, what is happening? Can the degree of multiprogramming be increased to increase the CPU utilization? Is the
paging helping?

a. CPU utilization 13 percent; disk utilization 97 percent a. Thrashing is occurring.


b. CPU utilization 87 percent; disk utilization 3 percent b. CPU utilization is sufficiently high to leave things alone,
c. CPU utilization 13 percent; disk utilization 3 percent and increase degree of multiprogramming.
c. Increase the degree of multiprogramming

12. Consider a file currently consisting of 100 blocks. Assume that the file control block (and the index block, in the case of
indexed allocation) is already in memory. Calculate how many disk I/O operations are required for contiguous, linked, and
indexed (single-level) allocation strategies, if, for one block, the following conditions hold. In the contiguous-allocation case,
assume that there is no room to grow in the beginning, but there is room to grow in the end. Assume that the block
information to be added is stored in memory.
a. The block is added at the beginning. Contiguous Linked Indexed
b. The block is added in the middle. a. 201 1 1
c. The block is added at the end. b. 101 52 1
d. The block is removed from the beginning. c. 1 3 1
e. The block is removed from the middle. d. 198 1 0
f. The block is removed from the end. e. 98 52 0
f. 0 100 0
13. Consider a system that supports the strategies of contiguous, linked, and indexed allocation. What
criteria should be used in deciding which strategy is best utilized for a particular file?
Answer:
• Contiguous—if file is usually accessed sequentially, if file is
relatively small.
• Linked—if file is large and usually accessed sequentially.
• Indexed—if file is large and usually accessed randomly.

14. Consider a file system on a diskthat has both logical andphysical block sizes of 512 bytes. Assume that the information
about each file is al- ready inmemory. For each of the three allocation strategies (contiguous, linked, and indexed), answer
these questions:
a. How is the logical-to-physical address mapping accomplished in this system? (For the indexed allocation, assume that a
file is always less than 512 blocks long.)
b. If we are currently at logical block 10 (the last block accessed was block 10) and want to access logical block 4, howmany
physical blocks must be read from the disk?
Answer:LetZ be the starting file address (block number).
a. Contiguous. Divide the logical address by 512 withX andY the resulting quotient and remainder respectively.
1. AddX toZ to obtain the physical block number.Y is the displacement into that block.
2. 1
b. Linked. Divide the logical physical address by 511 withX andY the resulting quotient and remainder respectively.
1. Chase down the linked list (gettingX+ 1 blocks).Y+ 1 is the displacement into the last physical block.
2. 4
c. Indexed. Divide the logical address by 512 withX andY the resulting quotient and remainder respectively.
1. Get the index block into memory. Physical block address is contained in the index block at locationX.Y is the dis-
placement into the desired physical block.
2. 2

15. Consider a demand-paging system with the following time-measured utilizations:


CPUutilization 20%
Paging disk 97.7%
OtherI/Odevices 5%
Answer:The system obviously is spending most of its time paging, indicating over-allocation of memory. If the level of
multiprogramming is reduced resident processes would page fault less frequently and the CPUutilization would improve.
Another way to improve performance would be to get more physical memory or a faster paging drum.

Which (if any) of the following will (probably) improveCPUutilization? a. Get a fasterCPU— No.
Explain your answer. b. Get a bigger paging drum — No.
a. Install a fasterCPU. c. Increase the degree of multiprogramming —
b. Install a bigger paging disk. No.
c. Increase the degree of multiprogramming. d. Decrease the degree of multiprogramming
d. Decrease the degree of multiprogramming. — Yes.
e. Install more main memory.
f. Install a faster hard disk or multiple controllers with multiple hard disks.
g. Add prepaging to the page fetch algorithms.
h. Increase the page size.

16. Given five memory partitions of 100KB, 500KB, 200KB, 300KB, and 600KB(in order), how would each of the first-fit,
best-fit, and worst-fit algorithms place processes of 212KB, 417 KB, 112 KB, and 426 KB(in order)? Which algorithm
makes the most efficient use of memory? Answer:
a. First-fit:
b. 212K is put in 500K partition
c. 417K is put in 600K partition
d. 112K is put in 288K partition (new partition 288K = 500K - 212K)
e. 426K must wait
f. Best-fit:
g. 212K is put in 300K partition
h. 417K is put in 500K partition
i. 112K is put in 200K partition
j. 426K is put in 600K partition
k. Worst-fit:
l. 212K is put in 600K partition
m. 417K is put in 500K partition
n. 112K is put in 388K partition
o. 426K must wait
In this example, Best-fit turns out to be the best.

17 . Compare the circular-wait scheme with the deadlock-avoidance schemes (like the banker’s algorithm)
with respect to the following issues:
a. Runtimeoverheads
b. Systemthroughput
Answer:A deadlock-avoidance scheme tends to increase the runtime overheads due to the cost of keep trackof the current
resource allocation. However, a deadlock-avoidance scheme allows for more concurrent use of resources than schemes that
statically prevent the formation of dead- lock. In that sense, a deadlock-avoidance scheme could increase system throughput.

18. Using the WindowsXPscheduling algorithm, what is the numeric priority of a thread for the following scenarios?
a. A thread in the REALTIMEPRIORITY CLASS with a relative priority of HIGHEST. a. 26
b. A thread in the NORMALPRIORITY CLASS with a relative priority of NORMAL. b. 8
c. A thread in the HIGHPRIORITY CLASS with a relative priority of ABOVE NORMAL. c. 14

19. Consider the scheduling algorithm in the Solaris operating system for time sharing threads: a. What is the time
quantum (in milliseconds) for a thread with priority 10? With priority 55?
b. Assumeathreadwithpriority35hasuseditsentiretimequantum without blocking. What new priority will the scheduler assign
this thread?
c. Assume a thread with priority 35 blocks for I/O before its time quantum has expired. What new priority will the scheduler
assign this thread?
Answer: a. 160 and 40 b. 35 c. 54

20. Consider a preemptive priority scheduling algorithm based on dynamically changing priorities. Larger priority numbers
implyhigher priority. When a process is waiting for theCPU(in the ready queue, but not run- ning), its priority changes at a
rate alpha; when it is running, its priority changes at a rate beta. All processes are given a priority of 0 when they enter the
ready queue. The parameters alpha and beta can be set to give many different scheduling algorithms.
a. What is the algorithm that results from beta > alpha > 0 ?
b. What is the algorithm that results from alpha < beta < 0 ?
Answer: a.FCFS b.LIFO

21. Describe the differences among short-term, medium-term, and long-term scheduling.
Answer:
•Short-term (CPU scheduler) — selects from jobs in memory those jobs that are ready to execute and allocates
theCPU to them.
•Medium-term — used especially with time-sharing systems as an intermediate scheduling level. A swapping
scheme is implemented to remove partially run programs from memory and reinstate them later to continue where they left
off.
•Long-term (job scheduler) — determines which jobs are brought into memory for processing.
The primary difference is in the frequency of their execution. The short- term must select a new process quite often. Long-
term is used much less often since it handles placing jobs in the system and may wait a while for a job to finish before it
admits another one.
22. The processes are assumed to have arrived in the orderP1,P2,P3,P4,P5, all at time 0 :

.
a. Draw four Gantt charts illustrating the execution of these pro- cesses usingFCFS, SJF, a nonpreemptive priority (a smaller
pri- ority number implies a higher priority), andRR (quantum = 1) scheduling.
b. What is the turnaround time of each process for each of the scheduling algorithms in part a?
c. What is the waiting time of each process for each of the scheduling algorithms in part a ?
d. Which of the schedules in part a results in the minimal average waiting time (over all processes) ?
b. Turnaround time :

c. Waiting time :
d. SJF
SOMETHINGS :
SCHEDULING CRITERIA :
1. CPU Utilization
2. Throughtput
3. Turnaround time
4. Waiting time
5. Response time
DISPATCH LATENCY : time for dispatcher to stop one process and start another running .
SJF is provably optimal . It ‘s main difficulty is how to detect the length of next processes .

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