MOS Transistor

Spring 2008

Poras T. Balsara
Center for Integrated Circuits and Systems
Department of Electrical Engineering
University of Texas at Dallas

Outline

„ MOSFET structure
„ Threshold voltage concept
„ I-V characteristics and different regions of operation
„ Secondary effects
„ Short-channel devices
„ SPICE model

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 The MOSFET

„ N areas have been doped

with donor ions (arsenic)
with concentration ND
- electrons are majority
carriers.

„ P areas have been doped

with acceptor ions (boron)
with concentration NA
- holes are majority
Cross-section of an NMOSFET carriers.

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N-Channel MOSFET (NMOSFET)

„ Conducting channel is formed between drain and source

when the gate-source voltage,
VGS ≥ VTn

„ VTn is the NMOSFET Threshold Voltage

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 P-Channel MOSFET (PMOSFET)

„ Conducting channel is formed between drain and source

when the gate-source voltage,
VGS ≤ VTp

„ VTp is the PMOSFET Threshold Voltage

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Enhancement vs. Depletion Mode

„ Enhancement Mode Devices: In these devices, application of

VGS forms a conducting channel between drain and source.
Channel does not exist under zero gate bias.
„ Depletion Mode Devices: In these devices, channel exists
under zero gate bias. Application of VGS turns these devices
off.
„ MOSFET Symbols:

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 Cross-section of CMOS Technology

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NMOSFET – Threshold Voltage

„ Accumulation Region:
VGS < 0

„ Flat-band Condition:
VGS = VFB

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 NMOSFET – Threshold Voltage

„ Depletion Region:
VGS > VFB

„ Surface Inversion:
VGS ≥ VTn

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Threshold Voltage

VT = VT 0 + γ ( −2φ F + VSB − −2φ F )

The body-effect coefficient: it
Threshold voltage at VBS=0 expresses impact of changes in VBS
and is mostly a function of
manufacturing process. = ( 2qε si N A ) C ox

Substrate Bias (bulk source voltage)

Note: The threshold voltage has a positive value for a typical NMOSFET,
while it is negative for a normal PMOSFET.

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 The Body Effect

„ Effect of well bias on an

NMOSFET is plotted here. (VTn
is positive for a normal
NMOSFET with body tied to
ground).
„ Negative bias on well or
substrate causes VTn to
increase from 0.45V to 0.85V

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Body Effect in a Logic Gate

n2
strong inversion: VGS > VT
VT2 VSB2=0 VG V > V
S T
n1

VT1 VSB1=0
body effect: VT2 > VT1

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 NMOSFET V-I : Cut-off Region

VGS < VTn

VDS

S D
n+ n+

p-

„ VGS < VTn

„ IDS ≈ 0
„ IDS is due to diode reverse-bias leakage current and/or
sub-threshold conduction.
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NMOSFET in Linear (Resistive) Region

VGS > VTn
VDS < VGS VTn

G I
DS
S D
n+ n+

p-

„ VGS ≥ VTn and VDS < VGS – VTn

W⎡ 2
VDS ⎤
„ I DS = kn′ (
⎢ GSV − VTn ) V DS − ⎥
L ⎣ 2 ⎦

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 NMOSFET V-I: Linear Region

W⎡ 2
VDS ⎤
(
I DS = kn′
⎢ GSV − VTn ) V DS − ⎥
L ⎣ 2 ⎦
Process Transconductance Parameter MOSFET Gain Factor
kn′ =µ n C ox = µ n ε ox / tox in A / V (
2
) kn = kn′ W L
Carrier Mobility
Oxide Perm ittivity:
µ n ≈ 1350 cm 2 / V sec
ε ox = 3.97 × ε 0 = 3.5 × 10 −11 F / m
µ p ≈ 480 cm 2 / V sec
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NMOSFET V-I: Saturation Region

> >

„ VGS > VTn and VDS ≥ VGS – VTn

kn′ W
(VGS − VTn )
2
„ I DS =
2 L
Why is this equation not entirely correct?
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 Channel Length Modulation

„ The position of the pinch-off point shifts as VDS is

increased. Consequently, the effective channel length
(i.e., L’ = L – ∆L) is modulated by VDS.
„ IDS is increased when the effective length is decreased.

kn′ W
(VGS − VTn ) (1 + λVDS )
2
I DS =
2 L
„ λ is an empirical constant parameter, called the
channel-length modulation coefficient (varies roughly
with the inverse of the channel length)

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Current Determinates

„ For a fixed VDS and VGS (≥ VTn), IDS is a function of

„ the distance between the source and drain - L

„ the channel width - W
„ the threshold voltage - VT
„ the thickness of the oxide - tox
„ the dielectric of the gate insulator (SiO2) - εox
„ the carrier mobility:
„ for NMOSFETs: µn ≈ 1350 cm2/V-sec
„ for PMOSFETs: µp ≈ 480 cm2/V-sec

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 Long Channel NMOS I-V Curves

Quadratic
dependence

NMOSFET: 0.25µm CMOS, VDD=2.5V, VTn=0.5V Ld=10µm W/L=1.5

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I-V Characteristics: Summary

Region NMOSFET PMOSFET

VGS < VTn VGS > VTp
Cutoff
IDS ≈ 0 IDS ≈ 0

VGS ≥ VTn VGS ≤ VTp

VDS < VGS – VTn VDS > VGS – VTp
Linear
W⎡ 2
⎤ W⎡ 2
VDS ⎤
⎢(VGS − VTp ) VDS −
VDS
I DS = kn′ ⎢(VGS − VTn ) VDS − ⎥ I DS = k ′p
L ⎣ 2 ⎦
⎥
L ⎣ 2 ⎦

VGS ≥ VTn VGS ≤ VTp

VDS ≥ VGS – VTn VDS ≤ VGS – VTp
Saturation
kn′ W k′ W
( VGS − VTp ) ( 1 + λVDS )
2
(VGS − VTn ) (1 + λVDS )
2
I DS = I DS = p
2 L 2 L

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 Short Channel Effects

„ The behavior of MOSFET with sub-micron channel length

deviates considerably from the first-order long channel
models discussed earlier.
„ Some short channel effects for sub-micron transistors:
„ Velocity saturation and mobility degradation
„ Sub-threshold conduction and gate leakage
„ Threshold voltage variations
„ Parasitic resistance
„ Secondary effects:
„ Temperature effects
„ Hot carrier effects
„ Latchup

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Velocity Saturation

„ Carrier velocity saturates when the electric field along the channel
reaches a critical value ξc. This is due to scattering (collisions suffered
by the carriers).

ξc vsat

1.5x104 V/cm
NMOS 107 cm/s
(or 1.5 V/µm)

PMOS ≥ 105 V/cm 107 cm/s

ξc
ξ

For an NMOSFET with L=1µm, only a couple of volts difference between

D and S is needed to reach velocity saturation.

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 V-I Relation: Velocity Saturation

„ NMOS Linear Region: VDS < VGS – VTn

W ⎡ 2
VDS ⎤
I DS = κ (VDS ) kn′ ⎢ ( GS Tn ) DS
V − V V −
L ⎣ 2 ⎥⎦
where,
κ (V ) = 1 (1 + (V ξc L ) ) is a measure of the degree
of velocity saturation.

„ NMOS Saturation Region: VDS = VDSAT ≥ VGS – VTn

W ⎡ V2 ⎤
I DSAT = κ (VDSAT ) kn′ ⎢ (VGS − VTn )VDSAT − DSAT ⎥
L ⎣ 2 ⎦
VDSAT = κ (VGS − VTn )(VGS − VTn )
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IDSAT Approximation

„ For first-order analysis the current equations for velocity

saturated devices can be approximated by assuming,
v = µn ξ for ξ < ξc
= v sat = µn ξc for ξ ≥ ξc
and
Lv sat
VDSAT = L ξc =
µn
„ IDSAT can be obtained by plugging in the saturation voltage.
I DSAT = I DS (VDS = VDSAT )
W ⎡ 2
VDSAT ⎤
= µnCox ⎢ (V − V ) V −
2 ⎥⎦
GS Tn DSAT
L ⎣
⎛ V ⎞
= v satCoxW ⎜VGS − VTn − DSAT ⎟
⎝ 2 ⎠
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 Effects of Velocity Saturation

„ For short-channel devices with

large enough (VGS-VT), κ<<1
Ö VDSAT < VGS-VT

„ Device enters saturation before

VDS reaches VGS-VT
Ö extended saturation
Ö device operates more often in
saturation.

„ IDSAT has a linear dependence

with respect to VGS
Ö reduction in the amount of
current for a given control voltage.

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Short Channel NMOS I-V Curves

Linear
dependence

NMOSFET: 0.25µm CMOS, VDD=2.5V, VTn=0.5V Ld=0.25µm W/L=1.5

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 Short Channel PMOS I-V Curves

For PMOSFETs polarities of all voltages and currents are reversed

NMOSFET: 0.25µm CMOS, VDD=2.5V, VTn=0.5V Ld=0.25µm W/L=1.5

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Unified Model

⎛W ⎞⎡ V2 ⎤
I Dn = kn′ ⎜ n ⎟ ⎢(VGSn − VTn )Vmin − min ⎥ (1+ λ VDSn ) … for VGSn ≥ VTn
⎝ Ln ⎠ ⎣ 2 ⎦
Vmin = min {(VGSn − VTn ) , VDSn , VDSATn } (use max. value for PMOSFETs)

For NMOSFETs For PMOSFETs

VGSn < VTn ⇒ cutoff region, VGSn > VTp ⇒ cutoff region,
if Vmin = VDSATn ⇒ velocity saturated if Vmax = VDSATp ⇒ velocity saturated
VDSn < (VGSn − VTn ) ⇒ linear region: Vmin = VDSn VDSp ≥ (VGSp − VTp ) ⇒ linear region: Vmax = VDSp
VDSn ≥ (VGSn − VTn ) ⇒ saturation region: Vmin = (VGSn − VTn ) VDSp < (VGSp − VTp ) ⇒ saturation region: Vmax = (VGSp − VTp )

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 Subthreshold Conduction

„ For VGS < VTn NMOSFET

conducts partially and the
current decays exponentially
(does not switch abruptly) –
subthreshold conduction or
weak inversion
„ For ideal device (n = 1), the
subthreshold slope factor,
S at room temperature is
60 mV/decade
„ For actual devices n > 1,
typically around 1.5 Ö relatively
larger voltage is required to
drop the current, i.e., higher S.
Subthreshold Slope Factor:
−1 „ Current roll-off is adversely
⎡ d log ( I DS ) ⎤ ⎛ kT ⎞ affected by increase in temp.
S =⎢ ⎥ = n⎜ ⎟ ln (10 )
⎣ dV GS ⎦ ⎝ q ⎠
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MOSFET Modeled as a Switch

„ Modeled as a switch with infinite off resistance and a finite on

resistance, Ron.
„ A simple model: use average value of resistance over operation
region of interest or even simpler, use average of resistance at the
end-points of the transition.

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 Ron for a MOSFET

„ Plot for average Ron for

VGS= VDD and VDS = VDD → VDD/2

„ Ron is inversely proportional to the

ratio, W/L
„ For VDD >> VT+VDSAT/2, Ron
becomes independent of VDD
„ Once VDD approaches VT, Ron
increases dramatically.

„ Ron for 0.25µm CMOS, with W/L=1

and L=Lmin

VDD(V) 1 1.5 2 2.5

NMOS (kΩ) 35 19 15 13
PMOS (kΩ) 115 55 38 31
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Threshold Voltage Variation

„ VT is a function of technology and the substrate bias.

„ For short channel devices it is also a function of L and VDS
„ VT decreases with L
„ VT decreases with increasing VDS (DIBL). For high enough VDS
the depletion region around drain may extend to the source
Ö IDS flows regardless of VGS.

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 Source Drain Resistance

„ For scaled MOSFETs, junctions are shallower, and

contact openings become smaller Ö parasitic resistance
in series with the drain and source regions increases.
„ Deterioration in performance since IDS for a given voltage is
reduced.

„ Improvements:
„ cover drain source regions with low-ρ material (e.g., titanium or

tungsten) to effectively reduce parasitic resistance – silicidation.

„ make the device wider than needed.

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Temperature Effects

„ Absolute value of VT decreases with an increase in

temperature. Variation is approx. -4mV/oC for high
substrate doping levels and -2mV/oC for low doping levels
Ö IDS should increase with increase in temperature, T

„ However, increase in IDS is overwhelmingly offset by the

degradation of mobility, µ
α
⎡ 295 ⎤
µ (T ) = µ ( 295o K ) ⎢
⎣ T ⎥⎦
where, α ≈ 1.5 for electrons and 1 for holes.
⇒ I DS ∝ T −α

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 Hot Carrier Effects

„ As L is reduced, the electric field at the drain of a MOSFET

in saturation increases (for a fixed VDS) Ö electrons are
imparted high enough energy to become “hot”.
„ Hot electrons can leave silicon and tunnel into the gate oxide
and get trapped therein, increasing VTn for NMOSFET and
decreasing VTp for PMOSFETs
„ Electric fields of at least 104V/cm is needed for electrons to become
hot.
„ Long-term reliability problems leading to circuit failure due to the
degradation of device parameters.
„ Improvements done in present day devices:
„ specially engineered source drain regions to bound peaks in elect. fields.
„ reduced supply voltages.

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Latchup in CMOS

„ Parasitic bipolar transistors exist in CMOS – a couple of

them form an SCR (thyristor) structure.

VDD

„ Triggering of this parasitic SCR leads to a short between

VDD and GND, usually resulting in a destruction of the
chip, or a system failure that can only be resolved by
power-down.
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 Prevention of Latchup

„ To avoid latchup, Rwell and Rsub should be minimized.

„ Provide numerous well and substrate contacts (plugs), placed close

to the source connections of the devices. Minimum of one plug per
well. One plug for every 5-8 devices in a well.
„ High current or highly susceptible devices like I/O drivers should be
surrounded by guard rings.
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MOSFET Description in SPICE3

d1 d1
g1 n1
g1
x1 x1
g2 g2
n2

GND
GND

Mn1 d1 g1 x1 GND nenh W=3.6u L=0.6u

+ ad=6.5p pd=7.2u
+ as=1.1p ps=0.6u
Mn2 x1 g2 GND GND nenh W=3.6u L=0.6u
+ ad=1.1p pd=0.6u
+ as=6.5p ps=7.2u
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 Bibliography

1. Weste & Eshraghian: “Principles of CMOS VLSI Design”,

Addison Wesley.
2. J. Rabaey: “Digital Integrated Circuits”, Prentice Hall
3. S-M. Kang & Y. Leblebici: “CMOS Integrated Circuits:
Analysis and Design”, McGraw Hill.
4. Y. Tsividis: “Mixed Analog-Digital VLSI Devices and
Technology”, McGraw Hill.

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