Instruction Execution

Instructing the Computer what to do.

Dr Philip Leong
[email protected]

Computer Architecture (P. Leong) Instruction execution (page 1)

Summary

¾ High and Low Level Languages

¾ Choices when designing a Machine Architecture

¾ The TOY1 Architecture (8086 subset)

¾ The Fetch-Execute Cycle

¾ Converting High Level language programs into

TOY1 assembly language
Computer Architecture (P. Leong) Instruction execution (page 2)
High-Level/Low-Level Languages, Machine Code
¾ High-Level Language (e.g. C++, Java, Lisp, Pascal, APL, ...)

A := B + C Assignment Statement

¾ Low-Level Language -> Assembly Language

¾ (e.g. Intel Pentium Assembly Language, Motorola 680x0 Assembly
Language, Java Bytecode)

MOV AX, [B] Assembly Language

ADD AX, [C] Instructions
MOV [A], AX

¾ (Binary) Machine Code

1A01 Machine Code Instructions (hex)

3A02
2A00
Computer Architecture (P. Leong) Instruction execution (page 3)
High Level Language

Int: A,B,C

Declare Variables
- Specify name and other properties

A := B + C

Specify operations The meaning depends on

on variables type and properties of
variables

Computer Architecture (P. Leong) Instruction execution (page 4)

Assembly Language for A:=B+C

A: Allocate 1 word
B: Allocate 1 word Allocate memory for
C: Allocate 1 word Variables.

MOV AX,[B] Specify computer

ADD AX,[C] operations on variables
MOV [A],AX
using register AX
NOTE - To obey the instructions we need to know:
The actual memory addresses of A, B & C
The codes for MOV and ADD
The Register number - if we want more than one
Computer Architecture (P. Leong) Instruction execution (page 5)
Machine Code for A:=B+C

MOV AX,[B] 0001 0011 1111 1101

ADD AX,[C] 0011 0011 1111 1110
MOV [A],AX 0010 0011 1111 1100

All information to execute the instruction is

immediately available to the CPU.

Computer Architecture (P. Leong) Instruction execution (page 6)

Architectural Design
- Number of Operands X:=Y+Z

3 Address machine Add Y, Z, X

Op Src1 Src2 Dest

2 Address machine Add Y, Z Store X, Y

Acc := Y+Z X := Acc
One operand Implicit or Y := Y+Z X := Y

1 Address machine Load Y Add Z Store X

Acc := Y Acc:=Acc+Z X:= Acc
Two Operands Implicit - Register is always Acc

0 Address machine Push Y, Push Z, Add, Pop X

All operands implicit (taken from the Stack)

- but need instructions to fill and empty the stack from memory.
Computer Architecture (P. Leong) Instruction execution (page 7)
Architectural Design
- Instruction Length

Memory
M x 16-Bit words, Word addressed

Length of an Instruction?
8-bits, 10-bits, 16-bits, 18-bits, 24-bits, 32-bits?

Number of CPU Registers? 1, 2, 3, 4, 5, 6, ..?

Number of Operations? Add, Sub, Load, Goto, .?

Instruction length =
Opcode Bits + Reg Bits + Operand(s) Bits
Computer Architecture (P. Leong) Instruction execution (page 8)
The Fetch-Execute Cycle - repeat forever
¾ Fetch the Instruction (=load or read from memory)

¾ Increment the Program Counter

¾ Decode the Instruction

¾ Fetch the Operands

¾ Perform the Operation

¾ Store the Results

¾ Repeat Forever

Computer Architecture (P. Leong) Instruction execution (page 9)

Fetch (load or read) the Instruction
What is an Instruction?
Opcode Operand(s)
Where is the Instruction? Memory
Why does it need to be fetched?
Speed Need to access each part of instruction
How does the computer know where it is?
CPU Register holding a
Program Counter (PC) memory address
Where is the fetched instruction put?
Instruction Register (IR) Internal CPU register
Computer Architecture (P. Leong) Instruction execution (page 10)
The Toy1 Architecture
¾ Maximum of 1024 x 16-bit memory words
Memory is Word Addressed

¾ Two’s Complement Integer Representation

¾ 4 General Purpose Registers (16-bit) : AX, BX, CX, DX

¾ Up to 16 different “Instructions”, e.g. MOV, ADD, SUB

Computer Architecture (P. Leong) Instruction execution (page 11)

Toy1 Instruction Set
¾ MOV <Register> , <Memory Address>
<Register> := Memory [ <Memory Address> ]

¾ MOV <Memory Address >, <Register> (STORE)

Memory [ <Memory Address> ] := <Register>

¾ ADD <Register> , <Memory Address>

<Register> := <Register> + Memory [ <Memory Address> ]

¾ SUB <Register> , <Memory Address>

<Register> := <Register> - Memory [ <Memory Address> ]

Computer Architecture (P. Leong) Instruction execution (page 12)

Toy1 Instruction Format

Assembly Instruction e.g. ADD CX, [C]

Machine Code OPCODE REG ADDRESS

4-bit 2-bit 10-bit

Instruction Fields
¾ OPeration CODE (Selects CPU Instruction)
¾ REGister (Specifies 1st Operand for Instruction)
¾ ADDRESS (Specifies 2nd Operand for Instruction)

Computer Architecture (P. Leong) Instruction execution (page 13)

Other Possibilities for Format

ADD CX, [C] OPCODE ADDRESS REG

4-bit 10-bit 2-bit

REG ADDRESS OPCODE

2-bit 10-bit 4-bit

ADD CX, DX OPCODE REG REG OPCODE REG REG

4-bit 2-bit 2-bit 4-bit 2-bit 2-bit

Computer Architecture (P. Leong) Instruction execution (page 14)

Instruction Field Encoding
OPCODE REG ADDRESS

4-bit 2-bit 10-bit 16-bit Instruction

¾ OPCODE MOV 0001

(4-bit) MOV 0010 ; i.e. STORE
ADD 0011
SUB 0100
¾ REG Register AX 00
(2-bit) Register BX 01
Register CX 10
Register DX 11
¾ ADDRESS 10-bit Memory Word Address
Computer Architecture (P. Leong) Instruction execution (page 15)
Memory Placement (Program)
Assembly Machine Instruction Memory
Instruction OP REG ADDRESS Address

MOV CX, [201H] 0001 10 10 0000 0001 00 1000 0000

1 A 0 1 0 8 0H

ADD CX, [202H] 0011 10 10 0000 0010 00 1000 0001

3 A 0 2 0 8 1H

MOV [200H], CX 0010 10 10 0000 0000 00 1000 0010

2 A 0 0 0 8 2H

MEMORY
Computer Architecture (P. Leong) Instruction execution (page 16)
Memory Placement (Data)
Assembly Data Memory
Instruction Address

A=0 0000 0000 0000 0000 10 0000 0000

0 0 0 0 2 0 0H

B=9 0000 0000 0000 1001 10 0000 0001

0 0 0 9 2 0 1H

C=6 0000 0000 0000 0110 10 0000 0010

0 0 0 6 2 0 2H

MEMORY
Computer Architecture (P. Leong) Instruction execution (page 17)
CPU Organisation
CPU AX 000
BX Address 001

CX Bus 002
I 003
DX n
t
ALU e
Input Reg1 Data
r Bus
Output Reg RAM
n
Input Reg2 a
l
Control
Program Counter B Bus
u
Instr. Decoder Instr. Register s
3FD
3FE
Control Unit 3FF

Computer Architecture (P. Leong) Instruction execution (page 18)

MOV CX,[201H] CX:=Memory[201H]
CPU 000
001
080H 002
CX 003

ALU

RAM

080H
080H
PC 080H 0
Instr. Decoder
0 3FD
0 3FE
Control Unit 3FF
1
Computer Architecture (P. Leong) Instruction execution (page 19)
MOV CX,[201H] CX:=Memory[201H]
CPU 000
001
080H 002
CX 003

ALU

RAM

PC 080H + 1 0
Instr. Decoder
3FD
3FE
Control Unit 3FF
2
Computer Architecture (P. Leong) Instruction execution (page 20)
MOV CX,[201H] CX:=Memory[201H]
CPU 000
001
080H 002
CX 003

ALU

RAM

0
PC 081H
Instr. Decoder
3FD
3FE
Control Unit 3FF
3
Computer Architecture (P. Leong) Instruction execution (page 21)
MOV CX,[201H] CX:=Memory[201H]
CPU 000
001
080H
CX
080 1A01H
1A01
081 3A02H
ALU 082 2A00H

RAM

200 0000
0 201 0009
PC 081H 202 0006

Instr. Decoder
3FD
3FE
Control Unit 3FF
4
Computer Architecture (P. Leong) Instruction execution (page 22)
MOV CX,[201H] CX:=Memory[201H]
CPU 000
001
201H
CX
080 1A01H
081 3A02H

201H
ALU 082 2A00H
1A01H 1A01
RAM

1A01H
200 0000
201 0009
PC 081H 0 202 0006
1A01H
1A01H 1A01H
0 3FD
1, 2, 201H 201H 3FE
1, 2, 201H 3FF
0 5
Computer Architecture (P. Leong) Instruction execution (page 23)
MOV CX,[201H] CX:=Memory[201H]
CPU 000
201H 001
0009 201H
CX 0009
080 1A01H
081 3A02H

0009
ALU 082 2A00H
0009 0009
RAM

200 0000
0 201 0009
PC 081H 0 202 0006

1A01H
3FD
3FE
1, 2, 201H 3FF
6
Computer Architecture (P. Leong) Instruction execution (page 24)
ADD CX,[202H] CX:=CX+Memory[202H]
CPU 000
001
081H
CX 0009
080 1A01H
081 3A02H

081H
ALU 082 2A00H

RAM

200 0000
081H 201 0009
PC 081H 0 202 0006

0 3FD
0 3FE
3FF
7
Computer Architecture (P. Leong) Instruction execution (page 25)
ADD CX,[202H] CX:=CX+Memory[202H]
CPU 000
001
081H
CX 0009
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 081H + 1 0 202 0006

3FD
3FE
3FF
8
Computer Architecture (P. Leong) Instruction execution (page 26)
ADD CX,[202H] CX:=CX+Memory[202H]
CPU 000
001
202H 081H
0009
CX 0009
0009

202H 0009
080 1A01H
081 3A02H
3A02
ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM

3A02H
200 0000
201 0009
PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
0 3FD
3, 2, 202H 202H 3FE
3, 2, 202H 3FF
0 9
Computer Architecture (P. Leong) Instruction execution (page 27)
ADD CX,[202H] CX:=CX+Memory[202H]
CPU 000
001
000FH 202H 202H
CX 000FH
0009

000FH
080 1A01
081 3A02
ALU 082 2A00
0009 0006 0006
000FH ADD RAM

000FH
0006
000FH 0006
200 0000
201 0009
PC 082H 0 0 202 0006

3A02H
3FD
3FE
3, 2, 202H 3FF
10
Computer Architecture (P. Leong) Instruction execution (page 28)
MOV [200H],CX Memory[200H]:=CX
CPU 000
001
082H
CX 000FH
080 1A01H
081 3A02H

082H
ALU 082 2A00H

RAM

200 0000
082H 201 0009
PC 082H 0 202 0006

0 3FD
0 3FE
3FF
11
Computer Architecture (P. Leong) Instruction execution (page 29)
MOV [200H],CX Memory[200H]:=CX
CPU 000
001
082H
CX 000FH
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 082H + 1 0 202 0006

3FD
3FE
3FF
12
Computer Architecture (P. Leong) Instruction execution (page 30)
MOV [200H],CX Memory[200H]:=CX
CPU 000
001
200H 082H
000FH
CX 000FH

200H 000FH
000F
080 1A01H
081 3A02H
ALU 082 2A00H
2A00
000FH 2A00H
RAM

2A00H
200 0000
201 0009
PC 083H 1 1 202 0006
2A00H
2A00H 2A00H
1 3FD
2, 2, 200H 200H 3FE
2, 2, 200H 3FF
1 13
Computer Architecture (P. Leong) Instruction execution (page 31)
MOV [200H],CX Memory[200H]:=CX
CPU 000
200H 200H 001

CX 000FH
080 1A01H
081 3A02H
ALU 082 2A00H
00FH 00FH
RAM

200 000FH
0000
1 1 201 0009
PC 083H 202 0006

3FD
3FE
3FF
14
Computer Architecture (P. Leong) Instruction execution (page 32)
The Fetch-Execute Cycle - repeat forever
¾ FI - Fetch the Instruction (=load or read from memory) and Increment the
Program Counter
¾ IR <- MEM[PC], PC <- PC + 1

¾ DI - Decode the Instruction

¾ {look at IR}

¾ CO - Calculate the Operand address

¾ OA = IR[9:0]

¾ FO - Fetch the Operands

¾ A <- MEM[OA]

¾ EI - Execute the Instruction {ADD, SUB, MOV operations only}

¾ Rx <- Rx op A {op is either ADD, SUB or Rx}

¾ WO - Store the Results {STORE operation only}

¾ MEM[OA] <- Rx

Computer Architecture (P. Leong) Instruction execution (page 33)

Think about

1. High level languages, Machine Code

and Assembly Language, strengths and weaknesses.

2. How instructions are represented/coded

3. Three, Two, One, and Zero address architectures

4. Designing an Instruction set

Instruction format and interpretation

Computer Architecture (P. Leong) Instruction execution (page 34)

Think About
5. Fetch-Execute Cycle
6. Assembly Languages
7. Program Representation: Instructions, Instruction Fields,
Instruction Formats
8. CPU Components: Registers, ALU, Control Unit
9. Registers: General Purpose Registers, Program
Counter (PC), Instruction Register (IR),
ALU Registers
10. Buses: Internal, Address, Data, Control

Computer Architecture (P. Leong) Instruction execution (page 35)

Think About

11. What would an instruction with the new addressing mode mean
if applied to the unconditional Jump?

12. Suggest how the wasted instruction bits could be profitably

used.

13. Suggest useful instructions which could be allocated to the

unused opcodes. Why do you consider them useful?

Computer Architecture (P. Leong) Instruction execution (page 36)

Think about

14. Translating High-level Language statements to Assembly Language

instructions (Compilation)

15. Allocating Variables to Registers and Main Memory

16. Branching and Looping

17. Indirect Addressing

Computer Architecture (P. Leong) Instruction execution (page 37)