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Serial Binary Adder

The document describes four different digital circuit designs - a serial binary adder using a Mealy model, a pattern detector using a Mealy model, a pattern detector using a Moore model, and a serial binary adder using a Moore model. For each design, it provides the Verilog code for the circuit module and a testbench module to simulate and test the design behavior.

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788 views16 pages

Serial Binary Adder

The document describes four different digital circuit designs - a serial binary adder using a Mealy model, a pattern detector using a Mealy model, a pattern detector using a Moore model, and a serial binary adder using a Moore model. For each design, it provides the Verilog code for the circuit module and a testbench module to simulate and test the design behavior.

Uploaded by

bcemailid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SERIAL BINARY ADDER - MEALY MODEL

PROGRAM
module serialmealy(clk,rst,inp,outp);
input clk,rst;
input [1:0] inp;
output outp;
reg state;
reg outp;
always @(posedge clk,posedge rst)
begin
if(rst==1)
state<=0;
else
begin
case(state)
1'b0:
begin
if(inp==2'b00)
begin
state<=1'b0;
outp<=0;
end
else if(inp==2'b01||inp==2'b10)
begin
state<=1'b0;
outp<=1;
end
else if(inp==2'b11)
begin

state<=1'b1;
outp<=0;
end
end
1'b1:
begin
if(inp==2'b00)
begin
state<=1'b0;
outp<=1;
end
else if(inp==2'b01||inp==2'b10)
begin
state<=1'b1;
outp<=0;
end
else if(inp==2'b11)
begin
state<=1'b1;
outp<=1;
end
end
endcase
end
end
endmodule
TESTBENCH
module serialmealy_tb();
reg clk,rst;

reg [1:0] inp;


wire outp;
serialmealy sm(clk,rst,inp,outp);
initial
begin
forever
begin
clk<=0;
#50 clk<=1;
#50 clk<=0;
end
end
initial
begin
rst=1;
#50 rst=0;
#50 inp=2'b00;
#50 inp=2'b01;
#50 inp=2'b10;
#50 inp=2'b11;
#50 inp=2'b01;
#50 inp=2'b11;
#50 inp=2'b00;
#50 inp=2'b10;
end
endmodule

WAVEFORM

PATTERN DETECTOR MEALY MODEL


PROGRAM
module mealypattern(out,inp,rst,clk);
output out;
reg out;
input clk,rst,inp;
reg[1:0] state;
always@(posedgeclk,posedgerst)
begin
if(rst==1)
state<=2'b00;
else
begin
case(state)
2'b00:
begin
if(inp==0)
begin
state<=2'b00;
out<=0;
end
else
begin
state<=2'b01;
out<=0;
end
end
2'b01: begin
if(inp==0)

begin
state<=2'b10;
out<=0;
end
else
begin
state<=2'b01;
out<=0;
end
end
2'b10: begin
if(inp==0)
begin
state<=2'b11;
out<=0;
end
else
begin
state<=2'b01;
out<=0;
end
end
2'b11: begin
if(inp==0)
begin
state<=2'b00;
out<=0;
end
else

begin
state<=2'b01;
out<=1;
end
end
endcase
end
end
endmodule

TESTBENCH

module mealypattern_tb();
reg inp,rst,clk;
wire out;
mealypattern m1(out,inp,rst,clk);
initial
begin
forever
begin
clk<=0;
#50 clk<=1;
#50 clk<=0;
end
end
initial
begin
rst=1;
#100 rst=0;

#100 inp=1;
#100 inp=0;
#100 inp=0;
#100 inp=1;
#100 inp=0;
#100 inp=1;
#100 inp=0;
#100 inp=0;
#100 inp=1;
#100 inp=0;
#100 inp=1;
end
endmodule

WAVEFORM

PATTERN DETECTOR MOORE MODEL


PROGRAM
module patternmoore(out,inp,rst,clk);
output out;
reg out;
input clk,rst,inp;
reg[2:0] state;
always@(posedgeclk,posedgerst)
begin
if(rst==1)
state<=3'b000;
else
begin
case(state)
3'b000:
begin
if(inp==0)
state<=3'b000;
else
state<=3'b001;
end
3'b001:
begin
if(inp==0)
state<=3'b010;
else
state<=3'b001;
end
3'b010:

begin
if(inp==0)
state<=3'b011;
else
state<=3'b001;
end
3'b011:
begin
if(inp==0)
state<=3'b000;
else
state<=3'b100;
end
3'b100:
begin
if(inp==0)
state<=3'b010;
else
state<=3'b001;
end
endcase
end
end
always@(posedgeclk, posedgerst)
begin
if(rst==1)
out<=0;
else
if(state==3'b000||state==3'b001|state==3'b010|state==3'b011)

out<=0;
else if(state==3'b100)
out<=1;
end
endmodule

TESTBENCH
module patternmoore_tb();
reg inp,rst,clk;
wire out;
patternmoore m1(out,inp,rst,clk);
initial
begin
forever
begin
clk<=0;
#50 clk<=1;
#50 clk<=0;
end
end
initial
begin
rst=1;
#100 rst=0;
#100 inp=1;
#100 inp=0;
#100 inp=0;
#100 inp=1;
#100 inp=0;

#100 inp=1;
#100 inp=0;
#100 inp=0;
#100 inp=1;
#100 inp=0;
#100 inp=1;
end
endmodule

WAVEFORM

SERIAL BINARY ADDER - MOORE MODEL


PROGRAM
module serialmoore( clk, rst, inp, outp);
input clk,rst;
input [1:0] inp;
output outp;
reg [1:0] state;
reg outp;
always @(posedgeclk,posedgerst)
begin
if(rst ==1)
state<=2'b00;
else
begin
case(state)
2'b00:
begin
if(inp==2'b00)
state<=2'b00;
else if(inp==2'b01||inp==2'b10)
state<=2'b10;
else if(inp==2'b11)
state<=2'b01;
end
2'b01:
begin
if(inp==2'b00)
state<=2'b10;
else if(inp==2'b01||inp==2'b10)

state<=2'b01;
else if(inp==2'b11)
state<=2'b11;
end
2'b10:
begin
if(inp==2'b00)
state<=2'b00;
else if(inp==2'b01||inp==2'b10)
state<=2'b10;
else if(inp==2'b11)
state<=2'b01;
end
2'b11:
begin
if(inp==2'b00)
state<=2'b10;
else if(inp==2'b01||inp==2'b10)
state<=2'b01;
else if(inp==2'b11)
state<=2'b11;
end
endcase
end
end
always@(posedgeclk, posedgerst)
begin
if(rst==1)
outp<=0;

else
if(state==2'b11||state==2'b10)
outp<=1;
else
outp<=0;
end
endmodule

TESTBENCH

module serialmealy_tb();
reg clk,rst;
reg [1:0]inp;
wire outp;
serialmealy sm(clk,rst,inp,outp);
initial
begin
forever
begin
clk<=1;
#50 clk<=0;
#50 clk<=1;
end
end
initial
begin
rst=1;
#50 rst=0;
#50 inp=2'b00;

#50 inp=2'b01;
#50 inp=2'b10;
#50 inp=2'b11;
#50 inp=2'b01;
#50 inp=2'b11;
#50 inp=2'b00;
#50 inp=2'b10;
end
endmodule

WAVEFORM

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