2.FPGA Implementation of An Advanced Encoding and Decoding Architecture of Polar Codes

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2.FPGA Implementation of An Advanced Encoding and Decoding Architecture of Polar Codes

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Softroniics

FPGA Implementation of an Advanced Encoding and Decoding

Architecture of Polar Codes
Abstract:
Polar code, newly formulated by Erdal Arikan, has got a wide recognition from the
information theory community. Polar code achieves the capacity of the class of symmetric binary
memory less channels. In this paper, we propose efficient hardware architecture on a FPGA
platform using Xilinx Virtex VI for implementing the advanced encoding and decoding schemes.
The performance of the proposed architecture out performs the existing techniques such as:
successive cancellation decoder, list successive cancellation, belief propagation etc; with respect
to bit error rate and resource utilization.

Existing Method:
A refined performance of polar codes by using Belief propagation decoding algorithm is
suggested in but in this method it is arduous to know the ideal scheduling of messages and it is
less efficient on other channels except Binary Erasure Channel (BEC). the existing techniques
such as: successive cancellation decoder, list successive cancellation, belief propagation etc; with
respect to bit error rate and resource utilization.

Proposed Method:
In this paper, we propose efficient hardware architecture on a FPGA platform using
Xilinx Virtex VI for implementing the advanced encoding and decoding schemes. Polar codes,
proposed by Arikan, is an alternate proof of Shannon's noisy coding theorem

with respect to

binary input symmetric memory less channels , he has also proposed successive cancellation and
iterative decoding for polar codes. The major reason that motivated to end up in a detailed study
of polar encoders and decoders is the lower complexity and its performance in high signal-toratio codes.

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Applications:
1. Digital Signal Processing
2. Encoding and decodingetc.
Advantages:
1. Lower complexity
2. Speed, area

System Configuration:In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration

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