Scribd
Upload
431 views6 pages

Question Bank DSD

This document contains question banks for 5 modules covering digital system design and Verilog HDL. The modules cover topics such as data types in Verilog, coding combinational logic circuits, sequential circuits and finite state machines, and modeling and testing circuits in Verilog. Example questions include writing code for circuits like multiplexers, decoders, adders and registers, designing sequential circuits to detect sequences, and modeling circuits like counters and shifters in Verilog along with writing test benches.

Uploaded by

Jithinmvijayan Vijayan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
431 views6 pages

Question Bank DSD

This document contains question banks for 5 modules covering digital system design and Verilog HDL. The modules cover topics such as data types in Verilog, coding combinational logic circuits, sequential circuits and finite state machines, and modeling and testing circuits in Verilog. Example questions include writing code for circuits like multiplexers, decoders, adders and registers, designing sequential circuits to detect sequences, and modeling circuits like counters and shifters in Verilog along with writing test benches.

Uploaded by

Jithinmvijayan Vijayan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 6

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

EC010 503 DIGITAL SYSTEM DESIGN

QUESTION BANK
FACULTY: JISHA M VIJAYAN

MODULE 1
1.What are the different data types in verilog HDL?

2.Write the verilog code for a 2:4 decoder circuit?


3.Design and implement 16:1 multiplexer using two 8:1 MUX in verilog HDL
4.Design and implement a full adder using verilog HDL
a)gate level modeling
b)structural modeling(using half adder)
5.Differentiate between behavior and structural model used in verilog HDL.
6.Write verilog code for a 8:1 MUX and explain.
7.Describe all the operators in Verilog HDL with the help of suitable examples
8.Write the verilog code for a positive edge sensitive 8 bit D-type register with synchronous
set and reset inputs
9.Using assign statement, write verilog code for the octal 2-to-1 MUX.
10.Write a verilog description for a 101 sequence detector with an a input pin and a w
output.
11.Write verilog code for a 4-to-1 MUX with a tri-state output and an active low output
enable input.The MUX has 4 data inputs(d0,d1,d2,d3) and two select inputs(s1,s0).Use
case and if statements.
12.Write verilog code for a cascadable 4-to-2 priority encoder .Your circuit should have an
enable input, four data inputs,an enable output, an interrupt output and two source id
outputs.All inputs and outputs must be active high. For cascading purposes and to be able to
use wired-OR logic,use tri-state for ur id outputs. Adjust the details of your design for a
better cascading capability.

MODULE 2
1.Draw the structure of 8:1 decoder
2. Realise the functions f1(x,y,z) = m(1,2,4,5) and f2(x,y,z) = m(1,5,7) using MUX.
3.Simplify the given Boolean function F(A,B,C,D) = m(0,1,2,8,10,11,14,15) using Quine
Mc Clusky algorithm.
4.a) With a neat block diagram, explain PLA.
( 4 marks)
b)Implement the functions, f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6) using 3X4X2
PLA ( true/compliment method).
5.Draw the structure of a 3-to-8 decoder

6.Illustrate how PLA can be used for combinational logic design with reference to
f=m(0,1,3,4).
7.Explain
the

Quine-Mc

Cluskey

algorithm

to

implement

f=(0,2,5,7,9,11,13,15,16,18,21,23,25,27,29,31)
8.Implement the following Boolean function using PLA with both true and complemented
outputs. Map to arrive at a design with a minimal number of product terms in the PLA. Write
PLA table. F1=(3,6,7),F2=(0,1,2,6,7),F3=(0,1,3,4,5)
9.How can a decoder be used as a de-multiplexer? Explain.
10.Implement f=(1,3,4,6,7) using decoder minimizing the number of inputs tobe summed.
11.Mention the advantages and disadvantages of Quine McCluskey method for obtaining the
primeimplicants of a given Boolean function, obtain all the prime implicants of the function
f=m(4,5,9,11,12,14,15,27,30)+d(1,17,25,26,31) using Quine McCluskey method.
12.Explain a general structure of PLA. Explain its advantages.Implement f=m(0,1,2,4,5)
using 3x4x2 PLA. Draw the logic diagram

MODULE 3
1.Define metastability.
2.With a neat block diagram, explain Mealy and MOORE model.
3.Design a clocked synchronous sequential circuit which detects the following sequence
0110/1001.
4.Design and implement a serial binary adder as a Mealy network.
5. Define synchronizer failure and metastability.
6.Design a sequence detector to detect the sequence 101 from 10101.
7.Show the design of a Mealy machine sequence detector that detects the 100 and 001
sequences on its serial input.Provide an asynchronous reset input that starts the detector in its
first state.
8.A network produces a 1 output if and only if the current input and the previous three
inputs correspond to either of the sequences 0110 or 1001. The output 1 is to occur at the
time of the fourth inputof the recognized sequence. Outputs of 0 are to be produced at all
other times. Construct the state diagram.
9.Draw the general model for a Mealy network using clocked D flip-flops.
10.Obtain the state table and state diagram for the sequential circuit shown in figure

11.Design a sequence detector to detect the sequence 101 from 10101. Draw the logic
diagram of your circuit.
12. Design a sequential circuit with two D flip-flops A and B, and one input x. When x=0, the
state of the circuit remains the same. When x=1, the circuit passes through the state
transitions from 00 to 01 to 11 to 10 and back to 00 and repeats. Draw the logic circuit
diagram.

MODULE 4

1. Explain ASM in brief.


2. Explain the relevance of implication table in state machine concepts.
3.Explain state table reduction and state assignment technique using the state table given
below.
Next State
Output (z)
Present
Input (x)
Input (x)
State
X =0
X=1
X=0
X=1
*A
A
B
0
0
B
D
C
0
1
C
F
E
0
0
D
D
F
0
0
E
B
G
0
0
F
G
C
0
1
G
A
F
0
0

4.a) Write notes on ASM charts. b) Draw the ASM chart for a MOD 8 UP/DOWN counter.
5.When do we say that two states in a state diagram are equivalent?
6.What are the different state machine styles? Which is better? Explain advantages and
disadvantages.

7.Construct a state diagram for two circuits both having 3states s1,s2,s3, and a single control
input which gives rise to 2 input conditions i1 and i2.
a)The first is divide by 3 up-counter which behaves normally when the control input is 0
and the circuit is reset to state s1 on the next clock pulse if the control input is 1.
b)The other circuit is an up-down divide by 3 counter whose direction is determined by the
logic values of control input.
8.Design a clocked sequential circuit using T flip flops for the state diagram shown below

9.What is a state assignment? When two states in a state diagram are said to be equivalent
states?
10.Reduce the following state table.
Present
State
*A
B
C
D
E
F
G
H
I

Next State
Input (x)
X =0
X=1
D
C
H
A
E
D
D
C
B
G
E
D
A
F
C
A
G
E

Output (z)
Input (x)
X=0
X=1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1

11.Design a synchronous circuit that has a single input variable and a single output variable.
The input data are received serially. Cause the first output bit to be the same value as the first
input bit in the serial string (ie, if x=0, then z=0; if x=1, then z=1). Output z is to change
thereafter only when 3 consecutive input bits have the same value. For example
X=00100111011000
Z=00000001111110
(a) Construct an ASM diagram describing the system, decide whether a Mealy or Moore
machine produces the fewest number of states.
(b) Create a state table, and reduce it.

12.Design a sequential circuit for the given state diagram using JK flip-flops.

MODULE 5

1. What is a test bench? What is its relevance in Verilog?


2. Explain the different types of modelling in Verilog.
3.
4.
5.
6.
7.

Model a 4 bit linear feedback shift register using Verilog HDL.


Model a 4 bit binary multiplier using Verilog HDL
Explain path sensitization method of finding a test vector.
With an example, describe the test bench used for testing a combinational circuit
Design a reversible shift register whose stages are connected in ring form, making use
of the following specifications:
(a) Each clock pulse will cause the register to shift when a control signal LR is 1
and is to shift right when the control signal LR is 0.
(b) Shift register is to be loaded in parallel from data appearing on 4 input pins under
the control of a signal LS which will come loading when true and shifting when
false
8.Model a 4 bit barrel shifter using Verilog HDL
9.What is a verilog test bench? What are its functions?
10.Write the verilog code for the following up-down counter. The counter has a
u input that controls its count direction. If u=1, it counts 010, 011, 101, 011, 111,
001,.. If u=0, it counts this same sequence in the opposite direction.
11.Write a Verilog description for a multiplier bit. Using this multiplier bit write a
verilog code for a 4 x 4 array multiplier.
12. What is a barrel shifter? Explain its principle. Using verilog HDL, model a 4bit barrel shifter?

You might also like