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VLSI

1. The document discusses application specific integrated circuits (ASICs). It defines an ASIC as an integrated circuit customized for a particular use. 2. There are several types of ASICs discussed, including full custom, semi-custom, and programmable. Full custom ASICs have all logic cells and mask layers customized. Semi-custom have some predesigned logic cells and customized mask layers. 3. The design cycle for an ASIC involves design entry, functional simulation, synthesis, design verification, and layout. Synthesis converts the RTL description to gates through optimization of area, timing and power. Verification ensures functional correctness through simulation and emulation.

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Ramesh Lakshmanan
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174 views26 pages

VLSI

1. The document discusses application specific integrated circuits (ASICs). It defines an ASIC as an integrated circuit customized for a particular use. 2. There are several types of ASICs discussed, including full custom, semi-custom, and programmable. Full custom ASICs have all logic cells and mask layers customized. Semi-custom have some predesigned logic cells and customized mask layers. 3. The design cycle for an ASIC involves design entry, functional simulation, synthesis, design verification, and layout. Synthesis converts the RTL description to gates through optimization of area, timing and power. Verification ensures functional correctness through simulation and emulation.

Uploaded by

Ramesh Lakshmanan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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1

Application Specific
Integrated Circuits
2

,Presented by
ANBURAJ(13BEC2009)
S.GIGNESH KUMAR(13BEC2043)
K.DHIVYA(13BEC2032)
R.GOWTHAMI(13BEC2054)
,GUIDED BY

Mrs.M.Arulpriya
[Asst.prof (ECE dept.)]

?What is an ASIC
An application-specific integrated circuit
(ASIC) is an integrated circuit (IC)
customized for a particular use

INTRODUCTION
.It is non-standard integrated circuit
A Structured ASIC falls between an FPGA and a Standard Cell.based ASIC
It contains very large part of the electronic needed on a single
.integrated circuit
.Structured ASICs are used mainly for mid-volume level designs

TYPES OF ASICs

FULL CUSTOM
A Full custom ASIC is one which includes some (possibly all)
logic cells that are customized and all mask layers that are
.customized
A microprocessor is an example of a full-custom IC
Full-custom ICs are the most expensive to manufacture and to
design
The manufacturing lead time (the time required just to make an
IC not including design time) is typically eight weeks for a full. custom IC

SEMI-CUSTOM
ASICs , for which all of the logic cells are predesigned and some
(possibly all) of the mask layers are customized are called
.semi custom ASICs
Using the predesigned cells from a cell library makes the
.design , much easier
There are two types of semicustom ASICs
Standard-cellbased ASICs)i(
.Gate-arraybased ASICs)ii(

STANDARD CELL
In semiconductor design,
standard cell methodology is a
method of designing
application-specific integrated circ
uits
(ASICs) with mostly digital-logic
features.
Using logic gates such as AND
,OR,NOT,etc

GATE ARRAY BASED


In a gate array (sometimes abbreviated GA) or gatearray based ASIC the transistors arepredefined on the
.silicon wafer
.There are three types of Gate Array based ASICs
.
Channeled gate arrays)i(
.Channel less gate arrays)ii(
.Structured gate arrays)iii(
10

CHANNELED GATE ARRAY


In a channeled gate array space is left between the rows
.of transistors for wiring
A channeled gate array is similar to a CBIC. Both use
the rows of cells separated by channels used for
.
interconnect

CHANNELLESS GATE ARRAY


This channel less gate-array architecture is now more
.widely used
The interconnect uses predefined spaces between rows
.of base cells
11

STRUCTURED GATE ARRAY


This design combines some of the features of CBICs
and MGAs. It is also known as an embedded gate
array or structured gate array(also called as master
.slice or master image)
An embedded gate array gives the improved area
efficiency and increased performance of a CBIC but
.with the lower cost and faster turn around of an MGA

12

PROGRAMMABLE

13

THE DESIGN CYCLE FOR AN


:ASIC AS FOLLOWS
Design entry
Functional simulation
Synthesis
Design verification
Layout

14

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:DESIGN DESCRIPTION
At initial stage of design process designer
provides a Behavioral description of the
functionality intended.
Behavioral model does not care about the
structure of the design, and does not include
timing information.

16

.Design Description cont


RTL description: (Register Transfer Level)
In this model the entire design is split into registers
with flow of information between these registers at
each clock cycle.
All the registers are updated at the same time in a clock
cycle.
RTL captures the data flow but fails to give a good
description of control flow.

17

.Design Description cont


Structural Description
Structural description consists of a network of instances
of logic gates and registers described by a technology
library.
Technology library is a description of simple AND, OR,
NOT and complicated multiple functionality cells.
The description of a cell includes its geometry, delay
and power characteristics.

18

:FUNCTIONAL SIMULATION
There are mainly two classes of logic
simulators:
compiled code logic simulators.
event-driven logic simulators.

19

ASIC SYNTHESIS:
RTL Synthesis involves three major steps:
1. Transition from RTL description into gates
and flip-flops. (in order to reduce number of
gates in the design)
2. Optimization of logic.
3. Placement and routing of optimized netlist.

20

.ASIC Synthesis cont

Area Optimization:
With shrinking system size ASIC
should be able to accommodate
maximum functionality in
minimum area.
Area can be optimized by having
lesser number of cells and by
replacing multiple cells with
single cell that includes both
functionality.
21

.ASIC Synthesis cont

Timing Optimization:
Designer specifies maximum delay between
primary input and primary output.

Power Optimization:
Development of hand-held devices has led to reduction of
battery size and hence low power consuming systems.
Low power consumption has become a big requirement
for lot of designers.
22

.ASIC Synthesis cont


Transition from RTL to FSM to Gates:

First step in synthesis process is to


convert a given RTL into a finite
state machine (FSM), in order to
reduce number of states.
Some of the common transformations
applied to FSM are constant
propagation, gate merging, dead code
elimination, arithmetic merging.

RTL to FSM(or graph)

Next step is to generate hardware.


FSM(graph) to Gates.
23

VERIFICATION
Biggest challenge in IC design is verification because the cost
of single error is huge.
One type of verification methods include Simulation, and
Emulation and hardware acceleration.
Emulator is a hardware device that can be used to emulate a
piece of hardware functionality. It is commonly used as a
debugging tool to test a system under development for
functional correctness.

24

Gate-level simulation and Extraction

Placement and routing involves placement of modules on chip


area and routing interconnect between various modules.
Various aspects of signal integrity include:
Technology scale down:
Aluminium has been replaced with material like copper with
lower resistance.
CrossTalk: When two wire segments are closer ,signal on one wire
may weaken due to electromagnetic effects of signal carried by
other wire. With diminishing technology size Crosstalk is major
contributor to high speed IC defects.

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