Pessimism Reduction in Crosstalk Noise Aware STA

M. Becer , V. Zolotov , R. Panda , A. Grinshpon , I. Algor , R. Levy , C. Oh

CLK

Design Automation, Littleton, MA Email: murat@clkda.com

IBM, Yorktown Heights, NY
Freescale Inc., Austin, TX
Nascentric, Austin, TX

Abstract High performance circuits are facing increasingly

severe signal integrity problems due to crosstalk noise and
crosstalk noise awareness has become an integral part of static
timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net
basis and in a pessimistic way, without considering the overlap
bounds of the victim and aggressor timing windows and realistic
delay impact on early and late signal arrival times. Since crosstalk
induced delay on indivudial nets contribute cumulatively on data
and clock paths, even small amounts of pessimism in computation
can add up to produce several unrealistic timing violations.
Unlike glitch noise analysis where noise often attenuates during
propagation, quality of delay noise analysis is severely affected
by any pessimism in noise estimation and can unnecessarily cost
valuable silicon and design resources for fixing unreal violations.
In this paper, we propose two temporal techniques to reduce pessimism in crosstalk noise aware STA. The first method, effective
delay noise, is a net based method where the exact overlap points
of victim and aggressor timing windows are considered to obtain
the part of delay noise that actually impacts early and late signal
arrival times. The second method, path based delay noise, is a
path based method where the reduced arrival uncertainty of the
nets of a given path are utilized for pessimism reduction. We also
propose a novel uncertainty propagation technique as part of
the second method, which results in an iteration free crosstalk
noise aware STA of the path with significantly reduced pessimism.
The two techniques are combined in a proposed methodology that
is compatible with existing industrial static timing analyzers with
very little computational overhead compared to the traditional
noise aware STA and a significant improvement in eliminating
unreal violations. The proposed techniques resulted in 77%
reduction of worst case negative slack and 57% reduction in the
number of failing paths in the setup analysis of a 90nm industrial
design.

I. I NTRODUCTION
Capacitive crosstalk noise continues to be a critical design
issue in both block level designs and at the chip integration
level of SoC (system on chip) systems. At the block level,
whether the design is a synthesized block, a custom macro
or a dense memory structure, it is necessary to design for
and verify the functionality of the part with crosstalk noise
taken into account. Even though the net lengths tend to be
shorter in the block level designs, the reduced noise margin of
low-Vt devices, increased crosstalk capacitance to grounded
capacitance ratio due to thick and narrow metals, and some
strict requirements in specific signals (e.g., sense amplifier
data and reference nets of memory designs) make crosstalk
noise an important design parameter. On the other hand, in
chip level designs, long routes between blocks and structured

0-7803-9254-X/05/$20.00 2005 IEEE.

nature of buses running long distances in parallel increase

the susceptibility of the top level nets to crosstalk noise.
For analysis of crosstalk noise in synthesized blocks and
chip level designs that consist of such blocks, usually a gate
level crosstalk noise analysis tool is employed. Digital gates
are usually pre-characterized to reflect drive/holding strengths
for the output pins and noise rejection/propagation properties
for the input pins. Reduced order modeling techniques are
employed on the linearized networks of gates and coupled
interconnects for improved performance. For custom blocks
and memory designs, transistor level tools are utilized that
can perform characterization and analysis on the fly.
Due to the static nature of crosstalk noise analysis tools,
significant inherent pessimism exists in all current industry
tools. Logic correlations between aggressor and victim nets
[1], [2], [3], and temporal correlations in the form of pin timing
windows [4], [5], [6] have been utilized successfully to reduce
this pessimism to some level. This pessimism is reflected in
the functional noise analysis as wider and taller noise pulses
at the victim net receiver inputs. However, in functional noise
analysis, noise analysis tools propagate noise through the
receivers and the failure criteria is usually defined either as a
certain threshold at the receiver outputs of each stage or at the
memory element (latch/flip-flop) termination of a signal path.
This results in pessimism tolerance as the noise pulses may
be attenuated through propagation. Therefore, the introduced
pessimism in the analysis does not tend to accumulate through
a signal/clock path.
However in delay noise, this is not true. At each stage
of the signal and clock path, introduced pessimism in the
calculated delay accumulates though the path resulting in
overly pessimistic noise aware STA results. This causes several
unreal timing failures which require design resources and time
to address the violations and results in unnecessary delays to
tape out. It is therefore very important to reduce pessimism in
delay noise analysis.
In recent years, several techniques have been published
to efficiently take crosstalk noise into account during static
timing analysis. One issue to address has been the delay
noise calculation model. With the purpose of existing STA
tool compatibility, early works broke the mutual dependence
between timing windows of nets by grounding the coupling
capacitances after multiplication with a factor, resulting in
the so called discrete coupling factor model [8], [12]. The
multiplication factor is decided based on the switching di-

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rections and the overlapping of timing windows. Although

easy to incorporate into existing static timing methodologies
and efforts to prove the timing window convergence [8];
discrete coupling factor techniques suffer from discontinuity
between the boundaries when coupling factors change between
iterations. To address this issue, continuous coupling factor
techniques [13], [10], [21] have been proposed. All coupling
factor techniques simplify the problem of estimating crosstalk
noise impact on delay as they do not consider the victimaggressors system as a whole which results in siginificant
accuracy loss. More accurate models have been proposed using
superposition without using coupling factors to decouple the
coupling capacitances [4], [7]. Apart from the noise calculation
model, the other issue has been the timing window overlapping
model where one tries to find the worst case delay noise due to
multiple aggressors satisfying the timing window constraints.
Discrete overlapping models which allow either a complete
noise contribution or zero noise ([18]), as well as continuous
overlapping models where noise contributions are allowed
to be fractional based on the timing window overlapping
range ([20], [11]) have been proposed. Recently, non-iterative
techniques have also been proposed where in [9] an eventdriven time sorting algorithm is discussed and in [21] the
authors use a continious piecewise linear timing window effective length function. These methods either require significant
modifications to the existing static timing tools or resort to
specific simplified assumptions on noise models as mentioned
above.
In this paper, we develop a methodology compatible with
existing industrial static timing analyzers, without simplified
delay noise estimation assumptions, and with significant pessimism reduction with minimal runtime overhead. Specifically,
we introduce two techniques for pessimism reduction in
crosstalk noise aware static timing analysis. First technique,
effective delay noise, utilizes timing windows and uses the
traditional net by net delay noise analysis technique. The
novelty is in the way that the timing windows are used. Victim
and aggressor timing windows and their overlap properties are
used such that for each victim net, only the contribution of
delay that impacts the early and late arrival times at the path
endpoints is taken into account. This is in principle a less
pessimistic but still conservative way of incorporating delay
noise into the timing windows of nets, similar in nature to the
efforts in [9], [11], [20]. However, existance of multicycle and
false paths restricts the conservative usage of this pessimism
reduction method. The goal of reducing pessimism along with
the requirement of respecting all timing constraints such as
multicycle/false paths and still be conservative necessitates
the second method, path based delay noise analysis. This
is a path based technique in contrast to the traditional net
based method. In this approach, the analysis is done one
signal path at a time. This allows us to get rid of the
uncertainty of timing windows on the victim path and work
with deterministic switching times which reduces pessimism
significantly. Furthermore, this method is designed to be
iterationless in contrast to the net based techniques. This is

accomplished with a novel uncertainty propagation technique

which solves the optimization problem that arises in search of
an iterationless method, resulting in conservative and reduced
pessimism results. It is crucial to note that path based analysis
is not proposed to substitute the net by net approach, as this
would result in an unaccaptable runtime penalty considering
the huge number of paths. In our proposed methodology;
consevative pessimism reduction technique, effective delay
noise is first applied on a net by net basis after which path
based analysis is employed as the last step only on timing
failing paths. We also show that as results from net by net
analysis step are reused in path based analysis, the additional
runtime is negligable. Traditional, effective, and path based
techniques will be compared on a large block level industrial
DSP design in 90nm technology.
The paper is organized as follows. In Section 2, we go over
traditional crosstalk noise aware STA. The proposed effective
delay noise and path based delay noise approaches are
explained in Sections 3 and 4. In Section 5, a crosstalk noise
aware STA methodology using the proposed techniques is
proposed. Results on a 90nm industrial DSP are shown in
Section 6. Section 7 contains closing remarks.
II. T RADITIONAL CROSSTALK NOISE AWARE STA
In this section, we briefly go over the traditional noise
aware STA approach [7], [4]. Note that the explained approach
does not resort to simplified noise estimation methods such
as decoupling and considers the noise cluster made up of
victim and aggressor nets as a whole. As a result of noise
free static timing analysis, early and late arrival times (timing
windows) as well as minimum and maximum transition times
are obtained for each node in the circuit where a node can
be a sequential/combinational gate input/output or primary
input/output. At the timing check points (i.e., memory element
inputs and primary outputs) the early and late arrival times
of the propagated timing windows are compared against the
required times (which are decided by the timing constraints of
the design) and a decision is made whether there are setup/hold
problems at these end points. Gate input/outputs are referred
to as pins whereas the primary inputs/outputs are referred to
as ports. A net represents an interconnect in the circuit which
connects pins and ports. A timing path is a collection of pins,
ports, gates, and nets which starts at a primary input or a
memory element output pin and ends at a primary output or
at a memory element data input pin. Figure 1 shows a flipflop to flip-flop signal path along with its launch and capture
clock paths as an example. The reason behind the existence of
timing windows is the fact that each pin can be part of multiple
paths that are going through it, some faster than others, thus
resulting in possible early and late switching times for each
pin. These windows can be large depending on the topology
of the circuit.
The impact of crosstalk noise on STA is manifested as
increases in late arrival times and decreases in early arrival
times of timing windows and thus making it harder to satisfy

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D
CLK

agg. timing windows

D
CLK

victim timing window

s1

CLK
SOURCE

Fig. 1.

A typical signal path along with launch and capture clock paths

delta_d due to
3 overlapping
aggressors

d_nominal + delta_d

Fig. 2. Traditional noise-aware STA delay calculation and backannotation

timing constraints. Traditional static noise analysis approaches

the calculation of this impact on a net by net basis. Timing
windows obtained from STA (usually driver output timing
windows are obtained from STA and shifted by the RC delay
to obtain fan-out timing windows during analysis) are used
as a means to prune out possible aggressor nets. A worst
set of aggressor nets, whose timing windows are intersecting
with each other and with that of the victim net, for each
victim-aggressor transition combination (e.g., victim rising
aggressors falling for delay increase) is found. The delay
increase/decrease at each victim net sink due to this worst
aggressor set is then backannotated into STA simply by
representing this information as min delay and max delay
for each corresponding timing arc of the victim net. This
is illustrated in Figure 2. Suppose that the aggressor and
victim timing windows in the figure correspond to victim
L(ow) H(igh) transition and aggressor H L transitions
and that the victim and aggressor driver node windows have
been shifted to represent possible switching times relevant
to sink s1 of the victim net. As can be seen, there is a
region where all 3 aggressor timing windows overlap among
themselves and with that of the victim. This means that all
three aggressors can switch together and impact the signal
delay of the victim net. The worst case impact due to these
three aggressors is then found by finding the right alignment
between the switching times of these four nets such that the
delay impact on the victim net is maximized (some approaches
try to maximize delay change at the victim sink, whereas
others aim to maximize delay change at the victim sink output
after the signal propagates). This delay is then backannotated
to the corresponding timing arc in STA as shown in the figure.
Once this operation is done for each net in the design, an
STA update is performed to account for the impact of the
backannotated delay s. Note that for each interconnect timing
arc, four delay numbers are backannotated, two for delay
increase and two for delay decrease. The STA update results in
new timing windows and noise analysis is repeated using these
modified timing windows and iterations continue until the
timing windows converge [7], [8], [10] - [20]. When the final
STA update is done and timing checks are being performed,
the corresponding delay value is chosen depending on the
type of timing check being employed. For example for a setup
analysis, the delay s are utilized such that the launch clock
and signal path delay are increased whereas the capture clock
delay is decreased.

Notice that in the above explained methodology, the late

arrival time of all paths through pin s1 is increased by the
annotated max delay . This results in an enlargement of
the original timing window by the same amount as shown in
Figure 2. A similar argument applies for min delay and
the early arrival time of the original timing window.
In the rest of this paper, we will refer to net timing windows instead of pin timing windows for ease of
discussion. However, note that each net can have several
sinks and therefore several shifted sink timing windows (and
corresponding aggressor timing windows that are shifted to
represent the times they impact each sink) as discussed above.
We will also only talk about delay increase due to crosstalk
noise while similar arguments apply for delay decrease.
In the remainder of this paper, we propose two techniques
to reduce pessimism in the above explained noise-aware STA
methodology. Utilizing logical correlations, which has been
explored in [1], [3], is orthogonal to what is proposed here
and is not considered in this paper.
III. E FFECTIVE DELAY NOISE
As explained before, the final step of static timing analysis
is to obtain the early and late arrival times at the timing check
points, and compare them with the required times at these
points. Therefore, what one should worry about in noise aware
STA is the actual impact of crosstalk induced delay to the
early and late arrival times. The proposed effective delay noise
technique in this section is driven by this observation.
Let us re-consider the victim and aggressor timing windows
situation in Figure 3. It is true that the three aggressor nets and
the victim net can switch together in the first region resulting
in all three aggressors impacting the delay of the victim net
in a worst case manner. However, observe that the latest time
point around which these nets should switch to be able to
realize this impact on the victim net is t1 . In other words, the
path in which the victim net is switching around time t1 is the
latest path through this net that can be impacted by all three
aggressors. If the delay due to these three aggressors is dd1 ,
then the switching time of the victim net will be delayed to
t1 + dd1 . Furthermore, only if t1 + dd1 > t3 , will this have an
impact on the late arrival point of the victim net timing window
by the amount t1 + dd1 t3 . Similarly, other possibilities
are when aggressors 1 and 2 switch together with the victim
around time t2 and when aggressor 2 switches together with

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the victim around time t3. The effective delta delay, which
is the maximum impact of all possible scenarios to the late
arrival time of the timing window is given in Equation 1.
ef f ective delay = max (ti + ddi tend )
i

(1)

ef f ective delay = max (ti + ddi tc )

(2)

For example tc = te2 in Figure 4.

a

agg. timing windows

where ti is the latest possible impact time for scenario i, ddi

is the crosstalk noise induced delay in scenario i and tend is
the late arrival time of the victim net window.

point in the timing window which should mark the max arrival
time of the non-false/multicycle paths should be found and
declared as the tc (critical time point) which transforms Eqn
(1) to Eqn (2).

victim timing window

b
dd1
dd2
dd3
t1

t2

t3

a
b

effective
delta_d

Fig. 3.

Effective delay calculation

d
e

When compared to traditional delay noise (Figure 2), this

technique results in the backannotation of dd3 instead of dd1 .
It is clear that the effective delay is never larger than the
delay backannotated in the traditional approach.
A. Limitations
Effective delay noise method is easy to compute and readily
implementable to improve the traditional noise aware STA
methodology. However, there exists a hurdle to this technique
when timing exceptions (i.e., false and/or multicycle paths)
exist in the design. The core argument in effective delay noise
technique is that we only need to worry about the delay noise
impact on the min and max arrival time points on a net. This
argument makes the assumption that the timing paths that
correspond to these min and max arrival times propagate to the
end points where final timing checks will be made. Suppose
that there are two paths (. . . a c e and . . . b d e)
coming into the same endpoint as shown in Figure 4. The
timing windows at a, b, c, d, e are also shown in the figure.
As can be seen, the . . . a c e path is earlier than the
. . . b d e path, therefore making . . . b d e the
critical one of the two in case of a setup analysis. If we look
at the contribution of the two paths to the timing window at
e, we can see that the . . . b d e path is contributing to
the later portion of this window (bold region). Now, suppose
that the paths through b to e are false and/or multicycle paths
(i.e., they are not important to be checked against the required
time at e). This brings the latest arrival time at e to te2 which
is the latest arrival considering all true paths to this end point.
If we employ effective delay noise method on net e and use
tend = te3 (Eqn. (1)), this results in an under-estimation of
the important delay . As can be seen in Figure 4, we should
be using tend = te2 as this is the max arrival time that matters
at the end point.
Therefore, if a net is part of false/multicycle paths, for
effective delay noise method to be conservative, an internal

time
te1

Fig. 4.

te2

te3

False/multicycle path

It is not trivial to obtain the critical time point in a

timing window as current STA tools do not maintain this
information. False paths are filtered out right before reporting
phase after STA computation is finished, resulting in arrival
times (thus timing windows) that include false path timing. In
our crosstalk noise aware STA methodology, this limitation is
addressed by using traditional delay noise method on the nets
that are on false/multicycle paths and then applying path based
delay noise on failing paths as explained in the next section.
IV. PATH BASED DELAY NOISE
One step further in pessimism reduction in noise aware STA
would be to try to get rid of the static nature of the above
techniques and aim toward a more dynamic analysis which
also would not require any iterations. The first step towards
this goal is to perform the analysis on a path by path basis
instead of the net by net approaches as mentioned above. If we
look at a timing path for setup analysis, it contains the launch
clock path and the signal path. The arrival times on the nets of
a particular path need not be represented as windows as they
are deterministic. Timing uncertainty due to process variations
is not considered here as it is an orthogonal problem. With
the purpose of keeping the complexity of the problem to a
manageable level, even if the aggressor net timing windows
remain as normal timing windows obtained from STA; a
significant pessimism reduction in delay noise calculation can
be expected as the timing windows of the victim path nets are
reduced to deterministic single time points.
Apart from pessimism reduction, another appealing property
of path based delay noise analysis is that it allows noise-aware
timing of a given path in a single pass, i.e. without iterations.

957

at v1 with and without additional uncertainty at this stage,

respectively. Corresponding aggressor timing windows that
can impact the arrival time at this stage are also shown in the
figure. As a1 aligns with all 3 aggressors, the uncertainty is
the delay that can be induced by all 3 aggressors, represented
in the figure by a bold vertical bar. The highest and the
lowest y-coordinates of this uncertainty profile is defined as the
uncertainty at this stage, shown as u1 on the y-axis. The nonoise arrival time at v2 is a2 as shown in Figure 5-(II-b). The
upstream uncertainty u1 is added to a2 to represent the total
uncertainty up to this point as shown in the x-axis of Figure
5-(II-b). The uncertainty profile of v2 from a2 a2 + u1
is shown in the figure. From a2 t1 , the uncertainty is
the delay from 2 aggressors and from t1 a2 + u1 , it is
the delay from 1 aggressor. The uncertainty at this stage
is again determined by the max and min y-coordinates of
the uncertainty profile and represented as u2 in the y-axis.
This propagation continues until the path end point is reached.
Using this method, the uncertainty window on the victim path
nets can only enlarge as the uncertainty is propagated down the
path, taking into account all aggressor switching possibilities.
The max point of the final uncertainty window obtained at the
path end point gives the worst case arrival time for the path in
one pass. The actual implementation of this technique requires
nearly no overhead as the uncertainty profile information on
each net is already generated as part of the traditional delay
noise analysis when a scan-line algorithm is used to obtain the
worst case aggressor set.
v1

v2
t3

scn_1
scn_2

a1

a2
(I)

arrival time w/ uncertainty

at this stage

The challenge and solution of realizing this iteration free

computation is illustrated in Figure 5-(I). Non-noisy switching
point of net v1 aligns with all three aggressors at time a1 .
Suppose the noise induced delay pushes this time by dd3. As
v2 is being analyzed, if we consider the delay change in v1
the non-noisy switching point of v2 (a2 ) is first moved by
dd3 to t3 (scn1 ). Now, v2 aligns with none of its aggressors.
However this greedy approach of iterationless analysis is
not guaranteed conservative. Consider the case where for v1 ,
only two of the possible three aggressors switch and that this
moves the switching point of v1 by less than dd3. Now, a2
will be shifted less and thus may align with all its aggressors,
resulting in a greater noise aware delay (scn2 ). Therefore, the
goal is to be able to get rid of iterations while making sure
that the path delay noise is maximized.
The uncertainty of victim switching time is due to two
reasons: Uncertainty due to different alignment of the aggressors injecting noise into this net and the uncertainty of the
victim arrival time without noise injected into this net. The
latter uncertainty is caused by the uncertainty of the noise
injection into the previous nets of the analyzed path. This
dependence of the victim switching time on two sources of
uncertainty is a major problem that complicates the analysis.
The goal of the proposed technique is to overcome this difficulty. Unlike [9] our technique does not make any restrictive
assumptions about the noise computation model except that
noise is additive, which is a common assumption in noise
analysis. Moreover the proposed technique can be generalized
for more complex noise models. The only requirement is the
necessity to compute maximum possible delay variation due
to a given set of simultaneously switching aggressors. If we
assume that the victim switching time without noise is fixed
and the switching time of each aggressor net is uncertain inside
its timing window then we can compute the timing interval
of the victim switching at the presence of the injected noise.
This timing interval is a function of non-noisy victim arrival
time. We call this function an uncertainty profile of the net.
The lower bound of the uncertainty profile is always the nonnoisy arrival time of the victim net and the upper bound is
more than the lower bound by the amount of noise due to all
the aggressor nets aligning with non-noisy victim arrival time.
Our technique analyzes the nets of the path in their topological
order from the source to the sink. For each net, we compute its
uncertainty profile and its uncertainty interval at the presence
of the injected noise using the uncertainty interval of its
arrival time without noise. Then we propagate the computed
interval to the next net as its no noise uncertainty interval
by adding the corresponding gate delay. This technique can
be easily modified to take into account delay uncertainty
due to process variation and environmental parameters. The
uncertainty propagation technique as illustrated in Figure 5(II).
Figure 5-(II-a) shows the uncertainty profile of net v1
assuming that it is the first net of the path (primary input
or first net after clock source) and has a deterministic single
switching point a1 . x and y axis represent the arrival time

t1 t2

x=y

x=y

u2

u1

a1

arrival time w/o uncertainty

at this stage
(a)

a2

a2+u1

(b)

(II)

Fig. 5.

Path based delay calculation

V. C ROSSTALK NOISE AWARE STA METHODOLOGY

In practice, we implemented the methods explained thus
far in a crosstalk noise aware STA analysis/repair system that
consists of a crosstalk noise calculation engine, and an STA
engine as shown in Figure 6. An extension to traditional delay
noise calculation, the effective delay noise calculation module has been implemented in the crosstalk noise calculation
engine. The noise calculation engine obtains timing windows
and slew rates from the STA engine and backannotates pin-topin delay s calculated using the effective delay noise method.

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To efficiently handle the limitation discussed in Section 3.1,

we simply use the more conservative traditional delay noise
calculation when a net is on a false/multicycle path. After the
iterations converge (usually 2 iterations are sufficient), failing
paths due to crosstalk induced delay are obtained in the STA
engine. A separate module that extracts these paths and applies
path based delay noise analysis only on these paths has been
implemented on top of the STA engine. Note that as we use
the aggressor windows as is in path based delay noise analysis,
aggressor windows used are based on the converged effective
delay noise analysis and therefore have already been enlarged
in a worst case manner. As a result, the iterationless path based
method is indeed conservative.

source to path end point) using three methods. TDN, EDN,

and PBDN mean traditional delay noise analysis, effective
delay noise analysis and path based delay noise analysis,
respectively. As can be seen, average path delay reduces from
0.437ns.(TDN) to 0.271ns.(EDN) to 0.121ns.(PBDN).
2000
1500

mean: 0.437ns

1000
500
0

0.2

0.4

0.6

3000

0.8
1
total path delay (TDN) [ns]

1.2

1.4

1.6

1.8

mean: 0.271ns

2000
1000

Critical paths extraction &

path based delay noise
module

0.2

0.4

0.6

2000

0.8
1
1.2
total path delay (EDN) [ns]

1.4

1.6

1.8

mean: 0.121ns

1500
1000
500
0

delta_delays

timing windows &

transition times

STA Engine

0.2

0.4

0.6

0.8
total path

delay

Fig. 7.

1
1.2
(PBDN) [ns]

1.4

1.6

1.8

Histogram of delay s using 3 techniques

Crosstalk induced delay

noise calculation engine

Figures 8 and 9 show a comparison of total path delay s

between the three methods. In these figures, x and y axis are
path delay s using different techniques. Each dot corresponds
to a path. Effects of pessimism reduction on the path delay s
are clear from these figures.

Effective delta delay

module

Fig. 6.

Reduced pessimism crosstalk noise aware STA

1.6

1.4

(EDN) [ns]

1.2

delay

total path

VI. R ESULTS
In this section, we present detailed results of the proposed
techniques on a 90nm DSP block. The block is synthesized
of 90nm standard cell library cells, and contains 56k nets. As
the STA engine, commercial tool Primetime is used whereas
an internal tool [4] has been utilized as the crosstalk induced
delay calculator. Timing libraries have been characterized at
typical corner (Vdd = 1.1V, Temp = 105C) and interconnect
extraction has also been done at the typical corner with commercial extraction tool Star-XT. The design has been timing
and functional crosstalk noise optimized. In other words, no
timing violations without crosstalk induced delay noise, and no
functional crosstalk noise violations (i.e., glitch noise) exist.
We ran traditional delay noise analysis, effective delay noise
analysis and path based delay noise analysis on this block. As
it is not feasible, nor necessary to run path based delay noise
analysis on all paths of the design; the paths on which this
technique will be applied are chosen based on the traditional
delay noise analysis. We chose close to 28k paths (from setup
analysis with timing slack less than 0.2ns, maximum 1000
paths per end point and maximum 10000 paths per clock
group) and compared the results of the three noise aware STA
techniques on these paths.
Figure 7 shows the histograms of total path delay s (i.e.,
delay accumulated on the nets of a path starting from clock

0.8

0.6

0.4

0.2

0.2

0.4

Fig. 8.

0.6

0.8
1
total path delay (TDN) [ns]

1.2

1.4

1.6

delay s TDN vs. EDN

Finally in Figures 10 and 11, a comparison of the timing

slacks from setup analysis using the three techniques, is
shown. The x and y axes are path timing slacks using different
methods. The diagonal line is the x = y line and there is a
vertical and a horizontal bold line at slack = 0 to represent
the timing failure criterion. Remember that all these paths
had positive slack before incorporation of any additional delay
due to crosstalk noise. Worst slack (i.e., slack of most failing
path) using TDN, EDN, PBDN are 0.819ns, 0.615ns,

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1.6

0.8

1.4

0.6

0.4

path slack (PBDN) [ns]

total path delay (PBDN) [ns]

1.2

0.8

0.6

0.2

0.2

0.4
0.4

0.6
0.2

0.8
0

0.2

0.4

0.6

0.8
total path

delay

Fig. 9.

1
(TDN) [ns]

1.2

1.4

1.6

0.8

delay s TDN vs. PBDN

Fig. 11.

and 0.185ns respectively. Out of 28826 paths, 12843 are

failing timing according to the traditional delay noise analysis
results. Using effective delay noise method, although slack
is improved for most paths, only 781 go to positive slack
territory. Out of the remaining 12062 paths, using path based
delay noise technique moves another 6572 paths to positive
slack territory, reducing the number of timing failing paths to
5490. This is a 57% improvement in the number of failing
paths in addition to the reduction of worst case negative slack
by 77% from 0.819ns to 0.185ns, resulting in a much more
manageable timing picture for the designer to deal with.
0.8

0.6

0.4

path slack (EDN) [ns]

0.6

0.4

0.2
0
0.2
path slack (TDN) [ns]

0.4

0.6

0.8

Comparing path slacks from TDN and PBDN

VII. C ONCLUSION
In this paper, we presented two temporal methods to reduce
pessimism in crosstalk noise aware STA. While effective delay
noise method is a net based technique that focuses on the
delay that matters at the timing end points, path based
delay noise method utilizes the reduced uncertainty in timing
windows when a particular path is considered. Limitations
to the effective delay noise approach in the existence of
false/multicycle paths have been discussed. We also presented
a novel uncertainty propagation technique which enables the
path based delay noise method to be an iterationless way of
finding a minimally pessimistic yet conservative maximum
path delay uncertainty due to crosstalk noise. Both techniques
are very easily adaptable to industrial crosstalk noise aware
STA tools and methodologies with minimal overhead to the
traditional methods.

0.2

R EFERENCES

0.2

0.4

0.6

0.8
0.8

0.6

Fig. 10.

0.4

0.2
0
0.2
path slack (TDN) [ns]

0.4

0.6

Comparing path slacks from TDN and EDN

These results are summarized in Table I.

avg. path delay
worst slack
# of failing paths

TDN
0.437ns
0.819ns
12843

EDN
0.271ns
0.615ns
12062

PBDN
0.121ns
0.185ns
5490

TABLE I
CROSSTALK NOISE AWARE

STA

RESULTS

0.8

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