Introduction to ADC

testing I
Definition of basic parameters
Jn aliga
Dept. of Electronics and Telecommunications
Technical University of Kosice, Slovakia

Agenda

Introduction
Deterministic and probabilistic
models
Basic static parameters
Basic dynamic parameters
Other parameters

A/D converter A/D

interface
A/D interface
Reference and
power sources

Signal
conditioning

S&H
(optional)

ADC

Buffe
r

Timing and control circuit

x
k round
Q

ADC parameters
(characteristics & errors)

Static (quasistatic) parameters derived

from transfer characteristic

Dynamic parameters characterize a

behavior of ADC at time-varying signals

Point (gain, gain error, offset, missing code, ...)

Function (transfer characteristic, INL, DNL, ...)
SINAD, ENOB, SNR, SFDR, THD, IMD, ...

ADC parameter testing requires

extraordinaire accuracy

E.g.: 12-bit ADC: detetermination of transition

level with uncertainty < 1% uncertainty of
measurement < 1/(100*4096) ~
0,00025%=2,5ppm of ADC FS

Accuracy versus precision

ADC transfer characteristic

T[k] - transition level
(threshold
of code k),
W[k]= T[k]T[k-1] code
N
T 2 1 Tnom 1
bin
Qnomwidth
nom
N
2 2

N nominal resolution
-4
-3
-2
(number of bits) of ADC
Real
ADC

Input
code k
111

Gain (slope)
error

Nonlinearity

Ideal and
real straight
lines

110
101
100
-1
0
1
011

Ideal
ADC

Input
analogue
value x(t)
[Vfs/Q]

Missing
code
2

Error in monotonicity
010

Offset
error

001
000

Vfs - full scale range

Vfs = Vref(2N-1)/(2N)

2N
Vfsn N
Tnom 2N 1 Tnom 1 2N Q
2 2

Gain and offset + their

errors

Fitting the straight line:

End points straight line - connecting the

two end code transition or code midstep
values
Least-square fit straight line according a
least-square fitting algorithm
Minimum-maximum straight line - the
line which leads to the most positive
and the most negative deviations from
the ideal straight line

ADC transfer
characteristic
Deterministic model
Output
code k
111

Stochastic model

Output
code k
101

Input
analogue
value x(t)

110

100

101

[Vfs/2N]

100
-4

-3

-2

-1

00111
010
001
000

1
2
Deterministic
definition
Channel profile

Input
analogue
value x(t)
[Vfs/2N]

P(k|x)
1

k =0,1,...,2N-1
0

Conditional
probability

1,5

Stochastic
definition
Input
analogue
value x(t)
[Vfs/2N]

T kTEST : P k kTEST T kTEST P k kTEST T kTEST 0,5

DNL and INL

Differential non-linearity
DNL [ k ] =

Integral non-linearity

W [k ] - Q
Q

no
m

no
m

T [k ] - Tnom[k ]
INL [k ]=
Qnom

INL k

DNL i
INL k 1 DNL k
i 0

Dynamic parameters I

Bandwidth (BW) - the band of frequencies of

input signal that the ADC under test is intended to
digitize with nominal constant gain. It is also
designated as the Half-power Bandwidth, i.e., the
frequency range over which the ADC maintains a
dynamic gain level of at least 3
dB with respect to
the maximum level.
Gain flatness error (G(f)) - the difference
between the gain of the ADC at a given frequency
in the ADC bandwidth, and its gain at a specified
reference frequency, expressed as a percentage of
the gain at the reference frequency. The reference
frequency is typically the frequency where the
bandwidth of ADC presents the maximum gain. For
DC-coupled ADCs the reference frequency is
usually f = 0.

Quantisation noise and

errors

Caused by rounding in quantisation process

(and ADC non-linearity)
Power of quantisation noise for ideal ADC
(2eq, 2rms)

Is it dependent/independent on input signal?

Is the value Q 2/12 correct?
1 1
2
2 1
Distribution?
q Q
2 2 J0 2N k
12 k 1 k

Answer: see the simulation

ADC noise and distortion

ADC output random noise random signal:

Quantisation noise - uniform

Noise generated in input analogue circuits - Gaussian
Noise caused by sampling frequency jitter and aperture
uncertainty (Kobayashi)

Spurious unwanted deterministic spectral

components uncorrelated with input signal (e.g.
50Hz)
Total noise any deviation between the output
signal (converted to input units) and the input
signal, except deviations caused by linear time
invariant system response (gain and phase shift),
harmonics of the fundamental up to the frequency
fm, or a DC level shift.
Distortion new unwanted deterministic spectral

Noise floor

determines the lowest input signal power

level which is reliably detectable at the ADC
output, i. e., it limits the ultimate ADC
sensitivity to the weak input signals, since
any signal whose amplitude is below the
noise floor (SNR < 0 dB) will become difficult
2
to recover.
M / 2 1
NFl

k 1, k J , k hJ

Y k

1 M
Y
2 2

M
hmax
2

h 2 hmax

Dynamic parameters II
Signal to noise and distortion ratio

SINAD: for a pure sinewave input of specified

amplitude and frequency, the ratio of the rms
amplitude of the ADC output fundamental tone to
the rms amplitude of the output noise, where
noise is defined as to include not only random
errors but also non-linear distortion and the
effects of sampling time errors, i.e., the sum of all
non-fundamental spectral components in the
range from DC (excluded) up to
sampling
2 half the
2
Y J NFl
frequency (fs/2).

SINADdB 10 log

M / 2 1

k 1, k J

Y K

1 M
2 NFl Y
2 2
2

Dynamic parameters III

SNR

Signal to noise ratio (SNR) - harmonic

signal power (rms) to broadband noise
power ratio excluding DC, fundamental,
and harmonics
Y J NFl
2

SNRdB 10 log

M / 2 1

k 1, k J , k hJ

Y k hmax 1 NFl
2

1 M
Y
2 2

Dynamic parameters IV
THD, THD+noise, IMD

THD

THDdB 20 log

H
i

2
i ADC

THD

H
i

2
i ADC

THD+noise = 1/SINAD

Intermodulation distortion (IMD) - for an input

signal composed of two or more pure sinewaves,
the distortion due to output components at
frequencies resulting from the sum and
difference of all possible integer multiples
of the
A
IMD
input frequency tones.
IMtone

Dynamic parameters V
Effective Number of Bits

Effective Number of Bits (Nef, ENOB) - for a sinusoidal input

signal, Nef is defined as:

Nef N log2

rms

12
N log2 rms

q
Qnom

SINADdBFS 1.76dB
6.02

where rms is the rms total noise including harmonic

distortion and eq the ideal rms quantisation noise for a
sinusoidal input. (SINADdBFS = SINADdB - 20log(SFSR))
SFSR signal to full scale ratio
Nef can be interpreted as follows: if the actual noise is
attributed only to the quantisation process, the ADC under
test can be considered as equivalent to an ideal Nef-bit
ADC insofar as they produce the same rms noise level.

Dynamic parameters VI
SFDR

Spurious-free dynamic range (SFDR) - expresses the

range, in dB, of input signals lying between the averaged
amplitude of the ADC's output fundamental tone, fi, to
the averaged amplitude of the highest frequency
harmonic or spurious spectral component observed over
the full Nyquist band, for a pure sinewave input of
specified amplitude and frequency, i.e., max{|Y(fh)|, |
Y(fsp)|}:

SFDR(dB) 20 log

Yavm (fi )

max{| Yavm (fh ) || Yavm (fsp ) |

where: Yavm is the averaged spectrum of the ADC output,

fi is the input signal frequency, fh and fsp are the
frequencies of the set of harmonic and spurious spectral
components.

Dynamic parameters VII

Experimental demonstration

Measurement setup (run generator

first and then demonstration)
Sound out
AI1 (DUT)

USB

NI USB 6009
ADC: 12 bits, 10kHz,
differential

Software (LabVIEW):
1. Sinewave generator = Sound
card
2. Control: AI1 = DUT (FS,
record)
Data processing and

Other parameters

Various electrical parameters, e.g.

input impedance, power
requirements, grounding,
Time parameters, e.g. clock
frequency, conversion time,
sampling frequency,
Digital output: data coding, levels
(logic), serial/parallel, error bit rate,

Introduction to ADC
testing II
Basic standardized test methods

Agenda

Standardization
Static test method
Histogram test
Dynamic test with data processing
in time domain
Dynamic test with data processing
in spectral domain

Standardization

IEEE Std. 1057 - 1994, "IEEE Standard for Digitizing Waveform

Recorders",
IEEE Std. 1241 - 2000, "IEEE Standard for Terminology and Test
Methods for Analog-to-Digital Converters
European project DYNAD SMT4-CT98-2214, Methods and draft
standards for the DYNamic characterisation of Analogue to Digital
converters
http://www.fe.up.pt/~hsm/dynad
IEC Standard 62008 Performance characteristics and calibration
methods for digital data acquisition systems and relevant software
Additional and related standards:

IEEE Standard on Transition and Pulse Waveforms, Std-181-2003 (IEC

60469-1, -2)
IEEE and IEC standards for DAQ and ADM in preparation
IEC 60748 - covers only static ADC and DAC operations

Detail overview of standards and standardisation see the lecture of

Pasquale Arpaia: A/D and D/A Standards, CD from SS on DAQ 2005
Standard comparison: Sergio Rapuano: Figures of Merit for Analog-toDigital Converters: Analytic Comparison of International Standards, In

ADC static test

Standardized method

ADC static test - basic

ideas

Yields ADC transfer characteristic

Static point and function parameters
can be derived and calculated:

Gain, offset, FS, DNL, INL,

Based on the stochastic model of ADC

Simple test setup DC voltmeter is the
only accurate instrument
Time consuming each T[k] is
determined individually. The total time:
2N x longer than determination of one T
[k]

Static test setup (IEEE

1057)
Control and sampling
clock, ADC power, ...

Programable
DC source

ADC
under
test

Buffer

DC
Voltmeter
Control of test stand
(PC)

Recording device,
e.g. logic analyzer

ADC static test - algorithm

Start with the code k = 1

Find an input voltage level for which the probability
of codes lower than k in the record is slightly
higher than 0.5 the voltage is below T[k].
Find a bit higher voltage (the usual step is a quarter
of Q) for which the probability of codes lower than k
is slightly lower than 0.5 the voltage is above T[k]
Fit these two point by line and calculate the voltage
for which the probability of codes smaller than k is
0.5 this is the transition level of code k the
voltage equal to T[k]
Repeat the procedure for all k = 1, 2, ., 2N-1 the
complete transfer characteristic will be measured

Uncertainty in the static

test
The uncertainty can be reduced by
increasing the number of acquired samples
(M).
The table shows the measurement precision
for a confidence
level of 99,87%. 102 409
Number
of acquired samples

64 256
(M)
4
6
Transition level measurement
precision
45% 23% 12% 6%
(% of noise standard
deviation)

The main disadvantage

of the static testing

The test is long time consuming:

Lets test 16bit ADC with sampling

frequency 10kHz, testing step is Q/4,
additive noise: =1LSB, required precision:
better than 10%.
The chosen record length: 2000 samples
Measurement on one level takes
2000 x 0.1ms = 0.2s
Total required time: 0.2s x 2(16+4)= 58.2
hours!!!

Static test
Experimental demonstration

Measurement setup (
run demonstration)
AI0 (DUT)

USB

AI1 (Voltmeter)
NI USB 6009
ADC: 12 bits, 10kHz,
differential
DAC: 12 bit, static, RSE

1:10

AO0 (DC
source)

Software (LabVIEW) controls:

1. AO0 = DC test voltage
2. AIO = DUT - FS, record
3. AI1 virtual DC voltmeter with
averaging
4. Statistical data processing
and visualisation

Alternative static method

with feedback - IEEE 1241

Alternative static method

with feedback - IEEE 1241

I
NI USB 6008 (12 bits, 10kHz,
10000s/T)

Some experimental results

II
NI USB 6008/9 (10000s/T)
Difference of
two
following
measuremen
ts

Switching
monitor
during the
measuremen
t

Histogram (statistical)
test
Standardized method

Histogram (statistical) test

Basic ideas I

Goal: to determine ADC transfer

characteristic (the same as in static test
method)
The calibrating signal is a time invariant
repetitive signal covering the ADC full scale

The stream of ADC output codes is recorded

Histogram is built from the record
The relative count of hits in code bin k in the
histogram in comparison to the calibrating
signal probability density function (or counts for
code bin k in cumulative histogram in relation to
signal probability distribution function) gives
information about the code bin width (or code
transition levels)

Histogram (statistical) test

Basic ideas II

The best shape would be ramp or triangular

signal. Why? Problem?
The basic recommended signal by all
standards: sinewave. Why?
To achieve a required accuracy a relative
long record (or records) is required
Faster than the static test
Requirement: an accurate generator with
an extremely high accuracy (low distortion,
high linearity, high spectral purity)

Histogram (statistical) test

General test setup
Obliged
Recommended
Optional

Synchronisation

Accurate generator
(arbitrary, DDS)

Notch
filter

CLK
generator

ADC under
test

Control and data

processing (PC)

Buffer

Recording
device

Ramp signal (IEEE 1241)

T[k]=C+G.HC[k-1]/S for k=1, 2, .... , (2N2)
G is a gain factor, C is an offset factor,
The code bins 0 and 2N-1 are usually
excludedj from data
processing (why?)
N
2 2
HC j H i
i 1

DNL k

H i

i 1

T 1

T k T k 1
H k

Q
S 2N 2

T 2 2 T 1
G
S

uncertainty : given by ramp nonlineari ty and noise

Sinewave signal
(All standards) theoretical background I

Signal: x t A cos 2ft

d 1
x
Density
p x 2.
arccos

dx 2
A
of probability:
Distribution of probability:

Vfs k 2N 1

Pk

2N

A2 x 2

Vfs k 1 2N 1
2N

A x
2
1

dx

1
Vfs k 2N 1
Vfs k 1 2N 1
arcsin
arcsin
N

A.2
A.2N

Sinewave signal
(All standards) theoretical
background I

Ideal theoretical histogram:

M
Hid k

Vfs k 2N 1
Vfs k 1 2N 1
arcsin
arcsin
N
N
A
2
A
2

H
k

H
k
id
DNL: DNL k
Hid k

Transition levels:

Hc k 1
T k C A cos

Hc 2 1

for

k 1, 2, , 2N 1

Sinewave signal
(All standards) theoretical
background II

Problem in praxis: what are the

sinewave parameters A, C Hid[k]?
Various ways of estimation, e.g
Dynad:
~
~
H 0
H 2
T 2 1 cos
T 1 cos
H 2 1
H 2
Incorrect C~
H 0
H 2 2
cos

cos

estimation
H 2 1
H 2 1
error in ~
~
~
T 2 1 T 1
gain and A
H 0
H 2 2
cos
cos
offset
H 2 1
H 2 1
N

C
N

C
N

C
N

N
N

2
1

Sinewave signal
Test conditions I

The total record must contain exactly an

integer number J of sinewave cycles
R partial records can be used instead of one
long record
Total recorded number M of samples must
be relatively prime with J, i.e. they have no
common factor
J
Then the sampling and fi M fs
sinewave frequency are:r
1

,
r
2 JM

r fi f s

Sinewave signal
Test conditions II

The number of samples (M) to acquire in

the histogram test, depends on:

The noise level in the measurement system,

The required tolerance (B is measured in LSBs)
and confidence level () and the M is different if
DNL (quantization interval) or INL (transition
levels) it to be determined.
P TMEAS BQ Treal TMEAS BQ 1
The specification of tolerance for an individual
transition level or code bin width, or for the
worst case in all range.

Sinewave signal
Test conditions III

The equation generally used to determine the number of

records to acquire is:

2N 1 K
R J
B

c 1,1

0
,
2
c

N
T 2 1 T 1

VS
c 1 2

N
T 2 1 T 1 M

K 2 erf

J=1 for INL, J=2 for DNL, is the standard deviation of noise
level in volt for the INL determination and the smaller of
the values of and Q/1,1 for the DNL determination.

Sinewave signal
Simulation

Simulation = (see the simulation):

Form of histogram for various test

signals
Error caused by limited number of
samples
Error caused non-coherent sampling
Error caused by noise in input signal
Error caused by higher harmonics

Histogram test
Experimental demonstration

Measurement setup (run generator

first and then demonstration)
Sound out

1:2

AI1 (DUT)

USB

NI USB 6009
ADC: 12 bits, 10kHz,
differential

Software (LabVIEW):
Sinewave generator = Sound
card
AI1 control = DUT - FS, record
Data processing and

tests
Comparison generators (USB
6009)
Stanford DS
360 (20-bits,
100 mil.
samples)

Agilent 33220A
(14-bits,
100 mil.
samples)

Histogram (statistical)
test
Some non-standardized methods

Non standardized histogram

tests Basic ideas

Reasons:

To use signals that are closer to real signal

digitized by ADC in common applications
To use signal that can be simply generated with
required precision

Common signals:

Gaussian noise
Exponential signal
Uniform noise, small sinewave or triangular
with DC steps,

Non standardized histogram

test Gaussian noise I
Martins, R. C., Serra, A. C.: ADC Characterisation by
using Histogram Test stimulated by Gaussian Noise.
Theory and experimental results, Measurement,
Elsevier Science B. V., vol. 27, n. 4, pp. 291-300,
June 2000
The noise is centred within ADC input range and
overlap the whole ADC range
Problem generate the noise with really precise
Gaussian distribution convenient methods for low
resolution ADCs and very high and very low
frequencies where it is difficult to generate sinewave
with required purity

Non standardized histogram

test Gaussian noise II
Holub J., Komrek M., Machek J., Vedral J.: STEP-GAUSS
STOCHASTIC TESTING METHOD APPLICATION FOR
TRANSPORTABLE REFERENCE ADC DEVICE, Proc. 8th IWADC
2003, Perugia, Italy, pp. 223-226
Gaussian noise with a small standard deviation is moved
within the ADC input range by adding a DC voltage (mean)
in small steps so that the results will be the same as using
uniform noise overlapping the whole ADC full scale

lim

pdfG k,

1
0

Discussion: is really possible in praxis to fulfil the

requirement of the limit with finite DC steps with
acceptable precision?

test
Small amplitude sinewave or
triangular with a DC component
Michaeli L., Serra A.C., ..: In: IEEE transactions on
instrumentation and measurement, Measurement,
proc. of IMTC, IMEKO IWADC
Idea: multistep test with fractional histograms (and
INLs) acquired at small signal (sinewave, triangular)
covering only a few tens/hundreds of codes shifted
within ADC FS by known DC voltage
Advantage: the quality of test signal may be much
worse than those of signal covering the whole FS of
ADC
Disadvantage: connecting the partial histograms to
build the final histogram

Non standardized histogram

test Exponential signal
Holcer R., Michaeli L., aliga J.: DNL ADC testing
by the exponential shaped voltage, In: IEEE
transactions on instrumentation and
measurement, Vol. 52, no. 3 (2003), pp. 946949.
aliga J., Holcer R., Michaeli L.: Noise sensitivity of
the exponential histogram ADC test, In:
Measurement, Vol. 39, no. 3 (2006), pp. 238244

We will continue with a new PhD. Student

next year
Exponential signal is simple to generate
native signal in electronic circuit
Problem: distortion by other exponential
with different time constant and keeping
the final value of the signal known and
constant.

x t FS B exp B

Non standardized histogram

test
Small signals with a DC component

Measurement setup (run generator

first and then demonstration)
Sound out

1:2
1:10

AI0 (DUT)

USB

AO0 (DC shift)

Software
(LabVIEW):
Arbitrary generator = Sound card
DC shift = AO0

NI USB 6009
ADC: 12 bits, 10kHz,
differential

AI0 = DUT (FS, record)

Data processing and
visualisation

Histogram test
Conclusions

Histogram versus static test:

histogram test gives usually better
more reliable results because:

Faster = the test conditions are

constant and measurement of any T [k]
is distributed and repeated in time over
the all testing time
Disadvantage: an precise generator is
needed

Non standardised test procedures can

bring simplifying in test setup and

ADC dynamic testing

Dynamic test
Introduction

Goal:

Determination of various dynamic ADC

parameters such as SINAD, ENOB, SNR,
THD, IMD SFDR,

Two ways of data processing:

Time domain directly SINAD, ENOB

Spectral domain (DFT test): SINAD, ENOB,
SNR, THD, IMD SFDR,
No way can be generally supposed to be
the best one

Dynamic test
General test setup

Synchronisation

Accurate harmonic
generator (DDS)

Notch
filter

Accurate harmonic
generator (DDS)

CLK
generator

ADC under
test

Control and data

processing (PC)

Buffer

Obliged
Recommended
Optional
Only for IMD and multitone methods

Recording
device

Dynamic test
Requirements

Coherent sampling the same as for

sinewave histogram test - the precise
coherence is not necessary
Minimal size of record:
N

2
Mmin
Mmin 2N
1 DNLmax
Record can consist of a few partial records
Sinewave must cover the ADC input range
as much as possible (more than 90 95%)
but must not overload it.

Dynamic test
Data processing in time domain

Dynamic test
Data processing in time domain I

See the following lectures by prof. Kollr

and prof. Hndel
Basic idea: to calculated the noise in the
record (residuals) as the deference between
the input signal sinewave (analogue
samples) and the record (digitized
samples). y ~
x
Knowing the noise the SINAD and ENOB can
be calculated according the definitions

Dynamic test
Data processing in time domain
II

Difficult task and question: the input signal

must be precisely know how to do it?
Common solution: recovering the input
signal from the record by a fitting method
(LMS)

Three-parameter fit (A, C, )

Four-parameter fit (A, C, , f)

Question: is the recovered fitted signal

really the origin input signal?!

Dynamic test
Three-parameter fit I

Simple calculation = system of linear

system of 3 equations is to be solved
~
x m A cos 2m fi C A cos 2mfiN C
fs

A cos cos 2m fi A sin sin 2m fi C

fs
fs

A cos cos 2mfiN A sin sin 2mfiN C

1
M

M 1

y
m

A
cos

cos
2

mf

A
sin

sin
2

mf

iN
iN

m0

2
~
2
E y x rms

Dynamic test
Three-parameter fit II
In matrix form:

y ~x

x P A cos , A sin , C

y Dx P y Dx P , where
T

1
cos2fiN
...
cos2 M - 1 fiN

y Dx

0
1
sin2fiN
1
...
...
sin2 M - 1 fiN 1

y Dx P
T

x P

xP D D

D y
1

Dynamic test
Three-parameter fit III
Necessary condition:
The input (and sampling) frequency
must be precisely known!!!
If not incorrect results SINAD,

SEE THE SIMULATION

Dynamic test
Four-parameter fit I

Unknown parameters: A, C, , f
Difficult calculation = system of nonlinear system of 4 equations is to be
solved
The system can be solved only by
iteration process

Dynamic test
Four-parameter fit II
Let x P A cos , A sin , C , fiN

x P j Aj cos j , Aj sin j , C j , fiN j

Let the first estimationfiN 0 f iN 0 0

is
1
T
Repeat
x P j D j D j DTj y fiN j fiN j 1 fiN j 1
calculation:

cos 2fiN j

D j

...

cos 2fiN j M 1

sin 2fiN j

...

sin 2fiN j M 1

A j 1 cos j 1 sin 2fiN j

A j 1 sin j 1cos 2fiN j

...
...
Aj 1 M 1 cos j 1 sin 2fiN j M 1

A j 1 M 1 sin j 1 cos 2fiN j M 1

Dynamic test
Four-parameter fit III

Problem with convergence one global

minimum and a few local minima
If the first estimation is incorrect the
iteration converges to the fault minimum

One of best estimations is the estimation from

spectrum within the interval (J-s, J+s):
Js

See the simulation

~
fiN

2
m
m

m J s

Js

2
Y
m

m J s

Dynamic test
Data processing in spectral
domain DFT test

Dynamic test
Data processing in spectral domain I

The same test setup, requirements

and the first step as for Data
processing in time domain
The DFT spectrum is calculated
from the record
Using the definitions (see the
beginning part of this lecture) the
unknown ADC parameters can be
estimated

Dynamic test
Data processing in spectral domain II

Common problem in praxis: incoherent

sampling leakage effect in the record
spectrum
Solution: applying a window function
(Hanning, 7 term Blackman-Harris, ) to
suppress the leakage effect and then
correction of results according the window
parameters (see the general theory of
windowing in DSP)

Introduced in detail in DYNAD

Rule: the higher the ADC resolution is, the lower
the side-lobes of the window have to be.
Nevertheless, lowering the side-lobes results in
increasing the main lobe width

Dynamic test
Data processing in spectral domain
III

Spectrum calculation:
Y i

M 1

w m x m e

j 2fiN

m 0

Error in coherency:fi J J fs

Processing gain

PG

M 1

2
T

w n

n 0
M 1

w n

n 0

M 1

A
T2

w n

n 0
M 1

2
w
n

n 0

Equivalent Noise
Bandwidth
M 1

ENBW

M w 2 n
n 0

n0

M 1

w n

i .m
M

Dynamic test
Data processing in spectral domain
IV

Changes in formulas: example 1: Noise

floor:
M / 2 1

NFl

k 1, k J 1, k rnd h( J j l

Y k

1 M
Y
2 2

M
hmax (2lmax 1)
2

h 2 hmax , l 0 lmax

Dynamic test
Data processing in spectral domain
V

Changes in formulas: example 2:

SINADY J NFl

W 0
2

SINADdB 10 log

AB

where :
M / 2 1

B ENBW

Y k 2lmax

Y rnd h J

h max
h 2

10 log ENBW 10 log

jr fs

W
c
M

k 1, k J 1, k rnd h( J j l

with l 0 lmax
and

1 M
2 NFl Y ,
2 2
2

W 0

fracr h J j fs

Wc

W 0

M 1

w n

n 0

f
Wc j s
M

i 2

e j fs
M

w t dt

Dynamic test
Conclusions

No method of data processing can be

suppose to be absolutely the best
Processing in time domain is less
sensitive on coherency but the 4parameter fit can be problematic
Processing in frequency domain gives
directly much more parameters but it
is very sensitive on coherency

The final conclusions

ADC testing is not a simple task

Extremely difficult task: to test ADC with
high resolution (more than 20 bits)
Methods are in the process = a challenge
for you
Another challenge: test procedures for
special ADC, e.g. band-pass for direct
digitalization and demodulation of high
frequency signals, etc.

Thank you for your

attention