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Combinational Loops

The document discusses combinational loops in integrated circuit design. It defines a combinational loop as a signal passing through combinational gates and returning to the starting gate without passing a sequential element. Unstable loops like ring oscillators can be used to characterize delay but should not be used for clock generation. Stable loops get stuck in one state and cause issues for testing controllability and observability. Combinational loops can also degrade signal slew over time, impacting timing and power. In general, combinational loops should be avoided except in special cases like ring oscillators used for testing.

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Sumanth Varma
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363 views3 pages

Combinational Loops

The document discusses combinational loops in integrated circuit design. It defines a combinational loop as a signal passing through combinational gates and returning to the starting gate without passing a sequential element. Unstable loops like ring oscillators can be used to characterize delay but should not be used for clock generation. Stable loops get stuck in one state and cause issues for testing controllability and observability. Combinational loops can also degrade signal slew over time, impacting timing and power. In general, combinational loops should be avoided except in special cases like ring oscillators used for testing.

Uploaded by

Sumanth Varma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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5/26/2016

4thMay2013

CombinationalLoops

CombinationalLoops

You would often hear backend engineers remonstrating the frontend


designfolksonthepresenceofcombinationalloopsinthedesign.Butwhy
dotheycreatesuchahueandcry?Whatpossiblycouldoneormaybefew
combinational loops do? Well, potentially, they can render the entire
functionality of the SoC haywire and not taken care off. And some
combinationalloops,ontheotherhand,areindispensablefortheevolution
ofaparticulartechnology.We'llseehowandwhy.
Acomboloopisstructurewhichisformedbyasignalstartingfrom
aninputofacombinationalgate,afterpassingthroughoneormore
combinational gate, reaches the same combo gate from which it
startedwithoutencounteringanysequentialelementinbetween.
Here'swhatageneralizedcombolooplookslike:

[http://2.bp.blogspot.com/
H1rZifRhEaI/UYS2XUcBcSI/AAAAAAAAAYw/3npxw2AGx8s/s1600/Combo_1.bmp]

UnstableLoops:Let's start with a basic combo loop that you must


have studied in your academics or at least heard about it. The
reverend Ring Oscillator. It is an inveterate fallacy that a ring
oscillator can be used to make a clock generating circuit. Trust me,
clock generating or even divider circuits, for that matter, are not as
simpleastheringoscillatorshownbelow.

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CombinationalLoops

ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmp]

Of what use could this simple circuit be? Well, if we can control any one
inputofanyofthethreeinvertersshownhere,wecanknowthedelayof
an inverter which is often the first cell to be characterized in any
technology.Moreover,teststructureslikethesealsohelpthefoundryguys
in determining the manufacturing process of a particular chip whether it
wasWCSorBCS.
Stable Loops: Here's an example of a stable loop consisting of an
OR gate. Note that, as soon as the free input receives a logic 1, the
output goes to 1.And same signal is conveyed back to the another
input,andtheloopisstableorratherstuckat1.

[http://2.bp.blogspot.com/
JnY0OX_pmk/UYS55Z9zMI/AAAAAAAAAZU/LLcnr4bKqZg/s1600/stable_loop.bmp]

Notethatstableloopswouldnotposeproblemsofcopiousdynamicpower
consumption. But such a loops pose headaches to DFT teams. Recall
fromthepost:TwoPillarsofDFT:Controllability&Observability [http://vlsi
soc.blogspot.in/2013/04/twopillarsofdftcontrollability.html] , we talked about
how stuckat faults are simulated and detected. If such a loop would be
presentinthedesign,anystuckatfaultsinthevicinityofthisgatecannot
beobserved,andhenceDFTteamwouldlosetheirstuckatcoveragebya
considerableamount!!
STA Concerns: We started this post with a preamble talking about
backendengineersrepiningthefrontendengineers.Howwouldabackend
engineerbeaffectedbyacomboloop?Here'show.
Recallfromthepost:FactorsAffectingDelaysofStandardCells [http://vlsi
soc.blogspot.in/2012/07/factorsaffectingdelaysofstandard.html] that the delay
andoutputslewofanystandardcelldependsontheinputslewandoutput
load.Thebelowfigureshowsonesuchexample,whereslewcankeepon
degrading indefinitely, and would ultimately impact the timing and more
importantlythepowerconsumptionoftheSoC.

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[http://4.bp.blogspot.com/
Rf8THNsxTw/UYTEVNL1EnI/AAAAAAAAAZg/C_Tocquhqx8/s1600/Slew_deg.bmp]

To sum up, combo loops must be avoided in all SoCs except for special
circumstances like ring oscillator circuit can be employed for testing
thecharacteristicsoftheSoC.

Posted4thMay2013byNamanGupta
Labels:CombinationalLoops,ComboLoops,RingOscillator,Slew
Degradation

7 Viewcomments

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