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ARM Interview Questions

This document summarizes the different processor modes in the ARM architecture: - System mode is the only non-privileged mode. - Supervisor (svc) mode is a privileged mode entered when executing an instruction that modifies bits of the CPSR register. - Abort, Undefined, Interrupt, and Fast Interrupt modes are privileged modes entered when certain exceptions occur. - Hyp mode is a hypervisor mode introduced in ARMv7 for hardware virtualization. The CPSR register bits represent the processor status including the current mode, condition codes from the ALU, interrupt disables, and more.

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15K views1 page

ARM Interview Questions

This document summarizes the different processor modes in the ARM architecture: - System mode is the only non-privileged mode. - Supervisor (svc) mode is a privileged mode entered when executing an instruction that modifies bits of the CPSR register. - Abort, Undefined, Interrupt, and Fast Interrupt modes are privileged modes entered when certain exceptions occur. - Hyp mode is a hypervisor mode introduced in ARMv7 for hardware virtualization. The CPSR register bits represent the processor status including the current mode, condition codes from the ALU, interrupt disables, and more.

Uploaded by

Akhilesh Chaudhry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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01/02/2016

ARMInterviewQuestions

Theonlynonprivilegedmode.
Systemmode

Theonlyprivilegedmodethatisnotenteredbyanexception.Itcanonlybeenteredbyexecutinganin
bitsoftheCPSR.
Supervisor(svc)mode
AprivilegedmodeenteredwhenevertheCPUisresetorwhenaSWIinstructionisexecuted.
Abortmode
Aprivilegedmodethatisenteredwheneveraprefetchabortordataabortexceptionoccurs.
Undefinedmode

Aprivilegedmodethatisenteredwheneveranundefinedinstructionexceptionoccurs.
Interruptmode
AprivilegedmodethatisenteredwhenevertheprocessoracceptsanIRQinterrupt.
FastInterruptmode
AprivilegedmodethatisenteredwhenevertheprocessoracceptsanFIQinterrupt.
Hypmode
Ahypervisormodeintroducedinarmv7aforcortexA15processorforprovidinghardwarevirtualizatio
Reference:http://en.wikipedia.org/wiki/ARM_architecture

ExplainaboutthebitsinCPSRregister.

Theindividualbitsrepresentthefollowing:
NNegativeresultfromALU.
ZZeroresultfromALU.
CALUoperationCarryout.
VALUoperationoVerflowed.
Qcumulativesaturation(alsodescribedassticky).
JindicateswhethertheprocessorisinJazellestate.
GE[3:0]usedbysomeSIMDinstructions.
IT[7:2]IfThenconditionalexecutionofThumb2instructiongroups.
Ebitcontrolsload/storeendianness.
Abitdisablesasynchronousaborts.
IbitdisablesIRQ.
FbitdisablesFIQ.
TbitindicateswhethertheprocessorisinThumbstate.
M[4:0]specifiestheprocessormode

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