Scribd Logo
Upload

Welcome to Scribd!

  • 67 views

    Scheme Quartus ASC Pentru Primul Subiect Poarta Şi

    Uploaded by

    Alin Chiper
    The document describes several digital logic components including basic logic gates (AND, OR, NOT, XOR, NAND, NOR), flip flops (D flip flop, D flip flop with clear), multiplexers, adders, decoders, ALUs, tri-state buffers, and shift registers. Code examples in VHDL are provided for the structural and behavioral modeling of each component.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Scheme Quartus ASC Pentru Primul Subiect Poarta Şi

    Uploaded by

    Alin Chiper
    67 views11 pages
    The document describes several digital logic components including basic logic gates (AND, OR, NOT, XOR, NAND, NOR), flip flops (D flip flop, D flip flop with clear), multiplexers, adders, decoders, ALUs, tri-state buffers, and shift registers. Code examples in VHDL are provided for the structural and behavioral modeling of each component.

    Original Title

    Scheme AuP

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document describes several digital logic components including basic logic gates (AND, OR, NOT, XOR, NAND, NOR), flip flops (D flip flop, D flip flop with clear), multiplexers, adders, decoders, ALUs, tri-state buffers, and shift registers. Code examples in VHDL are provided for the structural and behavioral modeling of each component.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    67 views11 pages

    Scheme Quartus ASC Pentru Primul Subiect Poarta Şi

    Uploaded by

    Alin Chiper
    The document describes several digital logic components including basic logic gates (AND, OR, NOT, XOR, NAND, NOR), flip flops (D flip flop, D flip flop with clear), multiplexers, adders, decoders, ALUs, tri-state buffers, and shift registers. Code examples in VHDL are provided for the structural and behavioral modeling of each component.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 11

    Scheme Quartus ASC

    Pentru PRIMUL SUBIECT


    POARTA I

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    entity poarta_AND is
    port(
    in1 : in STD_LOGIC;
    in2 : in STD_LOGIC;
    out1 : out STD_LOGIC
    );
    end poarta_AND;
    architecture behaviour of poarta_AND is
    begin
    out1 <= in1 and in2;
    end behaviour;
    POARTA SAU

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    entity poarta_OR is
    port(
    in1 : in STD_LOGIC;
    in2 : in STD_LOGIC;
    out1 : out STD_LOGIC
    );
    end poarta_OR;
    architecture behaviour of poarta_OR is
    begin
    out1 <= in1 or in2;
    end behaviour;

    POARTA NU

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    entity poarta_NOT is
    port(
    in1 : in STD_LOGIC;
    out1 : out STD_LOGIC
    );
    end poarta_NOT;
    architecture behaviour of poarta_NOT is
    begin
    out1 <= not in1;
    end behaviour;

    POARTA SAU-EXCLUSIV

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    ENTITY poarta_XOR is
    port(
    in1 : in STD_LOGIC;
    in2 : in STD_LOGIC;
    out1: out STD_LOGIC
    );
    END poarta_XOR;
    Architecture behaviour of poarta_XOR is
    begin
    out1 <= in1 xor in2;
    end behaviour;

    POARTA I-NU

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    ENTITY poarta_NAND is
    port(
    in1 : in STD_LOGIC;
    in2 : in STD_LOGIC;
    out1: out STD_LOGIC
    );
    END poarta_NAND;
    Architecture behaviour of poarta_NAND is
    begin
    out1 <= in1 nand in2;
    end behaviour;
    POARTA SAU-NU

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    ENTITY poarta_NOR is
    port(
    in1 : in STD_LOGIC;
    in2 : in STD_LOGIC;
    out1: out STD_LOGIC
    );
    END poarta_NOR;
    Architecture behaviour of poarta_NOR is
    begin
    out1 <= in1 nor in2;
    end behaviour;

    Pentru AL DOILEA SUBIECT

    bistabil de tip D activ pe front cu o intrare asincron de tergere

    library ieee ;
    use ieee.std_logic_1164.all;
    entity DFF_CLEAR is
    Port (CLK, CLEAR, D : in std_logic;
    Q : out std_logic);
    end DFF_CLEAR;

    architecture BEHAV_DFF of DFF_CLEAR is


    begin
    DFF_PROCESS: process (CLK, CLEAR)
    begin
    if (CLEAR = '1') then
    Q <= '0';
    elsif (CLK' event and CLK = '1') then
    Q <= D;
    end if;
    end process;
    end BEHAV_DFF;

    bistabil de tip D
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY D_flipflop IS PORT (
    D, Clock: IN STD_LOGIC;
    Q: OUT STD_LOGIC);
    END D_flipflop;
    ARCHITECTURE Behavior OF D_flipflop IS
    BEGIN
    PROCESS(Clock)
    BEGIN
    IF Clock'EVENT AND Clock = '1' THEN
    Q <= D;
    END IF;
    END PROCESS;
    END Behavior;

    multiplexor cu 4 intrri i 1 ieire

    Library ieee ;
    use ieee.std_logic_1164.all;
    entity MUX_4_1 is
    port ( SEL: in std_logic_vector(2 downto 1);
    A, B, C, D: in std_logic;
    Z: out std_logic);
    end MUX_4_1;
    architecture behav_MUX41 of MUX_4_1 is
    begin
    PR_MUX: process (SEL, A, B, C, D)
    begin
    case SEL is
    when "00" => Z <= A;
    when "01" => Z <= B;
    when "10" => Z <= C;
    when "11" => Z <= D;
    when others => Z <= 'X';
    end case;
    end process PR_MUX;
    end behav_MUX41;

    sumatorul complet pe un bit


    LIBRARY IEEE ;
    USE IEEE.STD_LOGIC_1164.ALL ;
    ENTITY fa IS PORT (
    Ci, Xi, Yi: IN STD_LOGIC ;
    Ci1, Si: OUT STD_LOGIC) ;
    END fa;
    ARCHITECTURE Dataflow OF fa IS
    BEGIN
    Ci1 <= (Xi AND Yi) OR (Ci AND (Xi XOR Yi));
    Si <= Xi XOR Yi XOR Ci;
    End Dataflow ;

    Combinaia dintre un sumator i un circuit de scdere

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;
    ENTITY AddSub IS
    GENERIC(n: NATURAL :=8); -- default number of bits = 8
    PORT ( A: IN std_logic_vector(n-1 downto 0);
    B: IN std_logic_vector(n-1 downto 0);
    subtract: IN std_logic;
    carry: OUT std_logic;
    sum: OUT std_logic_vector(n-1 downto 0));
    END AddSub;
    ARCHITECTURE Behavioral OF AddSub IS
    -- temporary result with one extra bit for carry
    SIGNAL result: std_logic_vector(n downto 0);
    BEGIN
    PROCESS(subtract, A, B)
    BEGIN
    IF (subtract = '0') THEN -- addition
    --add the two operands with one extra bit for carry
    result <= ('0' & A)+('0' & B);
    sum <= result(n-1 downto 0); -- extract the n-bit result
    carry <= result(n); -- extract the carry bit from result
    ELSE -- subtraction
    result <= ('0' & A)-('0' & B);
    sum <= result(n-1 downto 0); -- extract the n-bit result
    carry <= result(n); -- extract the borrow bit from result
    END IF;
    end process;
    END Behavioral;

    ALU

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY alu IS PORT (
    S: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    F: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
    END alu;
    ARCHITECTURE Behavior OF alu IS
    BEGIN
    PROCESS (S,A,B)
    BEGIN
    CASE S IS
    WHEN "000" => F<=A;
    WHEN "001" => F<=A AND B;
    WHEN "010" => F<=A OR B;
    WHEN "011" => F<=NOT A;
    WHEN "100" => F<=A+B;
    WHEN "101" => F<=A-B;
    WHEN "110" => F<=A+1;
    WHEN OTHERS => F<=A-1;
    END CASE;
    END PROCESS;
    END Behavior;

    Decodorul

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY Decoder IS PORT(
    E: IN STD_LOGIC; -- enable
    A: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- 3 bit address
    Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); -- data bus
    output
    END Decoder;
    ARCHITECTURE Behavioral OF Decoder IS
    BEGIN
    PROCESS (E, A)
    BEGIN
    IF (E = '0') THEN -- disabled
    Y <= (OTHERS => '0'); -- 8-bit vector of 0
    ELSE
    CASE A IS -- enabled
    WHEN "000" => Y <= "00000001";
    WHEN "001" => Y <= "00000010";
    WHEN "010" => Y <= "00000100";
    WHEN "011" => Y <= "00001000";
    WHEN "100" => Y <= "00010000";
    WHEN "101" => Y <= "00100000";
    WHEN "110" => Y <= "01000000";
    WHEN "111" => Y <= "10000000";
    WHEN OTHERS => NULL;
    END CASE;
    END IF;
    END PROCESS;
    END Behavioral;

    multiplexor cu 8 intrri i 1 ieire

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY Multiplexer IS
    PORT (S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
    D0,D1,D2,D3: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    Y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END Multiplexer;
    ARCHITECTURE Behavioral OF Multiplexer IS
    BEGIN
    PROCESS (S, D0,D1,D2,D3)
    BEGIN
    CASE S IS
    WHEN "00" =>Y<=D0;
    WHEN "01" =>Y<=D1;
    WHEN "10" =>Y<=D2;
    WHEN "11" =>Y<=D3;
    WHEN OTHERS =>Y<=(OTHERS => 'U');
    END CASE;
    END PROCESS;
    END Behavioral;
    ARCHITECTURE Dataflow OF Multiplexer IS
    BEGIN
    WITH S SELECT Y<=
    D0 WHEN "00",
    D1 WHEN "01",
    D2 WHEN "10",
    D3 WHEN "11",
    (OTHERS => 'U') WHEN OTHERS;
    END Dataflow;

    Buffer cu trei stri

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY TriState_Buffer IS PORT (
    E:IN STD_LOGIC;
    d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END TriState_Buffer;
    ARCHITECTURE Behavioral OF TriState_Buffer IS
    BEGIN
    PROCESS (E,d)
    BEGIN
    IF (E='1') THEN
    Y<=d;
    ELSE
    Y<= (OTHERS => 'Z');
    END IF;
    END PROCESS;
    END Behavioral;

    Registru de deplasare (Shifter)

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY shifter IS PORT (
    S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    input: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END shifter;
    ARCHITECTURE Behavior OF shifter IS
    BEGIN
    PROCESS (S, input)
    BEGIN
    CASE S IS
    WHEN "00" => output <=input;
    WHEN "01" => output <=input(6 DOWNTO 0) & '0';
    WHEN "10" => output <= '0' & input(7 DOWNTO 1);
    WHEN OTHERS => output <= input (0) & input (7 downto 1);
    end case;
    end process;
    end Behavior;

    You might also like