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Toy 1 CPU

This document summarizes the internal structure and operation of a simple CPU. It describes the main components of the CPU including registers, an ALU, memory, and a register file. It then walks through the step-by-step micro-operations needed to execute sample LOAD, ADD, and GOTO instructions using a TOY1 instruction set. This involves controlling data movement between components using control signals and multiplexers. Diagrams are provided and components are gradually added to fully depict the control and data flow within the CPU when executing each instruction type.

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ConradGodfrey
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© © All Rights Reserved
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187 views24 pages

Toy 1 CPU

This document summarizes the internal structure and operation of a simple CPU. It describes the main components of the CPU including registers, an ALU, memory, and a register file. It then walks through the step-by-step micro-operations needed to execute sample LOAD, ADD, and GOTO instructions using a TOY1 instruction set. This involves controlling data movement between components using control signals and multiplexers. Diagrams are provided and components are gradually added to fully depict the control and data flow within the CPU when executing each instruction type.

Uploaded by

ConradGodfrey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 24

Story so far

simplest description of computer?


what makes it general purpose?
CPU
CPU

Main Memory
Memory

wl 2012 7.1

Story so far
simplest description of computer?
what makes it general purpose?
CPU
CPU

Main Memory
Memory
Registers

Arithmetic & Logic Unit (ALU)

Control
Unit

Program

Data

this lecture: internal structure of the CPU


- how it relates to the instruction set
wl 2012 7.2

CPU Organisation: Overview


Memory

CPU
CPU
Register
file
2. Arithmetic/logic
R1..RN
1. Fast Memory

ALU

Input Reg1

Output Reg
Input Reg2
Program Counter

3. Control
Instr. Decoder

Instr. Register

Control Unit

I
n
t
e
r
n
a
l
B
u
s

Addres
s
Bus

000
001
002
003

Data
Bus

RAM

Control
Bus

3FD
3FE
3FF
wl 2012 7.3

TOY1 Instruction Set


OPCODE REG

4-bit

2-bit

ADDRESS

10-bit
if opcode=LOAD
then Rn = (a)
if opcode=ADD
then Rn = (b)
(a)

(b)

wl 2012 7.4

Micro-steps: LOAD R2,[201]

wl 2012 7.5

Understand CPU structure


step by step
step 1: just main elements, no connections, no control
step 2: add control elements, e.g. multiplexers (mux)
step 3: derive control signals: next lecture

Register Transfer Level (RTL) description: simple


6 registers: PC, IR, A1, A2, Aout, MDR (memory data register)
2 components respond in same cycle: UX, ALU, combinational
2 components have Read and Write signals: Memory, Register file

circuit diagram (see notes on basic logic design)


with or without control elements (e.g. mux)
with or without control unit
wl 2012 7.6

Abstraction: include the minimum


Control and next
instruction logic

Mread Mwrite
addr

IR

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write
MDR

Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.7

+1

Mread Mwrite

81

IR

80
addr

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write

store in 80

MDR

Register
File
data

LOAD R2,[201]:
1. PC=PC+1, IR=M[PC]

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.8

C1

IR0-3

Control
Unit

C2
Mread

IR6-15
Mread Mwrite

IR

201
UX

addr

Write

PC

A2
Rread

Rwrite

Memory

09
data
Write
MDR

LOAD R2,[201]:
2. MDR = M[addr]
addr = UX(IR6..15)
UX: Unsign eXtension
from 10 to 16 bits

Write

ALU

index
Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.9

Mread Mwrite

IR
IR4-5

addr

A2

Write

PC

Memory

Rread

Write

ALU

index

data
Write

09
MDR

Register
File
data

LOAD R2,[201]:
3. R[IR4..5] = MDR

Rwrite

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.10

C1

Control
Unit

C2
Mread

Mread Mwrite

IR

UX

addr

Write

PC

A2
Rread

Rwrite

Memory

Write
index

data
Write

LOAD R2,[201]:
2. MDR = M[addr]
addr = UX(IR6..15)
but step 1: IR = M[PC]
so need mux

ALU

MDR

Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.11

+1
C1

Control
Unit

C2
Mread

Mread Mwrite

IR

UX

M1

addr

Write

PC

A2
Rread

Rwrite

Memory

Write

C1

ALU

index

data
Write
MDR

Register
File
data

include mux M1

Write

A1
Write

Aout

ALU control

Write
P

Q 1
C

if C = 0 then P
if C = 1 then Q

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
1 multiplexer signal

wl 2012 7.12

Micro-steps: ADD R2,[202]

wl 2012 7.13

+1

Mread Mwrite

82

IR

81
addr

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write

store in 81

MDR

Register
File
data

ADD R2,[202]:
1. PC=PC+1, IR=M[PC]

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.14

C1

Control
Unit

C2
Mread

Mread Mwrite

IR

202
UX

addr

Write

PC

A2
Rread

Rwrite

Memory

06
data
Write
MDR

ADD R2,[202]:
2. MDR = M[addr]
addr = UX(IR6..15)

Write

ALU

index
Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.15

2
Mread Mwrite
addr

IR
IR4-5
A2

Write

Rread

PC

Rwrite

Memory

Write
index

data
Write

Register
File

MDR

ADD R2,[202]:
3. A1 = R[IR4..5]
A2 = MDR

ALU

06

data

Aout
Write

A1

09
Write

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.16

Mread Mwrite
addr

IR

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write
MDR

ADD R2,[202]:
4. Aout = A1 + A2

0F

06

Register
File
data

Aout
Write

A1

09
Write

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.17

2
Mread Mwrite
addr

IR
IR4-5
Write

PC

A2
Rread

Rwrite

Memory

Write
index

data
Write
MDR

ADD R2,[202]:
5. R[IR4..5] = Aout

ALU

Register
File
data

Aout
Write

A1
Write

0F

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.18

Mread Mwrite

IR
IR4-5

addr

A2

Write

PC

Memory

Rwrite
Write

ALU

index

data
Write

Recall:
LOAD R2,[201]:
3. R[IR4..5] = MDR
and
ADD R2,[202]:
5. R[IR4..5] = Aout

Rread

09
MDR

Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.19

Mread Mwrite
addr

IR

A2

Write

Rread

PC

Rwrite

Memory

Write
index

data
Write

Register
File

MDR

M2
Write
P

Q 1
C

if C = 0 then P
if C = 1 then Q

ALU

data

C2

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

Write

A1
Write

Aout

ALU control

include mux M2
10 read/write signals
1 ALU Control signal
1 multiplexer signal

wl 2012 7.20

+1

Mread Mwrite

83

IR

82
addr

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write

store in 82

MDR

Register
File
data

GOTO 300
1. PC=PC+1, IR=M[PC]

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.21

C1

300

addr

IR6-15

IR

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write
MDR

Register
File
data

GOTO 300
2. PC = UX(IR6..15)

UX

C2
Mread

300
Mread Mwrite

IR0-3

Control
Unit

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
wl 2012 7.22

+1
C1

Control
Unit

M3
UX

C2

C3

Mread

include
mux M3

IR6-15
Mread Mwrite
addr

C4 or A10

IR

Write

PC

A2
Rread

Rwrite

Memory

Write

ALU

index

data
Write
MDR

Register
File
data

Write

A1
Write

Aout

ALU control

Write

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
2 multiplexer signals

wl 2012 7.23

+1
C1

Control
Unit

M3
UX

C2
Mread

C3

IR0-3
IR6-15

IR6-15
Mread Mwrite

C4 or A10

IR
IR4-5

UX

M1

addr

A2

Write

Rread

PC

Rwrite

Memory

Write

C1

index

data
Write

Register
File

MDR

M2
Write

Now put everything


together!

ALU

data

Write

A1
Write

Aout

ALU control

C2

if ALU Control = 0 then Aout = A1 + A2


if ALU Control = 1 then Aout = A1 - A2

10 read/write signals
1 ALU Control signal
4 multiplexer signals

wl 2012 7.24

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