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Introduction To Input-Output Devices

The document discusses input/output devices for the 8085A microprocessor. It notes that the 8085A has separate 16-bit memory and 8-bit I/O address spaces distinguished by the IO/M status line. Memory instructions access the memory space while the IN and OUT instructions access the I/O space. A simple input device uses tri-state buffers to connect an input data source to the data bus, controlled by address decoding. A simple output device uses latches to connect the data bus to a peripheral device. Address and control lines are used to select devices and ports.

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17 views

Introduction To Input-Output Devices

The document discusses input/output devices for the 8085A microprocessor. It notes that the 8085A has separate 16-bit memory and 8-bit I/O address spaces distinguished by the IO/M status line. Memory instructions access the memory space while the IN and OUT instructions access the I/O space. A simple input device uses tri-state buffers to connect an input data source to the data bus, controlled by address decoding. A simple output device uses latches to connect the data bus to a peripheral device. Address and control lines are used to select devices and ports.

Uploaded by

نورول نضيره رشدي
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Introduction to Input-Output

Devices

05/28/16

8085A Address Space


Unlike modern microprocessors, the 8085A microprocessor has
two address spaces. A 16-bit address space, nominally for
memory devices
An 8-bit address space, nominally for
input/output devices
The two address spaces are distinguished by the processor by
the state of the IO / M status line.

05/28/16

Memory and IO Instructions

Separate sets of instructions are used to access storage locations in the


memory address space of the processor and the IO address space of the
processor.

All external data transfer instructions other the IN port and OUT port access
addresses in the memory space of the processor. Execution of this class of
data transfer instruction forces the status line IO / M* to be logic 0.

The instruction IN port reads 8-bits of data from the I/O location with the 8bit address port. Execution of this instruction forces the status line IO / M*
to be logic 1.

The instruction OUT port writes 8-bits of data to the I/O location with the 8bit address port. Execution of this instruction forces the status line IO / M*
to be logic 1.

05/28/16

A Simple Two-Port, Input


Device
In its most simplistic form an input
port comprises a set of tri-state
buffers.
The input to the buffers is connected
to the data source. The outputs of the
buffers are connected to the
processors data bus.
Buffer control is provided by
combinational circuitry receiving
inputs from the processors control
and address busses and from
external IO decoding logic.

05/28/16

Control Inputs to IO Port


The address input connections to the IO device provide a
mechanism to select a particular 8-bit port from the ports within
the device.
The RD/ input line specifies when the input tri-state buffers can
be enabled onto the data bus.
The CS/ input line enables the processor to select a particular
IO device when the computer system has a number of IO
devices.
The CS/ line is usually fed from the output of decoding logic
which decodes high order address lines.

05/28/16

Example of IO Decoding

05/28/16

A Simple Two-Port, Output


Device
In its most simplistic form an
output port comprises a set of
data latches buffers.
The outputs of the latches are
connected to the peripheral
device. The inputs to the latches
are connected to the processors
data bus.
Latch control is provided by
combinational circuitry receiving
inputs from the processors
control and address busses and
from external IO decoding logic.

05/28/16

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