!

2!

CHAPTER 1
1.1

Base-10:
Octal:
Hex:
Base-12

16 17
20 21
10 11
14 15

1.2

(a) 32,768

18
22
12
16

19
23
13
17

20
24
14
18

21
25
15
19

(b) 67,108,864
3

22 23 24 25
26 27 30 31
16 17 18 19
1A 1B 20 21

26 27 28 29 30
32 33 34 35 36
1A 1B 1C 1D 1E
22 23 24 25 26

31
37
1F
27

32
40
20
28

(c) 6,871,947,674

(4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 58010

1.3

(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010

! !
!
! !
!
1.4

1.5

(435)8!=!4!*!82!+!3!*!81!+!5!*!80!=!28510!

(345)6!=!3!*!62!+!4!*!61!+!5!*!60!=!13710!
16-bit binary: 1111_1111_1111_1111
Decimal equivalent:
216 -1 = 65,53510
Hexadecimal equivalent: FFFF16
!
Let b = base
(a) 14/2 = (b + 4)/2 = 5, so b = 6
(b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 4, and b = 8
(c) (2 *b + 4) + (b + 7) = 4b, so b = 11

1.6

(x 3)(x 6) = x2 (6 + 3)x + 6*3 = x2 -11x + 22

Therefore: 6 + 3 = b + 1m, so b = 8
Also, 6*3 = (18)10 = (22)8

!
1.7

64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8

1.8

(a) Results of repeated division by 2 (quotients are followed by remainders):

43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1)
Answer: 1111_10102 = FA16

3(0)

1(1)

(b) Results of repeated division by 16:

43110 = 26(15); 1(10) (Faster)
Answer: FA = 1111_1010
1.9

(a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125

(b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125
(c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125
(d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875

Digital'Design'With'An'Introduction'to'the'Verilog'HDL''Solution'Manual.!M.!Mano.!M.D.!Ciletti,!Copyright!2012,!!
All!rights!reserved.!

3!

(e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125

!
1.10

(a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310

(b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510'

!
!
! !
1.11

Reason: 110.0102 is the same as 1.100102 shifted to the left by two places.
!

!
1011.11
101 | 111011.0000
101
01001
101
1001
101
1000
101
0110
The quotient is carried to two decimal places, giving 1011.11
Checking: 1110112 / 1012 = 5910 / 510 1011.112 = 58.7510

1.12

(a) 10000 and 110111

1011
+101
10000 = 1610

1011
x101
1011
1011
110111 = 5510

(b) 62h and 958h

2Eh
+34 h
62h

1.13
!

0010_1110
0011_0100
0110_0010 = 9810

2Eh
x34h
B 38
2
8A
9 5 8h = 239210

(a) Convert 27.315 to binary:

27/2 =
13/2
6/2
3/2

Integer
Quotient
13
6
3
1
0

Remainder
+
+
+
+
+

Coefficient
a0 = 1
a1 = 1
a2 = 0
a3 = 1
a4 = 1

Digital'Design'With'An'Introduction'to'the'Verilog'HDL''Solution'Manual.!M.!Mano.!M.D.!Ciletti,!Copyright!2012,!!
All!rights!reserved.!

4!

2710 = 110112
.315 x 2
.630 x 2
.26 x 2
.52 x 2

=
=
=
=

Integer
0
1
0
1

+
+
+
+

Fraction
.630
.26
.52
.04

Coefficient
a-1 = 0
a-2 = 1
a-3 = 0
a-4 = 1

.31510 .01012 = .25 + .0625 = .3125

27.315 11011.01012
(b) 2/3 .6666666667
.6666_6666_67 x 2
.3333333334 x 2
.6666666668 x 2
.3333333336 x 2
.6666666672 x 2
.3333333344 x 2
.6666666688 x 2
.3333333376 x 2

Integer
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0

+
+
+
+
+
+
+
+

Fraction
.3333_3333_34
.6666666668
.3333333336
.6666666672
.3333333344
.6666666688
.3333333376
.6666666752

Coefficient
a-1 = 1
a-2 = 0
a-3 = 1
a-4 = 0
a-5 = 1
a-6 = 0
a-7 = 1
a-8 = 0

.666666666710 .101010102 = .5 + .125 + .0313 + ..0078 = .664110

.101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)).
1.14

`
1.15

(a)

0001_0000
1s comp: 1110_1111
2s comp: 1111_0000

(b)

0000_0000
1s comp: 1111_1111
2s comp: 0000_0000

(c)

1101_1010
1s comp: 0010_0101
2s comp: 0010_0110

(d)

1010_1010
1s comp: 0101_0101
2s comp: 0101_0110

(e)

1000_0101
1s comp: 0111_1010
2s comp: 0111_1011

(f)

1111_1111
1s comp: 0000_0000
2s comp: 0000_0001

(a)

25,478,036
9s comp: 74,521,963
10s comp: 74,521,964

(b)

63,325,600
9s comp: 36,674,399
10s comp: 36,674,400

(c)

25,000,000
9s comp: 74,999,999
10s comp: 75,000,000

(d)

00000000
9s comp: 99999999
10s comp: 100000000

!
1.16
15s comp:
16s comp:
1.17

C3DF
3C20
3C21

C3DF: 1100_0011_1101_1111
1s comp: 0011_1100_0010_0000
2s comp: 0011_1100_0010_0001 = 3C21

(a) 2,579 02,579 97,420 (9s comp) 97,421 (10s comp)

4637 2,579 = 2,579 + 97,421 = 205810
(b) 1800 01800 98199 (9s comp) 98200 (10 comp)
125 1800 = 00125 + 98200 = 98325 (negative)
Magnitude: 1675
Result: 125 1800 = 1675

Digital'Design'With'An'Introduction'to'the'Verilog'HDL''Solution'Manual.!M.!Mano.!M.D.!Ciletti,!Copyright!2012,!!
All!rights!reserved.!

5!

(c) 4,361 04361 95638 (9s comp) 95639 (10s comp)

2043 4361 = 02043 + 95639 = 97682 (Negative)
Magnitude: 2318
Result: 2043 6152 = -2318
(d) 745 00745 99254 (9s comp) 99255 (10s comp)
1631 -745 = 01631 + 99255 = 0886 (Positive)
Result: 1631 745 = 886
'
1.18

1.19

Note: Consider sign extension with 2s complement arithmetic.

(a)

0_10010
(b)
0_100110
1s comp: 1_01101
1s comp: 1_011001 with sign extension!
2s comp: 1_01110
2s comp: 1_011010
0_10011
0_100010
Diff:
0_00001 (Positive)
1_111100 sign bit indicates that the result is negative
Check:19-18 = +1
0_000011 1s complement
0_000100 2s complement
000100 magnitude
Result: -4
Check: 34 -38 = -4

(c)

0_110101
(d)
1s comp: 1_001010
1s comp:
2s comp: 1_001011
2s comp:
0_001001
Diff:
1_010100 (negative)
0_101011 (1s comp)
0_101100 (2s complement)
101100 (magnitude)
-4410 (result)

0_010101
1_101010 with sign extension!
1_101011
0_101000
0_010011 sign bit indicates that the result is positive
Result: 1910
Check: 40 21 = 1910

+9286 009286; +801 000801; -9286 990714; -801 999199

(a) (+9286) + (_801) = 009286 + 000801 = 010087
(b) (+9286) + (-801) = 009286 + 999199 = 008485
(c) (-9286) + (+801) = 990714 + 000801 = 991515
(d) (-9286) + (-801) = 990714 + 999199 = 989913

!
1.20

+49 0_110001 (Needs leading zero extension to indicate + value);

+29 0_011101 (Leading 0 indicates + value)
-49 1_001110 + 0_000001 1_001111
-29 1_100011 (sign extension indicates negative value)
(a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.)
Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20
(b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value)
(-29) + (+49) = +20

Digital'Design'With'An'Introduction'to'the'Verilog'HDL''Solution'Manual.!M.!Mano.!M.D.!Ciletti,!Copyright!2012,!!
All!rights!reserved.!