RC4558 Dual General-Purpose Operational Amplifier: 1 Features 3 Description
RC4558 Dual General-Purpose Operational Amplifier: 1 Features 3 Description
RC4558 Dual General-Purpose Operational Amplifier: 1 Features 3 Description
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RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
3 Description
2 Applications
PART NUMBER
PACKAGE (PIN)
BODY SIZE
SOIC (8)
4.90 mm 3.91 mm
SOIC (8)
3.00 mm 3.00 mm
PDIP (8)
9.81 mm 6.35 mm
TSSOP (8)
3.00 mm 4.40 mm
SOP (8)
6.20 mm 5.30 mm
VIN
RIN
RG
VOUT
RF
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
4 Revision History
Changes from Revision F (September 2010) to Revision G
Page
Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
RC4558
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1OUT
1IN
1IN+
VCC
VCC+
2OUT
2IN
2IN+
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
1IN+
Noninverting input
1IN-
Inverting Input
1OUT
Output
2IN+
Noninverting input
2IN-
Inverting Input
2OUT
Output
VCC+
Positive Supply
VCC-
Negative Supply
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC+
VCC
MAX
18
18
UNIT
V
VID
30
VI
15
(5)
Unlimited
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC.
Differential voltages are at IN+ with respect to IN.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
-65
150
500
1000
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MIN
MAX
15
15
RC4558
70
RC4558I
40
85
Supply voltage
Operating free-air temperature
UNIT
V
C
DGK
97
172
PS
PW
UNIT
95
149
C/W
8 PINS
RJA
(1)
85
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RC4558
www.ti.com
PARAMETER
VIO
VO = 0
IIO
VO = 0
IIB
VO = 0
VICR
(2)
25C
12
14
12
14
13
25C
10
Full range
10
25C
20
Full range
15
25C
ri
Input resistance
25C
CMRR
25C
AVD = 100,
RS = 100 ,
f = 1 kHz,
BW = 1 Hz
ICC
VO = 0,
No load
PD
VO1/VO2
(1)
(2)
VO = 0,
No load
Crosstalk attenuation
AVD = 100
RS = 1 k,
f = 10 kHz
mV
200
nA
500
nA
800
25C
Unity-gain bandwidth
Vn
150
25C
B1
UNIT
300
25C
RL 2 k,
VO = 10 V
Full range
MAX
7.5
Full range
AVD
kSVS
TYP
0.5
25C
RL = 2 k
VCC = 15 V
to 9 V
MIN
Full range
RL = 10 k
VOM
TA
V
V
300
V/mV
MHz
0.3
70
90
dB
25C
30
25C
25C
V/V
150
nV/Hz
2.5
5.6
TA min
6.6
TA max
2.3
25C
75
170
TA min
90
200
TA max
70
150
85
25C
mA
mW
dB
105
All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified.
Full range is 0C to 70C for RC4558 and 40C to 85C for RC4558I.
TEST CONDITIONS
MIN
Rise time
VI = 20 mV,
RL = 2 k,
CL = 100 pF
Overshoot
VI = 20 mV,
RL = 2 k,
CL = 100 pF
VI = 10 V,
RL = 2 k,
CL = 100 pF
TYP
MAX
0.13
ns
5%
1.1
1.7
UNIT
V/s
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
5
ICC Supply Current mA
0
0
10
12
14
16
18
0
-55
20
-35
-15
25
45
65
40
30
-20
-60
10
-100
-120
Phase
-60
Gain
10
-140
-160
-10
-40
20
Gain dB
-80
Gain
Phase deg
20
Gain dB
30
-40
Phase
-160
-180
-200
10000
-20
100
10
25
VOM Output Voltage Swing V
30
-5
-10
-15
12
14
16
20
15
10
0
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
10
100
10k
100k 1.E+06
1
1k
1M
18
f Frequency Hz
-200
10000
15
10
1000
f Frequency kHz
-120
-140
-10
f Frequency kHz
-80
-100
-180
1000
125
-20
-20
100
105
85
TA Temperature C
Phase deg
RC4558
www.ti.com
32
14.75
28
30
26
24
22
20
18
16
14.5
14.25
14
13.75
13.5
13.25
14
12
100
1000
13
-55
10000
-35
-15
25
45
65
85
105 125
TA Temperature C
RloadR Load
LoadResistance
Resistance W
L
-12
110
100
-12.5
-12.25
-12.75
-13
-13.25
-13.5
90
80
70
60
50
40
30
20
-13.75
10
-14
-55
-35 -15
25
45
65
85
0
100
1.E+02
105 125
1k
1.E+03
TA Temperature C
10k
1.E+04
100k
1.E+05
1M
1.E+06
10M
1.E+07
f Frequency Hz
200
0.003
190
0.002
180
170
160
150
140
130
120
0.001
-0.001
-0.002
110
100
-55
-35
-15
25
45
65
85
-0.003
-55
105 125
-35 -15
25
45
65
85
105 125
TA Temperature C
TA Temperature C
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
Input
NoiseVoltage
VoltagenV/rt(Hz)
nV/Hz
Vn Vn Input
Noise
14
12
10
8
6
0
10
1.E+01
100
1.E+02
1k
1.E+03
10k
1.E+04
100k
1.E+05
f Frequency Hz
RC4558
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7 Detailed Description
7.1 Overview
The RC4558 device is a dual general-purpose operational amplifier, with each half electrically similar to the
A741, except that offset null capability is not provided.
The high common-mode input voltage range and the absence of latch-up make this amplifier ideal for voltagefollower applications. The device is short-circuit protected, and the internal frequency compensation ensures
stability without external components.
IN
IN+
OUT
VCC
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
R2
15 V
R1
VOUT+
R3
VREF
12 V
R4
VDIFF
VOUT+
+
VIN
10
RC4558
www.ti.com
(1)
R 44 R22
R2
VOUT
- VINin 2
out - = VREF
ref
1 +
+ R 44
R11
R11
R33+
(2)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to the VREF. The differential output range is
2VREF. Furthermore, the common mode voltage will be one half of VREF (see Equation 7).
R
R4
R2
VD IF F = V O U T + - V O U T - = VIN 1 + 2 - VR E F
1 +
R1
R1
R3 + R4
VOUT+ = VIN
VOUT = VREF VIN
VDIFF = 2VIN VREF
(3)
(4)
(5)
(6)
+ VOUT - 1
V
Vcm = OUT +
= VREF
2
(7)
11
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
16
12
14
12
VOUT+ (V)
VDIFF (V)
8
4
0
10
8
6
2
0
12
0
10
VIN (V)
12
6
VIN (V)
C003
10
12
C001
12
10
VOUTt (V)
8
6
4
2
0
0
VIN (V)
10
12
C002
12
RC4558
www.ti.com
Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
13
RC4558
SLOS073G MARCH 1976 REVISED OCTOBER 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
RIN
RG
VOUT
RF
VS+
RF
OUT1
VCC+
GND
IN1
OUT2
VIN
IN1+
IN2
VCC
IN2+
RG
GND
RIN
Use low-ESR, ceramic
bypass capacitor
RC4558
www.ti.com
11.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
15
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (C)
Device Marking
(4/5)
RC4558-W
ACTIVE
WAFERSALE
YS
RC4558D
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558DE4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558DG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558DGKR
ACTIVE
VSSOP
DGK
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
RC4558DGKRG4
ACTIVE
VSSOP
DGK
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RC4558DR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558DRG3
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558DRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RC4558
RC4558ID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
R4558I
RC4558IDGKR
ACTIVE
VSSOP
DGK
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
RC4558IDGKRG4
ACTIVE
VSSOP
DGK
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RC4558IDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
R4558I
RC4558IDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
R4558I
RC4558IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
RC4558IP
RC4558IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
RC4558IP
RC4558IPW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
R4558I
Addendum-Page 1
Samples
www.ti.com
24-Apr-2015
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
Device Marking
(4/5)
RC4558IPWR
ACTIVE
TSSOP
PW
R4558I
RC4558IPWRE4
ACTIVE
TSSOP
PW
TBD
Call TI
Call TI
-40 to 85
RC4558IPWRG4
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
-40 to 85
RC4558P
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
RC4558P
RC4558PE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
RC4558P
RC4558PSLE
OBSOLETE
SO
PS
TBD
Call TI
Call TI
0 to 70
RC4558PSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
R4558
RC4558PSRG4
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
R4558
RC4558PW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
R4558
RC4558PWLE
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
0 to 70
RC4558PWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
RC4558PWRE4
ACTIVE
TSSOP
PW
TBD
Call TI
Call TI
0 to 70
RC4558PWRG4
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
0 to 70
RC4558Y
OBSOLETE
DIESALE
TBD
Call TI
Call TI
R4558
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
Samples
www.ti.com
24-Apr-2015
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
15-Sep-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
RC4558DGKR
VSSOP
DGK
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
RC4558DR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
RC4558DR
SOIC
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
RC4558DR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
RC4558DRG3
SOIC
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
RC4558DRG4
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
RC4558DRG4
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
RC4558IDGKR
VSSOP
DGK
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
RC4558IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
RC4558IPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
RC4558IPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
RC4558PSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
RC4558PWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
RC4558PWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
15-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
RC4558DGKR
VSSOP
DGK
2500
364.0
364.0
27.0
RC4558DR
SOIC
2500
340.5
338.1
20.6
RC4558DR
SOIC
2500
364.0
364.0
27.0
RC4558DR
SOIC
2500
367.0
367.0
35.0
RC4558DRG3
SOIC
2500
364.0
364.0
27.0
RC4558DRG4
SOIC
2500
340.5
338.1
20.6
RC4558DRG4
SOIC
2500
367.0
367.0
35.0
RC4558IDGKR
VSSOP
DGK
2500
364.0
364.0
27.0
RC4558IDR
SOIC
2500
340.5
338.1
20.6
RC4558IPWR
TSSOP
PW
2000
364.0
364.0
27.0
RC4558IPWR
TSSOP
PW
2000
367.0
367.0
35.0
RC4558PSR
SO
PS
2000
367.0
367.0
38.0
RC4558PWR
TSSOP
PW
2000
367.0
367.0
35.0
RC4558PWR
TSSOP
PW
2000
364.0
364.0
27.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 0.65
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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PW0008A
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
4
(5.8)
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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PW0008A
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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