5

=46<67(0%/2&.',$*5$0

BOM MARK
IV@: INT VGA

DDR3 PWR

EV@: STUFF FOR EXT VGA

THERMAL
PROTECTION

X'TAL
14.318MHz

SP@: STUFF FOR UMA or VGA

Penryn 478

5(9%

CHARGER

TPS51116

uFCPGA

CLOCK GENERATOR
ICS:
SELGO: SLG8SP513VTR

Fan Driver

Thermal Sensor
(G780P81U)

P3, P4

P3

(G991)

P40

ISL88731A

3/5V SYS PWR

P44

CPU CORE PWR

P42

VGA CORE
MAX8792

P2

P37

RT8206

DISCHARGER

P25

P36

P39

ISL6266A

+1.05V
P41

P38

UP6111A

FSB
667/800/1067 Mhz

EXT_LVDS

ATI-Park

DDRIII
Dual Channel DDR3
667/800 MHz

SO-DIMM 0
SO-DIMM 1
P16,P17

Cantiga
(GM45/ PM45/ GL40)

P24

SWITCH

EXT_HDMI

VRAM DDRIII
512MB P18-P23

NB

CRT

EXT_CRT

PCIE 16X

LVDS

LVDS

INT_LVDS

RGB

INT_CRT

P24

CIRCUIT
HDMI
P25

P25
C

P5, P6, P7, P8, P9, P10, P11

HDMI switch
(PS8101T)

INT_HDMI

P25

X4 DMI interface

HDD (SATA) *1
P26

Ext USB Port x 2

P27

USB 0,2

SATA0

ODD (SATA)

Int USB Port x 1

P27

USB 6

Bluetooth
USB3

SATA1

P26

USB 2.0

PCI-Express

SB

P27

ICH9M

USB1

P27

Azalia
P24

USB11

Mini Card
WLAN

X'TAL
32.768KHz

CCD

PCIE-4

PCIE-6

Media
Cardreader

LPC

Giga-LAN

(AU6437)

Audio CODEC
P28
(272)

USB2

EC (WPC781)
P33

X'TAL
25MHz

P12,P13,P14,P15

BCM57780
P30

P30

X'TAL
32.768KHz

Card Reader
Connector

SPI ROM

Transformer

P31

P32

P33

Audio Amplifier
G1453L P28

MIC Jack

RJ45

Int. MIC

P29

P29

P31

Touch Pad

K/B COON.

P26

P33

352-(&7=4
4XDQWD&RPSXWHU,QF

Int.
Speaker
P29

Size

Document Number

Rev
1A

Block Diagram
Date:
5

Monday, July 12, 2010

Sheet 1
1

of

43

&ORFN*HQHUDWRU&/.

+3V

C573

C574

C545

C568

C551

C546

C435

L43
+1.05V
PBY160808T-301Y-N/2A/300ohm_6
C437

*10u/10V_8

10u/10V_8

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

*0.1u/10V_4

9
16
23
4

VDD_CK_VDD_REF

46
62
+1.05V_VDD

19
27
33
52
43
56

10u/10V_8

VDD_PCI
VDD_48
VDD_PLL3
VDD_REF

IO_VOUT
SCLK
SDA

CK505

VDD_SRC
VDD_CPU

SRC5/PCI_STOP#
SRC5#/CPU_STOP#

VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO

CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#

SATA_CLKREQ#_R 8

14 SATACLKREQ#

R321

31 LAN_CLKREQ#

R325

475/F_4

LAN_CLKREQ#_R 10

R330

33_4

PCLK_DEBUG_R

11

475/F_4

PCI_CLK_SIO

12

T95
C

35
13

R334

33_4

PCLK_591_R

13

PCLK_ICH R346

33_4

PCLK_ICH_R

14

PCLK_591
PCLK_ICH

CG_XIN

CG_XOUT
R345
R337
CPU_BSEL0 R338
CPU_BSEL1
CPU_BSEL2 R314
R318

33 CLK_Card48
14 CLKUSB_48

14

14M_ICH

22_4
22_4
2.2K_4

17

FSA

64
10K_4
33_4

5
65
15
18
22
26
59
30
36
49
1

FSC

CG_XIN

C549
33p/50V_4

Y2

CL=20p
14.318MHZ

C548
33p/50V_4

PM_STPPCI#

R313

*2.2K_4

PM_STPCPU#

R316

*2.2K_4

02

5/7 Modfiy

CLK_PCIE_SRC11# R322

10K_4

SATA_CLKREQ#_R R324

10K_4

LAN_CLKREQ#_R

R320

10K_4

U15

C541

28 PCLK_DEBUG

+1.05V_VDD

Modfiy it 5/4

PBY160808T-301Y-N/2A/300ohm_6
C544
+3V
L42
*0.1u/10V_4
C434
*0.1u/10V_4
C542
*10u/10V_8
C569
0.1u/10V_4
C557
0.1u/10V_4
C550
0.1u/10V_4
C450
0.1u/10V_4

CG_XOUT

PCI0/CR#_A

SRC10#
SRC10

PCI1/CR#_B
SRC11/CR#_H
SRC11#/CR#_G

PCI2/TME
PCI3

SRC9
SRC9#

PCI4/SRC5_EN
SRC7/CR#_F
SRC7#/CR#_E

PCIF5/ITP_EN
XTAL_IN

SRC6
SRC6#

XTAL_OUT
SRC4
SRC4#

USB_48/FSA
FSB/TEST/MODE

SRC3/CR#_C
SRC3#/CR#_D

REF0/FSC/TESTSEL
VSS_BODY
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF

SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
CKPWRGD/PWRDWN#

55
7
6

SMBCK1
SMBDT1

45
44

PM_STPPCI#
PM_STPCPU#

61
60
58
57
54
53

CLK_MCH_OE#_C R319
CLK_PCIE_SRC11# R323

475/F_4
475/F_4

CLK_PCIE_SRC7
CLK_PCIE_SRC7#

R349

10K_4

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

To CPU

CLK_MCH_OE#_C

R317

10K_4

CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5

To NB

PCLK_591_R

C571

*33p/50V_4

CLK_PCIE_3GPLL# 6
CLK_PCIE_3GPLL 6

To NB

CLKUSB_48

C581

*15p/50V_4

14M_ICH

C554

*33p/50V_4

PCLK_ICH_R

C578

*33p/50V_4

CLK_PCIE_SRC3
CLK_PCIE_SRC3#

CLK_PCIE_MINI1 28
CLK_PCIE_MINI1# 28

To Mini Card 1 (WLAN)

CLK_PCIE_ICH 13
CLK_PCIE_ICH# 13

To ICH

SEL2 SEL1

34
35
R348

*EV@475/F_4

24
25

CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R

20
21

CLK_DREFCLK_R
CLK_DREFCLK#_R

CLK_PCIE_LAN 31
CLK_PCIE_LAN# 31

To LAN

PEG_CLKREQ# 19

Modfiy it 5/4

CLK_PCIE_SATA 12
CLK_PCIE_SATA# 12

To ICH
To NB or VGA
To NB or VGA

63

SEL0

FSC FSB FSA

T97

28
29

5/5 Add

For EMI

T94
T93

48
47

31
32

CLK_PCIE_SRC3

CLK_MCH_OE# 6
MINI_CLKREQ# 28

37
38
51
50

To SB

T91
T92

42
41
40
39

PM_STPPCI# 14
PM_STPCPU# 14

Frequence select
CPU

SRC

PCI

100

100

33

133

100

33

166

100

33

200

100

33

266

100

33

333

100

33

400

100

33

Reserved

Default

CK_PWRGD 14

SLG8SP513

SLG8SP513VTR ,ICS9LPRS365BKLFT

+3V

5/5 modify
ICS9LRS3165BKLFT
(ALPRS365000)

Pin 11

Pin 12

Pin 13

Pin 14

RTM875T-606
(AL000875000)

PCI2/TME

PCI2/TME
internal PD

PCI-3

PCI-3/SRC5_EN
internal PD

PCI-4/27M_SEL

PCI-4/27M_SEL
internal PD

PCIF-5/ITP_EN

PCIF-5/ITP_EN
internal PD

PULL HIGH

+3V

PULL DOWN

NO OVERCLOCKING (default)

NORMAL RUN

PIN37/38 IS SRC5

PIN37/38 IS
PCI_STOP/CPU_STOP

PIN 17/18 IS 27MHz

PIN 17/18
IS SRC/DOT

PIN 46/47 IS CPUITP

+3V

R329

10K_4

R331

*10K_4

R336

EV@10K_4

R332

IV@10K_4

R342

*10K_4

R343

10K_4

PCLK_DEBUG_R

PCLK_591_R
HIGH 27MHz
LOW SRC

From GMCH

PCLK_ICH_R

(default)

To NB
(default)

PIN 46/47 IS SRC8

(default)

3 CPU_BSEL0
3 CPU_BSEL1
3 CPU_BSEL2

RN15
CLK_DREFCLK_R
CLK_DREFCLK#_R
RN14
CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R

3
1

4
2

IV@0_4P2R

CLK_DREFCLK 6
CLK_DREFCLK# 6

3
1

4
2

IV@0_4P2R

CLK_DREFSSCLK 6
CLK_DREFSSCLK# 6

RN10
1
CLK_DREFCLK_R
3
CLK_DREFCLK#_R

2
4

EV@0_4P2R

CLK_PCIE_VGA 18
CLK_PCIE_VGA# 18

From Deisceret

R347

0_4

MCH_BSEL0 6

R267

0_4

MCH_BSEL1 6

R315

0_4

RN9
CLK_DREFSSCLK_R 1
CLK_DREFSSCLK#_R 3

&ORFN*HQ,&

MCH_BSEL2 6

R258
4.7K_4

Q13

14,16,28 PDAT_SMB

<MAIN>:ICS9LRS3165BKLFT QCI:ALPRS365000
<SECOND>:SLG8SP513VTR QCI:AL8SP513000
<SECOND>:RTM875N-606-VD-GRT QCI:AL000875000
Q12

5/22 modify

+3V

SMBDT1

14,16,28 PCLK_SMB

2N7002E

2N7002E

REV:B 6/12

REV:B 6/11

R259
4.7K_4

352-(&7=4
4XDQWD&RPSXWHU,QF

SMBCK1

Size

Document Number

Rev
1A

CLOCK GENERATOR
Date:

27M_NONSS 19
*EV@33_4P2R

5/18 Modify
+3V

2
4

Monday, July 12, 2010

Sheet 2
1

of

43

H_A#[3..16]

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

H5
F21
E1

H_D#[0..15]

H_D#[0..15]

H_BREQ# 5
H_IERR#

R245

56_4

H4

+1.05V
H_INIT# 12
H_LOCK# 5

C1
F3
F4
G3
G2

H_CPURST# 5
H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5

G6
E4

H_HIT# 5
H_HITM# 5

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
SYS_RST#

D21
A24
B25

H_PROCHOT#_D
H_THERMDA
H_THERMDC

C7

PM_THRMTRIP#

5
5
5

H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#[16..31]

+1.05V

THERMTRIP#

H CLK
BCLK[0]
BCLK[1]

A22
A21

5
5
5

H_DSTBN#1
H_DSTBP#1
H_DINV#1

2
2
2

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_GTLREF AD26
CPU_TEST1 C23
CPU_TEST2 D25
CPU_TEST3 C24
CPU_TEST4 AF26
AF1
CPU_TEST5
A26
CPU_TEST6
C3
CPU_TEST7
B22
B23
C21

T108
T112
T125
T90
T87
T126
T127

R312
2K/F_4

CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

H_D#[32..47]

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

MISC

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

03
D

H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5
H_D#[48..63]

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

Connect it to CPU DBR# is for ITP debug port

or CPU interposer (like ICE) to reset the system

R311
1K/F_4

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

H_D#[16..31]

T56
T86
T88
T55
T89

SYS_RST# 14

H_D#[32..47]

U17B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_DEFER# 5
H_DRDY# 5
H_DBSY# 5

F1
D20
B3

DATA GRP 2

CONTROL

PROCHOT#
THERMDA
THERMDC

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

H_ADS# 5
H_BNR# 5
H_BPRI# 5

DATA GRP 1

D5
C6
B4
A3

H_STPCLK#
H_INTR
H_NMI
H_SMI#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H1
E2
G5

THERMAL

ICH

A20M#
FERR#
IGNNE#

LOCK#

HIT#
HITM#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A6
A5
C4

12 H_A20M#
12 H_FERR#
12 H_IGNNE#

IERR#
INIT#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

ADDR GROUP_1

H_ADSTB#1

BR0#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

DEFER#
DRDY#
DBSY#

XDP/ITP SIGNALS

H_A#[17..35]

ADS#
BNR#
BPRI#

DATA GRP 3

K3
H2
K2
J3
L1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

12
12
12
12

DATA GRP 0

5 H_ADSTB#0
5 H_REQ#[0..4]

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

ADDR GROUP_0

U17A
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_D#[48..63]

Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
C

H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5
R344
R328
R257
R254

27.4/F_6
54.9/F_4
27.4/F_6
54.9/F_4

E5
B5
D24
D6
D7
AE6

ICH_DPRSTP# 6,12,39
H_DPSLP# 12
H_DPWR# 5
H_PWRGD 12
H_CPUSLP# 5
PSI#
39

Penryn

RESERVED

Layout note:
H_GTLREF: Zo=55 ohm
L<0.5", 2/3*VCCP+-2%

Penryn

Thermal Trip

CPU Thermal monitor

+1.05V

XDP PU/PD

+3V

+3V
SYS_RST#

R400
2

6,14,39 DELAY_VR_PWRGOOD

R391

*1K_4

Q18
200_6

+1.05V

DMN601K-7
VCC_TH
1

+1.05V

56_4
PM_THRMTRIP#

Q17
3 MMBT3904

U21
SYS_SHDN#

35 2ND_MBCLK

35 2ND_MBDATA

No use Thermal trip CPU side still PU 56ohm.

Use Thermal trip can share PU at SB side
+1.05V

No use PROCHOT CPU side still PU 56ohm.

Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
side

R273

4
+3V

R401
R395

14 THERM_ALERT#

*10K_4
*0_4

R274

*0_4

SCLK

VCC

SDA

DXP

ALERT#

DXN

OVERT#

GND

+3V

54.9/F_4

XDP_TMS

R264

54.9/F_4

XDP_BPM#5

R310

54.9/F_4

C621

XDP_TCK

R265

54.9/F_4

2200p_4

XDP_TRST#

R266

54.9/F_4

H_THERMDC

G780P81U(MSOP-8)

XDP_DBRESET# and XDP_TDO

reserve for XDP

4/20 Modify
H_PROCHOT# 39

GMT

AL000780000

Use 2200p

NS

AL095245000

Use 2200p

WINDBOND

AL83L771K01

Use 2200p

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

CPU Host Bus

Date:

10K_4

27 THER_OVERT#

&38
5

*54.9/F_4

R260

$''5(66+
R394

56_4
H_PROCHOT#_D

R261

XDP_TDI
H_THERMDA

37,44

Processor hot

XDP_TDO
0.1U/10V_4
2

R398

6,12 PM_THRMTRIP#

ZR6 hang up issue

C624

Monday, July 12, 2010

Sheet 3
1

of

43

VCC_CORE

U17D

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

C470

C445

C447

C444

C471

C564

C563

C424

*10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

C562

C590

C589

C588

C468

C466

C429

C465

10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

C442

C441

C472

C433

C419

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

Layout Note:
Place these parts
reference to Intel demo
board.

C446

C443

C420

*10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

C425

C421

C422

C423

C567

C566

*10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

C565

C591

C587

C586

C469

C467

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

10U/6.3V_8

*10U/6.3V_8

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

+ C491
*330U/2V_7343

+ C580
330U/2V_7343

+ C430
330U/2V_7343

04

VCC:38A (Low power type)

VCC:47A (Standard type)

Layout Note:
Inside CPU center cavity in 2 rows

VCCP : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)
+1.05V

C428

C431

C438

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

+ C622
330U/2V_7343

C426

C432

C440

*0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA:130mA

+1.5V

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

39
39
39
39
39
39
39

C599

C598

0.01U/25V_4

10U/6.3V_8

R308

100/F_6

AF7

VCC_CORE
VCCSENSE 39

AE7

VSSSENSE 39
R309

Penryn
+ C623

100/F_6

*330U/2V_7343

Layout Note:
Z0=27.4,PU/PD L<1"
A

Penryn

352-(&7=4
4XDQWD&RPSXWHU,QF

Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
stuff 330U*2, NC330U*2

&38
5

VCC_CORE
U17C

Size
Date:

Document Number

Rev
1A

CPU Power
2

Sheet

Monday, July 12, 2010

1

of

43

*0&+&$17,*$

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

Intel Cantiga (G)M

AJSLB940T04

Intel Cantiga (P)M

AJSLB970T06

Intel Cantiga (G)L A1

AJSLGGM0T04

+1.05V

0.3125*VCCP
WIDE(10):SPACING(20) ,
L<0.5"

R411
221/F_4

H_SWING
R410

C642

100/F_4

0.1U/10V_4

H_RCOMP

R407

Layout Note:
WIDE(10):SPACING(20) ,
L<0.5"

24.9/F_4

H_SWING
H_RCOMP

+1.05V

3
3

R414

2/3*VCCP
WIDE(10):SPACING(20),
L<0.5"

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3

C12
E11

H_CPURST#
H_CPUSLP#

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

R415

C649

2K/F_4

*0.1U/10V_4

A11
B11

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_SWING
H_RCOMP

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_CPURST#
H_CPUSLP#

H_RS#_0
H_RS#_1
H_RS#_2

1K/F_4
H_AVREF

H_A#[3..35]

U20A

H_D#[0..63]

QCI P/N

HOST

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

05

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_ADS#
3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR#
3
H_BPRI# 3
H_BREQ# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT#
3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

H_DINV#[3..0]

3
B

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_REQ#[0..4]

H_RS#[0..2]

H_AVREF
H_DVREF

CANTIGA_PM

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

GMCH HOST
Date:
5

Monday, July 12, 2010

Sheet 5
1

of

43

IV@
EV@

06

+3V_S5

DDR3

0 = DMI X2
1 = DMI X4(Default)
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)

CFG7

ME TLS Confidentiality

0 = AMT Firmware will use TLS cipher suite

with no confidentiality
1 = AMT Firmware will use TLS cipher suite
with confidentiality(Default)

CFG8

Reserved

CFG9

PCIE Graphics Lane Reversal

0 = Reverse Lanes
1 = Normal operation(Default)

CFG10

PCIE Loopback enable

0 = Enabled
1 = Disabled (Default)

CFG11

Reserved

T24
B31
M1
AY21
B2
BG23
BF23
BH18
BF18

ALLZ

0 = ALLZ mode enable

1 = disable(Default)

CFG13

XOR

0 = XOR mode enable

1 = disable(Default)

CFG[15:14]

Reserved

CFG16

FSB Dynamic ODT

CFG[18:17]

Reserved

CFG19

DMI Lane Reversal

0 = Normal (Default)
1 = Lanes Reversed

CFG20

Digital Display Port

(SDVO/DP/iHDMI)
Concurrent with PCIE

0 = Only Digital Display port (SDVO/DP/iHDMI)

or PCIE is operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and
PCIE are operating simultaneously via PEG
port

CFG12

DDPC_CTRLDATA

AL34

T43

AK34

T39

AM35

T44

2
2
2

0 = Digital display(HDMI/DP) device

absent(Default)
1 = Digital display(HDMI/DP) device present

AN35

T47

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
T31
T35

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25

T29
T32
T30

Strap pin

T27
T33

+3V
*4.02K/F_4
*4.02K/F_4

MCH_CFG_19
MCH_CFG_20

*2.21K/F_4
*2.21K/F_4
*2.21K/F_4

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7

R183

*2.21K/F_4

MCH_CFG_9

R416
R208
R213
R196

*2.21K/F_4
*2.21K/F_4
*2.21K/F_4
*2.21K/F_4

MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16

TPM Disable

14 PM_SYNC#
3,12,39 ICH_DPRSTP#
16 PM_EXTTS#0
17 PM_EXTTS#1
3,14,39 DELAY_VR_PWRGOOD
13 PLT_RST#
3,12 PM_THRMTRIP#
14,39 PM_DPRSLPVR

R239
R210

100/F_4
*0_4

NB Thermal trip pin

No use Thermal trip NB side can
NC.(NB has ODT)

5/4 modify it for park reversal PCIE x16

+3V
SDVO_CTRLDATA
SDVO_CTRLCLK
DDPC_DDCDATA
DDPC_CTRLCLK
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1

ME_JTAG_TDO

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

ME_JTAG_TMS

PEG_CLK
PEG_CLK#

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
CANTIGA_PM

AP24
AT21
AV24
AU20

16
16
17
17

U10
4

AR24
AR21
AU24
AV20

HWPG_1.5V 35,40

M_CLK#0
M_CLK#1
M_CLK#2
M_CLK#3

BC28
AY28
AY36
BB36
BA17
AY16
AV16
AR13
BD17
AY17
BF15
AY13
BG22
BH21

M_RCOMP
M_RCOMP#

BF28
BH28

SM_RCOMP_VOH
SM_RCOMP_VOL

AV42
AR36
BF17
BC36

SM_VREF
SM_PWROK
SM_REXT R247

B38
A38
E41
F41

CLK_DREFCLK
CLK_DREFCLK#
CLK_DREFSSCLK
CLK_DREFSSCLK#

F43
E43

CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#

AE41
AE37
AE47
AH39

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AE40
AE38
AE48
AH40

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AE35
AE43
AE46
AH42

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AD35
AE44
AF46
AH43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

16
16
17
17

M_CS#0
M_CS#1
M_CS#2
M_CS#3

16
16
17
17

M_ODT0
M_ODT1
M_ODT2
M_ODT3

16
16
17
17

R252

*short0402

SUSC#

14,35

*0_4

SUSB#

14,35

SM_PWROK
R251
10K_4

+1.5V_SUS
M_RCOMP R340
M_RCOMP# R339

SM_VREF=0.5*VCC_SM
SM_PWROK only for
DDR3.(DDR2 PD only)
SM_DRAMRST# only
for DDR3.(DDR2:NC)

80.6/F_4
80.6/F_4

+1.5V_SUS
SM_VREF

R241
R242

10K/F_4
10K/F_4

499/F_4
DDR3_DRAMRST# 16,17
CLK_DREFCLK 2
CLK_DREFCLK# 2
CLK_DREFSSCLK 2
CLK_DREFSSCLK# 2

SM_VREF.Default use voltage divider for

poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is
1K,But Check list PU/PD is 10K.

CLK_PCIE_3GPLL 2
CLK_PCIE_3GPLL# 2

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

INTEL FAE Suggest PD for Ext graphics

DMI_TXP[3:0] 13

CLK_DREFCLK#
CLK_DREFCLK
CLK_DREFSSCLK#
CLK_DREFSSCLK

DMI_RXN[3:0] 13

R184
R182
R190
R187

EV@0_4
EV@0_4
EV@0_4
EV@0_4

DMI_RXP[3:0] 13
+1.5V_SUS
1K/F_4

SM_RCOMP_VOH

B33
B32
G33
F33
E33

C560

C577

2.2U/6.3V_6

R335
0.01U/25V_4
3.01K/F_4

R327

SM_RCOMP_VOL
B

C559

C576

2.2U/6.3V_6

0.01U/25V_4 1K/F_4

R326

C34
+1.05V

NB Thermaltrip
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#

AH37
AH36
AN36
AJ35
AH34

R227

CL_CLK0 14
CL_DATA0 14
MPWROK 14,35
CL_RST#0 14

MCH_CLVREF_R

1K/F_4

Check list note : CL_VREF=0.35V

N28
M28
G36
E36
K36
H36

DDPC_CTRLCLK
DDPC_DDCDATA

B12

TSATN#

C394

R228

0.1U/10V_4

511/F_4

SDVO_CTRLCLK 26
SDVO_CTRLDATA 26
CLK_MCH_OE# 2
MCH_ICH_SYNC# 14

CLK_MCH_OE#

R169

56_4

DDPC_CTRL for HDMI port C

SDVO_CTRL for HDMI port B

+1.05V

Modify 4/19
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

HDA_BIT_CLK_HDMI
HDA_RST#_HDMI
HDA_SDIN_HDMI
HDA_SDOUT_HDMI
HDA_SYNC_HDMI

HDA_BIT_CLK_HDMI 12
HDA_RST#_HDMI 12
HDA_SDIN_HDMI 12
HDA_SDOUT_HDMI 12
HDA_SYNC_HDMI 12

If HDMI not support

HDA --> NC
VCC_HDA-->GND
Differential signal-->NC

Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V

<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56- pull-up resistor to VCCP.
A

<Pin out check issue>

Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

GMCH DMI
Date:

R253

R250
12.1K_4

16
16
17
17

M_CKE0
M_CKE1
M_CKE2
M_CKE3

NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
be used on the platform.

*0&+&$17,*$

TC7SH08FU
1

M_CLK0
M_CLK1
M_CLK2
M_CLK3

DMI_TXN[3:0] 13
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

NC

PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
order.

RST_IN#_MCH
THRMTRIP#_R

R29
B7
N33
P32
AT40
AT11
T20
R32

ME_JTAG_TDI

PM

R417
R214
R197

[email protected]/F_4
[email protected]/F_4
*2.21K/F_4
*2.21K/F_4
10K_4
10K_4
10K_4

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

ME_JTAG_TCK

CFG

MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

T28

R185
R192
R205
R206
R198
R204
R200

RSVD20

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

0 = No SDVO/HDMI Device Present(Default)

1 = SDVO/HDMI Device present

Digital Display Present

R203
R207

RSVD17

0 = Dynamic ODT disable

1 = Dynamic ODT Enable(Default)

SDVO Present

RSVD15

ME JTAG

SDVO_CTRLDATA

RSVD14

RSVD

iTPM Host Interface

DDR CLK/ CONTROL/COMPENSATION

DMI X2 Select

CLK

CFG5

DMI

Reserved

000= FSB 1066MHz

010 = FSB 800MHz
011 = FSB 667MHz

GRAPHICS VID

CFG[4:3]

CFG6

FSB Frequency Select

REV:B
Add 6/11

R571
*0_4

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

ME

CFG[2:0]

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12

Configuration

MISC

U20B

Strap description

HDA

Pin Name

Strap table

Monday, July 12, 2010

1

Sheet 6

of

43

IV@

07

25 L_BKLT_CTRL
25 INT_LVDS_BLON
+3V

R201

IV@10K_4

L_CTRL_CLK

R199

IV@10K_4

L_CTRL_DATA

25 INT_LVDS_EDIDCLK
25 INT_LVDS_EDIDDATA
25 INT_LVDS_DIGON

R188

[email protected]/F_4

M29
C44
B43
E37
E38
C41
C40
B37
A37

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

A41
H38
G37
J37

SP@

R189
R195
R194

SP@75_4
SP@75_4
SP@75_4

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

B42
G38
F37
K37

TV_A/B/C
For IV: 75ohm
For EV:0ohm

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

INT_TV_COMP F25
H25
INT_TV_Y/G
K25
INT_TV_C/R

TV_RTN

C31
E32

TV_DCONSEL_0
TV_DCONSEL_1

25 INT_CRT_GRN

25 INT_CRT_DDCCLK
25 INT_CRT_DDCDAT
25 INT_HSYNC
25

INT_VSYNC

CRT_BLUE

INT_CRT_GRN G28

CRT_GREEN

INT_CRT_RED J28

CRT_RED

G29

R426

[email protected]_4

R425

[email protected]_4

HSYNC_G
CRTIREF
VSYNC_G

CRT_IRTN

H32
J32
J29
E29
L29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

HSYNC/VSYNC serial R place close to NB

Discrete STUFFED.
HSYNC_G
A

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

VGA

6/14 Modify
REV:B

25 INT_CRT_RED

INT_CRT_BLU E28

TV

TVA_DAC
TVB_DAC
TVC_DAC

H24

25 INT_CRT_BLU

PEG_COMPI
PEG_COMPO

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

H48
D45
F40
B40

INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+

25 INT_TXLOUT0+
25 INT_TXLOUT1+
25 INT_TXLOUT2+

M33
K33
J33

H47
E46
G40
A40

INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2-

25 INT_TXLOUT025 INT_TXLOUT125 INT_TXLOUT2-

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

LVDS

INT_TXLCLKOUTINT_TXLCLKOUT+

25 INT_TXLCLKOUT25 INT_TXLCLKOUT+

,9 (9'LV(QDEOHVHWWLQJ
<5/31>Montevina_Schematics_Checklist_Rev0_8
a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
design guide Rev0.7 show NC.What is correct.
b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
CRT_HSYNC, CRT_VSYNCThese signals should be connected to
GND. But design guide Rev0.7 show NC, Intel suggest follow
Design guide.

+1.05V

L32
G32
M32

GRAPHICS

SP@

L<0.5" , If PCIE not support

still connect to +VCC_PEG

U20C

PCI-EXPRESS

EV@

,9 (9'LV(QDEOHVHWWLQJ
If LVDS no use,all signal can NC

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

EXP_A_COMPX

R209

49.9/F_4

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

<check list>
For EV@
CRT R/G/B 0ohm to GND
CRTIREF 0ohm to GND

PEG_RXN[15:0] 18

<check list>
For IV@
CRT R/G/B 150ohm to GND
CRTIREF 1Kohm to GND

Can support reversal routing.If CFG9=1, PCI Express

is normal operation. If CFG9=0, then PEG_TXP0
becomes PEG_TXP15, PEG_TXP1 becomes
PEG_TXP14, PEG_TXP2 becomes PEG_TXP13, etc.
similarly for PEG_RXP[15:0] and PEG_RXN[15:0]

CRTIREF
For IV: 1Kohm
For EV:0ohm
R186

C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15

C309
C323
C629
C332
C330
C626
C336
C339
C351
C353
C356
C369
C376
C377
C391
C384

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15

C311
C318
C632
C334
C324
C627
C338
C344
C346
C355
C363
C365
C371
C382
C396
C387

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

CRTIREF

SP@

PEG_RXP[15:0] 18,26

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

SP@1K/F_4

CRT_R/G/B
For IV: 150ohm
For EV:0ohm
R179

SP@150_4

INT_CRT_BLU

R178

SP@150_4

INT_CRT_GRN

R180

SP@150_4

INT_CRT_RED

PEG_TXN[15:0] 18,26

PEG_TXP[15:0] 18,26

CANTIGA_PM

CRTIREF pull down

for IV cantiga 1k ohm/F

VSYNC_G
R413
EV@0_4

352-(&7=4
4XDQWD&RPSXWHU,QF

R412
EV@0_4

Size

Document Number

Rev
1A

GMCH VGA
Date:
5

Sheet 7

Monday, July 12, 2010

1

of

43

08

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BB20
BD20
AY20

M_A_RAS# 16
M_A_CAS# 16
M_A_WE# 16

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_B_DQ[63:0]

U20E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_A_BS0 16
M_A_BS1 16
M_A_BS2 16

M_A_DM[7:0] 16

M_A_DQS[7:0] 16

M_A_DQS#[7:0] 16

M_A_A[14:0] 16

CANTIGA_PM

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#

SA_RAS#
SA_CAS#
SA_WE#

BD21
BG18
AT25

MEMORY

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

SYSTEM

17

U20D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR

M_A_DQ[63:0]

DDR

16

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BC16
BB17
BB33

M_B_BS0 17
M_B_BS1 17
M_B_BS2 17

AU17
BG16
BF14

M_B_RAS# 17
M_B_CAS# 17
M_B_WE# 17

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_DM[7:0] 17

M_B_DQS[7:0] 17

M_B_DQS#[7:0] 17

M_B_A[14:0] 17

CANTIGA_PM

352-(&7=4
4XDQWD&RPSXWHU,QF

*0&+&$17,*$
5

Size

Document Number

Rev
1A

GMCH DDRII
Date:
4

Monday, July 12, 2010

Sheet
1

of

43

09

IV@
SP@
Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10

Intel check list(Rev 0.8)

270U*1 near to power(+V1.05M).
270U*2 near to NB
Intel CRB(Rev 0.7)
270U*3 near to power(+V1.05M).
270U*1 near to NB
ESR=12m ohm

Intel check list(Rev 0.8)

No description for VCC_SM bulk CAP
Intel CRB(Rev 0.7)
330U*1 Reserve near to power
330U*1 near to NB

*07'3a:
*67'3a:
307'3:
D

+1.05V_AXG

9&&B609
''50
P$B6P$B6
''50P$B6
''50P$B6

BA36
BB24
BD16
BB21
AW16
AW13
AT13

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

Voltage regulator is shared between

the Graphics Core Rail,
VCCA_HPLL,VCCA_MPLL,VCCA_PEG_PLLVCCD_PEG_PLL,
VCCA_SM_CK, VCCA_DPLLA, VCCA_DPLLB, VCCD_HPLL,
VCCA_SM, VCC_AXF

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

+1.05V_AXG

IV@

R235
R230

IV@10/F_4 AJ14
IV@10/F_4 AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

+1.05V

U20F

C375

C379

C359

0.1U/10V_4

0.22U/6.3V_4 0.22U/6.3V_4

C381
22U/6.3V_8

C631
330U/2V_7343

Place close to
the GMCH

+1.05V

IV@

+1.05V_AXG

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

+1.05V_AXG

R384

IV@0_8

R381

IV@0_8

R383

IV@0_8

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

T32

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

+1.05V

,9 (9'LV(QDEOHVHWWLQJ
Design guide(Table 72)
For INT VGA diasble.VCC_AXG power can connect to GND

SP@
+ C602
IV@330U/2V_7343

+ C601
IV@330U/2V_7343

C399

C392

C367

[email protected]/6.3V_4

SP@1U/10V_6

IV@10U/6.3V_8 IV@22U/6.3V_8 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4

Place close to the GMCH

Intel check list(Rev 0.8)
220U*2 near to NB(ESR=15m ohm)
Intel CRB(Rev 0.7)
270U*4 near to power(+V1.05S).
330U*2 near to NB

VCC GFX

9
*UDSKLFVFRUH
9&&B$;*
9&&B$;*B1&7)
P$

VCC GFX NCTF

+1.05V_AXG

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

63#,96XWIIXI
(9VWXIIRKP

C380

C393

C410

C370

VCC NCTF

330U/2V_7343

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC CORE

0.1U/10V_4

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

POWER

22U/6.3V_8

C572

Cavity Capacitors

1.8V
Internal connect to power

VCC SM LF

C414

VCC SM

22U/6.3V_8

C558

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

POWER

U20G

+1.5V_SUS

C561

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

C403

C417

C416

C404

C415

C413

0.1U/10V_4

0.1U/10V_4

0.22U/6.3V_4

0.22U/6.3V_4

0.47U/6.3V_4

1U/6.3V_4

1U/6.3V_4

9&&
9&&B1&7)
P$B(9
P$B,9
0((QJLQH
P$
7RWDO0D[ P$

CANTIGA_PM

C418

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

CANTIGA_PM

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest

352-(&7=4
4XDQWD&RPSXWHU,QF

*0&+&$17,*$

Size

Document Number

Rev
1A

GMCH VCC,NCTF
Date:
4

Monday, July 12, 2010

1

Sheet

of

43

Power consumption reference to Intel

Cantiga chipset EDS Volume1. Section 10
+3V_CRT_TV_DAC

R171

EV@

R429

63#,17XVH8
(;7XVHRKP
L51

+1.05V

IV@10U/6.3V_8

+3V_A_DAC_BG

IV@BLM18PG181SN1D_6
C651

C647

([WHUQDO*UDSKLFV
*0&+,QWHJUDWHG*UDSKLFV'LVDEOH

9
P$

C653
IV@10U/6.3V_8

[email protected]/10V_4 [email protected]/25V_4

IV@10uh_8

1.05V
FSB-1067
852mA

U20H
+ C644

C333

F47

+1.05VM_DPLLB

L48

C635

+1.05VM_HPLL

AD1

[email protected]/10V_4

+1.05VM_MPLL

AE1

9
P$

*0/short_6

1.5V
414uA

J47

+VCCA_PEG_BG

AD48

SP@1000P/50V_4

0.1U/10V_4

R388

*0/short_8
C610

3.9 nH, 0.2 nH, 1A

, DCR_max=32 m

BLM18PG181SN1D_6

1210 0.1uH, 20%, 1A,

DCR_max=0.078

+1.05V

R233

1.05V
DDR2-800
720mA
*0/short_6

0.1U/10V_4

VCCA_PEG_PLL
+1.25V for Teenah use(100mA)

C409
R393

AA48

+1.05VM_PEGPLL

+1.05VM_A_SM

C412

C402

0.5/F_6
22U/6.3V_8

C615

4.7U/6.3V_6

1U/6.3V_4

C609

22U/6.3V_8

0.1U/10V_4

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

L53

+3V

3.3V
79mA

*0/short_6

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

+1.05VM_A_SM_CK
C408

C406

*2.2U/6.3V_6

C405

22U/6.3V_8

0.1U/10V_4

,9 (9'LV(QDEOHVHWWLQJ

IV@BKP1608HS181-T_6

63#,17XVH8
(;7XVHRKP

C666

C650

C648

IV@10U/6.3V_8

[email protected]/10V_4

[email protected]/25V_4

C663

C654

R173

4/21 add

1.5V
50mA

63#,17XVH8
(;7XVHRKP

IV@0_6

B24
A24

A32

+VCC_HDA

VCCA_TV_DAC_1
VCCA_TV_DAC_2

VCC_HDA

FB 180@100 MHz, 25% 1.5A

DCR_max=90 m
L32

1.05V
157.2mA

C327

C335

0.1U/10V_4

0.01U/25V_4

+1.05VM_MCH_PLL2
C606

+1.05VM_PEGPLL

AF1
AA47

VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL

0.1U/10V_4
M38
L37

1.5V
0.5mA

VCCD_LVDS_1
VCCD_LVDS_2

DMI

*0/short_6

*0/short_6

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

CANTIGA_PM

GND

VCC_TX_LVDS

GND

VCCA_LVDS

GND

VCCA_TVDAC

GND

VCCD_QDAC

GND

VCCA_DAC_BG

GND

VCC_AXG

GND

VCC_AXG_NCTF

GND

Check list : 0.1UH

CRB : 0 ohm
1210 0.1 ?H, 20% 1A
DCR max = 78 m

1.05V
321.35mA

L52
C646

C652

1U/6.3V_4

*10U/10V_8

*0/short_8

1.8V
DDR2-800
124mA
L44

+1.05V

0805 1UH , Rdc = 0.14 - 0.26.

Max rated current = 220 mA

1uh_8

+1.5VSUS_SMCK_RC
4/15 Modify

R341

+1.5V_SUS

3.3V
105.3mA

C639

C570

DDR3
DDR2

+1.5V_SUS
+1.8V_SUS

10U/6.3V_8

0805 100 nH, DCR=160 m

1.8V
118.8mA
L50

63#,17XVHSI
(;7XVHRKP

BF21
BH20
BG20
BF20

GND

VCCD_LVDS

[email protected]_6

+1.8V

C643

SP@1000P/50V_4

IV@22U/6.3V_8

+3V
R176

10_4

+1.05V_SD

D9

2 CH751

+1.05V

C320

VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF

1.5V
48.363mA for CRT
5mA for TV

L28

+1.5V_QDAC
R396

LVDS

R175

ESR= 12m ohm

1/F_4

B22
B21
A21

GND

VCCA_CRT_DAC

330U/2V_7343

C575

VCC_TX_LVDS

D TV/CRT

M25

VCCD_QDAC share to TV and CRT

VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V

+1.5V

4.7U/6.3V_6

,9 (9'LV(QDEOHVHWWLQJ

[email protected]/10V_4

+1.05V

4.7U/6.3V_6

0.1U/10V_4

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

+1.5V_TVDAC

C319

1.5V
35mA

C360

4/15 Modify
+1.5VSUS_VCC_SM_CK

*IV@10U/6.3V_8 *IV@10U/6.3V_8
+3V_CRT_TV_DAC

CRB no 10U
Check list need min 10U~100U for VCCA_TV_DAC

0.47U/6.3V_4 2.2U/6.3V_6

VCCSYNC_CRT

+ C619

C361

+1.8VSUS_TXLVDS

CRB : 0 ohm
Check list : 2.2nH

FB 180@100 MHz, 25% 1.5A

DCR_max=90 m

C362

ESR = 60 m

TV

R231

+1.05V

+1.05V
C374

POWER

1.05V
DDR2-800
26mA

3.3V
24.15mA for VCCA_TVA_DAC
39.48mA for VCCA_TVB_DAC
24.15mA for VCCA_TVC_DAC
Total 87.78mA

+1.5V

VCCA_PEG_BG

1.05V
50mA

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
+1.05VM_AXF

AXF

+1.5V

1.05V
139.2mA

+1.05VM_MPLL_RC

VSSA_LVDS

C611

4.7U/6.3V_6

L48

VCCA_LVDS

HV

C616

VCCA_MPLL

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

A PEG

R397

J48
C637

SM CK

1.05V
24mA

VCCA_HPLL

+1.8VSUS_TXLVDS

PEG

ESR=15 m

VCCA_DPLLB

A LVDS

IV@220U/6.3V_7343

VCCA_DPLLA

VTT

+1.05VM_DPLLA

IV@10uh_8
+ C638

+1.05V

USE same GND plane

VCCA_DAC_BG
VSSA_DAC_BG

HDA

+1.05V

A25
B25

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

CRT

VCCA_DPLLA/B always keep to +1.05V

(If no use IV dynamic core power)

1210 10UH, 10%

0.45A DCR_max = 0.39
L49

B27
A26

9
P$

PLL

[email protected]/10V_4
EV@220U/6.3V_7343
ESR=15 m

A SM

9
P$IRU'3//B$%

A CK

5/12 UMA no stuff

10

C312

63#,17XVH8
(;7XVHRKP

,9 (9'LV(QDEOHVHWWLQJ

1210 10UH, 10%

0.45A DCR_max = 0.39

C328

[email protected]/10V_4 [email protected]/25V_4

Modify 6/18
REV:B

IV@

+3V_VCCA_CRT_DAC

IV@BLM18PG181SN1D_6
C322

SP@

If CRT have Flicker issue

STUFF 5.6 ohm
,9 (9'LV(QDEOHVHWWLQJ

VTTLF1
VTTLF2
VTTLF3

K47
0.1U/10V_4
C35
B35
A35

1.05V
1782mA

V48
U48
V47
U47
U46

+1.05V
B

C604

1.05V
456mA

AH48
AF48
AH47
AG47

4.7U/6.3V_6

C603

C605

+ C625
EV@220U/6.3V_7343

22U/6.3V_8

5/12 UMA no stuff

0.1U/10V_4
A8
L1
AB2
C617

C634

C321

1.05V
Internal connect to power

0.47U/6.3V_4 0.47U/6.3V_4 0.47U/6.3V_4

BKP1608HS181-T_6

C308
C345

C347

0.1U/10V_4

0.01U/25V_4

10U/6.3V_8

CRB no 10U
Check list need min 10U~100U
for VCCA_QDAC

FB 220 @100 MHz, 25%, 2A

A

L47

+1.05V

+1.05VM_PEGPLL_RC

Power Net Name

1.05V

VCCA_PEG_BG

1.5V

VCCA_DPLLA

1.05V

VCCA_DPLLB

1.05V

VCCA_SM_#

1.05V

VCCA_HPLL

1.05V

VCCA_MPLL

1.05V

VCCA_SM_CK_#

1.05V

C348

VCCA_PEG_PLL

1.05V

SP@1U/6.3V_4

VCC_AXF_#

1.05V

VCCD_HPLL

1.05V

VCCD_PEG_PLL

1.05V

1.05V
50mA

BKP1608HS181-T_6

R392

C614

C613

0.1U/10V_4

0.1U/10V_4

,9 (9'LV(QDEOHVHWWLQJ

1/F_4
+1.8V

C618

R202

1.8V
60.31mA

10U/6.3V_8

ESR=60m ohm

IV@0_6

Cantiga(V)

VCC_AXG_#
VCC_AXG_NCTF_#

+1.8VSUS_DLVDS

63#,17XVH8
(;7XVHRKP

*0&+&$17,*$

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

GMCH POWER
Date:
2

Monday, July 12, 2010

1

Sheet

10

of

43

VSS

BG21
L12
AW 21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW 20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW 17
AT17
R17
M17
H17
C17

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W 34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23

BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W 15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS

VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

CANTIGA_PM

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355

VSS NCTF

11

U20J

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

VSS SCB

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

NC

U20I

AU48
AR48
AL48
BB47
AW 47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW 37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_6
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW 2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29
AJ6
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47

352-(&7=4
4XDQWD&RPSXWHU,QF

CANTIGA_PM

*0&+&$17,*$

Size
Date:

Document Number

Rev
1A

GMCH VSS
4

Sheet

Monday, July 12, 2010

1

11

of

43

C594

12

15P/50V_4

1M/F_6

A25
F20
C22

R364
R355

330K/F_4
330K/F_4

B22
A22

ICH_INTVRMEN
LAN100_SLP

E25

,QWHUQDO950HQDEOHGIRU
9FF6XVB9FF6XVB
9FF&/B9FF/$1BDQG
9FF&/B
24.9 Ohm pull up to 1.5V
for GLAN_COMPI/O is
required, no matter intel
LAN is used or not.

C13
F14
G13
D14
D13
D12
E13

+3V_S5

+1.5V

R378

10K_4 ICH_GPIO56

R382

24.9/F_4

Internal pull-down
resistors that are
always enabled

B10
B28
B27

HDA_BIT_CLK_R
HDA_SYNC_R

AF6
AH4

HDA_RST#_R

AE7
AF4
AG4
AH3
AE5

29 ACZ_SDIN0
HDA_SDIN2
HDA_SDOUT_R

AG7
AE8

T23
T24
27

ODD (SATA)

AG5

AG8

SATA_LED#

27 SATA_RXN1
27 SATA_RXP1
27 SATA_TXN1
27 SATA_TXP1

C659
C658

0.01u/16V_4
0.01u/16V_4

AJ16
AH16
AF17
AG17

SATA_TXN1_C
SATA_TXP1_C

AH13
AJ13
AG14
AF14

RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
LAN100_SLP

FW H0/LAD0
FW H1/LAD1
FW H2/LAD2
FW H3/LAD3
FW H4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23

GLAN_CLK

A20GATE
A20M#

LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#/GPIO56

DPRSTP#
DPSLP#
FERR#
CPUPW RGD
IGNNE#
INIT#
INTR
RCIN#

GLAN_COMPI
GLAN_COMPO

NMI
SMI#

HDA_BIT_CLK
HDA_SYNC

STPCLK#
HDA_RST#
THRMTRIP#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT

TP8
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

K5
K4
L6
K2

LAD0
LAD1
LAD2
LAD3

K3

HDA_SDOUT_R

R471

IV@33_4

R478

33_4

HDA_SDOUT_HDMI

ACZ_SDOUT_AUDIO

HDA_BIT_CLK_R
29

LDRQ0/1# : Internal PU

T38
T122

R211

8.2K_4

N7
AJ27

R443
*56_4

+3V
GATEA20
H_A20M#

AJSLB8Q0T03

Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)

R406
*56_4

35
3

AJ25
AE23

ICH_DPRSTP#
H_DPSLP# 3

AJ26

H_FERR#_R

R463

+1.05V

R442
56_4

3,6,39

56_4

H_FERR# 3

AD22

H_PWRGD 3

AF25

H_IGNNE#

AE22
AG25
L3

R219

10K_4

H_INIT# 3
H_INTR 3
+3V
RCIN# 35
H_NMI 3
H_SMI# 3

AF23
AF24
AH27
AG26

H_STPCLK# 3
H_THERMTRIP_R

AG27

R421

54.9/F_4

AH11
AJ11
AG12
AF12

SATA_TXN0_C
SATA_TXP0_C

H_THERMTRIP_RR

R430

56_4

R420

*0_4

+1.05V
PM_THRMTRIP# 3,6

4/21 Modify andy

T22

C661
C660

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

0.01u/16V_4
0.01u/16V_4

AH9
AJ9
AE10
AF10

27
27
27
27

No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)

Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
PU L<2"

SATA HDD

AH18
AJ18

CLK_PCIE_SATA# 2
CLK_PCIE_SATA 2

AJ7
AH7

SATA_RBIAS_PN
R170

SATABIAS L<0.5"

24.9/F_4

R470

IV@33_4

R477

33_4

24.000 MHz is output from the ICH9M.

C671

Weak integrated PD on the HDA_SDOUT pin.

Intel ICH9M

+1.05V

LFRAME# 28,35

J3
J1

ICH9MREV1.0

HD Audio

28,35
28,35
28,35
28,35

RTC
HDA_BIT_CLK_HDMI

ACZ_BITCLK_AUDIO

29

C668

C664

*10P/50V_4

*10P/50V_4

Pjt: BCBAT54CZ04
Ons: BCBAT54CZ70

+3VPCU

20MIL

+VCCRTC

D28

R489

20K_6

SRTC_RST#

VCCRTC_1

*10P/50V_4

+VCCRTC
D

R379

RTC
LPC

RTC_RST#
SRTC_RST#
SM_INTRUDER#

15P/50V_4

RTCX1
RTCX2

LAN / GLAN
CPU

C23
C24

IHDA

C593

U23A
CLK_32KX1
CLK_32KX2

3
4

EV@

R363
10M_6

SATA

Y3
32.768KHZ

IV@

2
1

ICH9M

C667

IV@33_4

R479

33_4

Weak integrated PD on the HDA_SYNC pins

HDA_SYNC_HDMI
ACZ_SYNC_AUDIO

6
HDA_RST#_R

29

R473

IV@33_4

R483

33_4

HDA_RST#_HDMI

R495

ACZ_RST#_AUDIO

1U/10V_4

*SHORT_PAD

R472

C675
1U/10V_4

1K_4

29

R497

20K_6

RTC_RST#

C672

HDA_SYNC_R

G2

BAT54C

20MIL

C699

G3

*10P/50V_4
6

South Bridge Strap Pin (1/3)

Strap description

Sampled

HDA_DOCK_EN/
GPIO33

Flash Descriptor Security

Override Strap

PWROK

SATALED#

PCI Express Lane Reversal

(Lanes 1-4)

PWROK

TP3

XOR Chain Entrance

PWROK

Pin Name

Configuration

PU/PD

0 = The Flash Descriptor Security will be overridden.

1 = The security measures defined
in the Flash Descriptor will be in effect

This strap should only be enabled in manufacturing

environments using an external pull-up resistor.

1
VCCRTC_2

HDA_SDIN_HDMI

3 RTC_N01

R480

Q21

20MIL

*MMBT3904

*16K_6

1U/10V_4

+5VPCU

*SHORT_PAD

IV@0_4

R481
*68.1K/F_4
RTC_RST#

RTC_N03

CN13
1
2 1
2

R166

HDA_SDIN2

R482
*150K/F_6

35

RTC_EC

RTC_CONN

Pitch: 1,25mm; Height: 1.95mm

A

HDA_SDOUT

XOR Chain Entrance /PCI Express*

Port Config 1 bit 1(Port 1-4)
5

PWROK

Change type 4/21 (ZQ7)

Internal PU
ICH_TP3

HDA_SDOUT

RSVD

Enter XOR Chain

Normal opration(Default)

Set PCIE port config bit 1

Description
14

ICH_TP3

ICH_TP3

HDA_SDOUT_R

R440

R370

*1K_4

352-(&7=4
4XDQWD&RPSXWHU,QF

*1K_4

Size

+3V

Document Number

Rev
1A

ICH9M HOST
Date:

Q22
DMN601K-7

Sheet 12

Monday, July 12, 2010

1

of

43

13

ICH9M
U23D

INTA#
INTB#
INTC#
INTD#

T116
T115
T124
T106

J5
E1
J6
C4

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#

T111
T40
T100
T107
T102
T103
T104
T41

L29
L28
M27
M26
J29
J28
K27
K26

D8
B4
D6
A5
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

IRDY#

C14
D4
R2

PLT_RST#

T113

PCIRST#
DEVSEL#
PERR#
LOCK#
SERR#
STOP#
TRDY#
FRAME#

WLAN
PCIRST#

28

T109
T114
T110
T120
T105
T117
T101

28
28
28
28

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

H4
K6
F2
G2

PLT_RST# 6
PCLK_ICH 2

GLAN

31
31
31
31

GLAN_RXN
GLAN_RXP
GLAN_TXN
GLAN_TXP

C401
C398
T48
T50

T51

INTE#
INTF#
INTG#
INTH#

G29
G28
0.1U/10V_4 PCIE_TXN4_C H27
0.1U/10V_4 PCIE_TXP4_C H26
E29
E28
F27
F26

PME# internal PU 18K~42K

PIRQA#
PIRQB#
PIRQC#
PIRQD#

C385
C386

T121
T123
T118
T119

4/22 add it

ICH9MREV1.0
C

28

USBOC#6

28

USBOC#10

For EMI
PCLK_ICH

C579

*33p/50V_4

C29
C28
0.1U/10V_4 GLAN_TXN_SB D27
D26
GLAN_TXP_SB
0.1U/10V_4
SPI_CLK_R
SPI_CS0#_R
SPI_CS1#

D23
D24
F23

SPI_MOSI
SPI_MISO

D25
E23

USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#7
USBOC#8
USBOC#9
USBOC#10
USBOC#11

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

SB_USBBIAS

5/12 Add
4/26 add it

AG2
AG1

PERN1
PERP1
PETN1
PETP1

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

PERN2
PERP2
PETN2
PETP2

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

PERN3
PERP3
PETN3
PETP3

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

PCI-Express

PCI

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

Direct Media Interface

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

F1
G4
B6
A7
F13
F12
E6
F6

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#

SPI

N29
N28
P27
P26

U23B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

USB

V27
V26
U29
U28

DMI_RXN0 6
DMI_RXP0 6
DMI_TXN0 6
DMI_TXP0 6

Y27
Y26
W29
W28

DMI_RXN1 6
DMI_RXP1 6
DMI_TXN1 6
DMI_TXP1 6

AB27
AB26
AA29
AA28

DMI_RXN2 6
DMI_RXP2 6
DMI_TXN2 6
DMI_TXP2 6

AD27
AD26
AC29
AC28

DMI_RXN3 6
DMI_RXP3 6
DMI_TXN3 6
DMI_TXP3 6

T26
T25

CLK_PCIE_ICH# 2
CLK_PCIE_ICH 2

AF29
AF28

DMI_IRCOMP_R

R409

24.9/F_4

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+

28
28
33
33
28
28
28
28
28
28

USBP6USBP6+
USBP7USBP7+

28
28
28
28

+1.5V

EXT-USB
CardReader
EXT-USB
Bluetooth 3.0
Wireless
INT-USB
Bluetooth 2.1

6/14 Modify
C

USBP11- 25
USBP11+ 25

CAMERA

ICH9MREV1.0
R172
22.6/F_4

L<0.5",Avoid routing next to clock/high speed signals.

+3V

South Bridge Strap Pin (2/3)

C400

Pin Name

0.1U/10V_4
PLT_RST#
LOCK#
INTD#
REQ3#
DEVSEL#
+3V

6
7
8
9
10

5
4
3
2
1

+3V

RN18

+3V

6
7
8
9
10

5
4
3
2
1

U19

R354

TC7SH08FU

100K_4

INTH#
INTG#

+3V_S5

+3V

PWROK

0 = Default
1 = Setting bit 0

GNT2# / GPIO53

PCI Express Port

Config 2 bit 2 (Port 5-6)

PWROK

0 = Setting bit 2
1 = Default

GNT1# / GPIO51

ESI Strap(Server Only)

PWROK

0 = DMI for ESI-compatible

1 = Default

5
4
3
2
1

USBOC#1
USBOC#5
USBOC#2
USBOC#3

+3V_S5

GNT3# / GPIO55

Top-Block Swap Override

PWROK

0 = "top-block swap" mode

1 = Default

GNT3#

R237

SPI_MOSI

Integrated TPM Enable

CLPWROK

0 = INT TPM disable(Default)

1 = INT TPM enable

SPI_MOSI

R380

GNT0#

Boot BIOS Selection 0

PWROK

GNT0#

R236

*1K_4

SPI_CS1#

R234

*1K_4

PCI_GNT#0
5
4
3
2
1

8.2K_10P8R

6
7
8
9
10
10K_10P8R

RN17

REQ0#

PCI Express Port

Config 1 bit 0 (Port 1-4)

+3V

6
7
8
9
10

PU/PD

RN19
USBOC#0
USBOC#6
USBOC#4
USBOC#7

8.2K_10P8R

PERR#

Configuration

REQ2#
FRAME#
REQ1#
STOP#

8.2K_10P8R

INTF#
INTC#
INTE#
SERR#

Sampled

HDA_SYNC
PLTRST# 28,31,33,35

1
3

+3V

RN16

Strap description

RN20
IRDY#
INTB#
INTA#
TRDY#

USBOC#10
USBOC#11
USBOC#8
USBOC#9

8
6
4
2

7
5
3
1

+3V_S5

SPI_CS1# /
GPIO58 / CLGPIO6

10K_8P4R

Boot BIOS Selection 1

CLPWROK

SPI_CS#1

*1K_4

*10K_4

+3V_S5

Boot Location

SPI

PCI

LPC(Default)

5/11 Swap

5/11 Swap

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

ICH9M PCIE / PCI / USB

Date:
5

Monday, July 12, 2010

1

Sheet 13

of

43

+3V_S5

R357

10K_4

SMB_CLK_ME

R356

10K_4

SMB_DATA_ME

R366

2.2K_4

PCLK_SMB

6$7$>[@*3SLQVLIXQXVHGUHTXLUH
NWRNSXOOXSWR9FFBRU
NWRNSXOOGRZQWRJURXQG

'$$6)LVVXHZKHQL$07LVQRWLPSOHPHQWHG

,&+060%XVDQG60/LQNVKRXOGEHFRQQHFWHGWRJHWKHUWRVXSSRUWVODYHPRGH
&RQQHFW60/,1.WR60%&/.DQG60/,1.WR60%'$7$$GG55IRUGHEXJXVH

4/20 Modify

14

U23C

ICH_GPIO60

R224

10K_4

SYS_RST#

4/20 Modify

T34

R376

10K_4

SMB_ALERT#

R223

10K_4

PCIE_WAKE#

R368

8.2K_4

PM_BATLOW#

R403

*10K_4
10K_4

ICH_GPIO12

R360

10K_4

ICH_GPIO13

R218

8.2K_4

CLKRUN#

R217

10K_4

SERIRQ

R445

8.2K_4

THERM_ALERT#

R359

10K_4

EC_SCI#

R390

*10K_4

SATACLKREQ#

R444

*10K_4

MCH_ICH_SYNC#

R439

10K_4

KBSMI#_ICH

R448

10K_4

LID591#_ICH

R240

10K_4

PM_STPPCI#

PWRBTN : 16 ms of internal debounce

logic on this pin and internal PU 24K

PM_SYNC#

35

R4
G19
M6

SMB_ALERT#

A17

PM_STPPCI#
PM_STPCPU#

A14
E19
L4

CLKRUN#

CLKRUN#

35
25,35

E20
M5
THERM_ALERT# AJ23
PCIE_WAKE#

D26
D27

KBSMI#
LID591#

35

AG19
AH21
AG21
A21
C12
ICH_GPIO12
C21
ICH_GPIO13
AE18
BOARD_ID0
K1
BOARD_ID1
AF8
PANEL_ID1
AJ22
BOARD_ID3
A9
D19
L1
SATACLKREQ#
AE19
CR_WAKE#
AG22
ICH_GPIO39
AF21
ICH_GPIO48
DMI_TERM_SEL AH24
A8
GPIO57
KBSMI#_ICH
LID591#_ICH

BAS316
BAS316

EC_SCI#

T98
T45
2 SATACLKREQ#
T129
T128

PM_STPCPU#

5/7 Modify

10K_4
GPIO57
*100/F_4

TPM Physical
Presence for
iTPM.

29
PCSPK
6 MCH_ICH_SYNC#
12 ICH_TP3
T130
T133
T131

D21
A20

T132

+3V_S5

R352

SYS_RST#

T54

R351

F19

VR_PWRGD_CLKEN

Stuff at GEN

10K_4

28,31 PCIE_WAKE#
35
SERIRQ
3 THERM_ALERT#

+3V

R221

SYS_RST#

2 PM_STPPCI#
2 PM_STPCPU#

DNBSWON#

R358

RI#

M7
MCH_ICH_SYNC# AJ24
B21
ICH_TP3
AH20
AJ20
AJ21

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA
GPIO

10K_4

SMB

RI#

R375

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

CLK14
CLK48

Clocks

PDAT_SMB

10K_4

G16
A13
E17
C17
B18

RI#
SUS_STAT#/LPCPD#
SYS_RESET#

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

PMSYNC#/GPIO0
SMBALERT#/GPIO11

S4_STATE#/GPIO26
STP_PCI#
STP_CPU#
CLKRUN#
WAKE#
SERIRQ
THRM#
VRMPWRGD
TP12

SYS GPIO
Power MGT

2.2K_4

R225

PCLK_SMB
PDAT_SMB
ICH_GPIO60
SMB_CLK_ME
SMB_DATA_ME

PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#

GPIO1
GPIO6
GPIO7
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
ENERGY_DETECT/GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
SPKR
MCH_SYNC#
TP3
TP9
TP10
TP11

CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1

MISC
GPIO
Controller Link

R367

2,16,28 PCLK_SMB
2,16,28 PDAT_SMB

CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

AH23
AF19
AE21
AD20

BOARD_ID2
PANEL_ID0 R181
ICH_GPIO36 R446
ICH_GPIO37 R408

H1
AF3

14M_ICH
CLKUSB_48

10K_4

CR_WAKE#

R222

10K_4

ICH_PWROK

Add 4/19

ICH PWROK

+3V
14M_ICH 2
CLKUSB_48 2

P1

ICH_SUSCLK

C16
E16
G17

SUSB#
SUSC#

For EMI

CLKUSB_48
35

4/14 Modify

14M_ICH

6,35
6,35

T36

C10

C407
*10p/50V_4

T99

G20

ICH_PWROK

M2

PM_DPRSLPVR

B13

C325
*10p/50V_4

6,39

PM_BATLOW#

R3

DNBSWON#

D20

PM_LAN_ENABLE_R

R372

*0/short_4

D22

PM_RSMRST#_R

R361

*0_4

R5

35

<Checklist ver0.8>
If integrated LAN is not used LAN_RST# tie it to GND.NC serial R from RSMRST#.
If Intel LAN is used with Wake On LAN, tie LAN_RST# to RSMRST# and NC 0ohm.

PM_RSMRST#_R
CK_PWRGD

R6

CL_PWROK must not assert after PWROK asserts for IAMT.

CL_PWROK to the NB and SB should be connected to existing PWROK inputs
on the NB and SB on a platform with no IAMT

MPWROK 6,35

B16

T53

F24
B19

CL VREF

CL_CLK0 6
T46

F22
C19

CL_DATA0

C25
A19

CL_VREF0_SB
CL_VREF1_SB

F21
D18

CL_RST#0 6

+3V

T42

A16
C18
C11
C20

ICH_GPIO10
ICH_GPIO14
ICH_GPIO9

T52
R374
R377
R371

10K_4
10K_4
10K_4

<Checklist ver0.8>
The ICH9M Controller
Link 1 VREF circuit is
required only if Intel
AMT is to be supported.

VREF1 CRB connect to

+3V_S5
Checklist connect to
+3V(iAMT reserve)

T49

+3V_S5

R353

R256

CL_VREF1_SB

Resume RST

+3V

*3.24K/F_6

=6'HIDXOWQRW
VXSSRUW,$076RWKLV
LQWHUIDFHIROORZ
&5%&KHFNOLVW38
RQO\

ICH9MREV1.0
R449

10K_4
10K_4
10K_4

3.24K/F_6
CL_VREF0_SB

R373

C584

R255

C436

*453/F_4

*0.1U/10V_4

453/F_4

0.1U/10V_4

M/B ID

+3V_S5
*10K_4

EC_SCI#

PM_RSMRST#_R

R362
B

+3V_S5

R462

10K_4

ICH_GPIO39

R447

10K_4

C582

*0.1U/10V_4

ICH_GPIO48

ICH_PWROK

DELAY_VR_PWRGOOD

PWROK_EC

R333

PWROK_EC

+3V

+3V

4.7K_4

+3V_S5

35

100K_4

R466

R389

R469

*10K_4

*10K_4

*10K_4

*10K_4

BOARD_ID3

BOARD_ID2

BOARD_ID1

BOARD_ID0

R468

R465

R385

R450

10K_4

10K_4

10K_4

10K_4

BAV99

R238

D12
BAV99

2.2K_4

ZD1 INTEL FAE (08/17)

"Add RSMRST# isolation (important!!! See
ww22 Santa Rosa MoW)"
Default stuff for Teenah(Interposer) chipset
ZS2 Intel FAE suggestion to add for to protect
RTC/CMOS data from corruption when system
encounters an abnormal power down
sequence

Board ID

default

South Bridge Strap Pin (3/3)

Pin Name

Strap description

CLK Enable

Sampled

Configuration

Reserved

PWROK

SPKR

No Reboot

PWROK

PU/PD

C439

GPIO49

DMI Termination
Voltage

PWROK

*0.1U/10V_4
U18

0 = Default
1 = No Reboot mode
0 = for desktop applications
1 = for mobile applications
Internal PU

39 VR_PWRGD_CK410#
PCSPK

R216

*1K_4

1
2
3

Size

*1K_4

Document Number

Rev
1A

ICH9M GPIO
4

ID0

352-(&7=4
4XDQWD&RPSXWHU,QF

R350

Date:
5

ID1

VR_PWRGD_CLKEN

+3V

100K_4
R464

ID2

NC7SZ04

DMI_TERM_SEL

ID3

+3V

GPIO20

R467

3,6,39

TC7SH08FU

Follow CHECK LIST V1.5

+3V

D14
4/20 Modify

3
1

4
U16

R248
2

PANEL_ID1

+3V

MMBT3906

10K_4

R451

RSMRST# 35

10K_4

'(/$<B95B3:5*22'QHHG38.WR9
=638DWSRZHUVLGH

+3V

1
Q11

R369

Monday, July 12, 2010

1

Sheet 14

of

43

15

ICH9M
Power consumption reference to
Intel ICH9 Family EDS Rev 1.6
2~3.456v
3.6uA_G3

0.1U/10V_4

AE1

D24

+5V

R365

1 CH751

SB_V5REF
C596

+3V_S5

100_6

D25

5V
S0:2mA
S3/4/5:1mA

1 CH751

1U/10V_4
+5VPCU_ICH_V5REF_SUS
C640

+5V_S5

R404

100_6
1U/10V_4

1.5V
646mA

330 Ohms@ 100 MHz , 0805

+1.5V

L33

2 BLM21PG331SN1D
+ C366

+1.5V_B
C378

220U/6.3V_7343

22U/6.3V_8

C364

C395

2.2U/6.3V_6

22U/6.3V_8

1.5V
47mA
L54

+1.5V

10uh_8

+1.5V_APLL_ICH
C655

10U/6.3V_8

1U/10V_4

VCC1_5_A
1.5V
1342mA

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

C313
1U/10V_4

1U/10V_4

AC9
AC18
AC19
AC21

1.5V
11mA

G10
G9
AC12
AC13
AC14

C315
0.1U/10V_4

AJ5

1.05V , Powered by VCC1_05 in S0

3.3V
S0:19mA
S3/4/5:78mA

C583

0.1U/10V_4
0.1U/10V_4 VCCLAN1_05_INT_ICH

A12
B12

+3V

L45

1uh_6

1.5V
23mA

1.5V
80mA

MODIFY
follow ZR6

+1.5V_B

C585

A27

0.1U/10V_4

D28
D29
E26
E27

+1.5V_ICH_GLANPLL_R

A26

C597
10U/6.3V_8

C600
2.2U/6.3V_6

V_CPU_IO[1]
V_CPU_IO[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCHDA

VCCSATAPLL

VCCSUSHDA

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

VCCSUS1_05[1]
VCCSUS1_05[2]

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

VCC1_5_A[17]
VCC1_5_A[18]
VCC1_5_A[19]
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C358

C350

0.1U/10V_4

0.1U/10V_4

+1.5V_ICH_VCCDMIPLL

1.5V
23mA
L46

C620

C612

0.01U/25V_4

10U/6.3V_8

1uh_6

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL1_05
VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]

+1.5V

500 mA, 20%

1.05V
50mA
+1.05V_ICH_DMI

L34

C340

C341

4.7U/6.3V_6

NBQ160808T-100Y-N

+1.05V

5 Ohms @ 100 MHz , 0.7A

22U/6.3V_8
+1.05V

1.05V
2mA

R29
W23
Y23

C373

C357

C337

0.1U/10V_4

0.1U/10V_4

4.7U/6.3V_6

AB23
AC23
AG29

+3V

AJ6

C326

C310

C316

AC10

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

3.3V
308mA

AD19
AF20
AG24
AC20
B9
F9
G3
G6
J2
J7
K7

,PSDFW,&+09&&+'$DQG
9&&686+'$VXSSO\99
C411

C317

0.1U/10V_4

C383

0.1U/10V_4

0.1U/10V_4
C656

R458

EV@0_6 +3V

R457

IV@0_6

1.5V / 3.3V
11mA

+1.5V

6XSSRUW,17+'0,+'$
LQWHUIDFH7KHVHSRZHU
RQO\VXSSRUW9'HYLFH
PXVWWRPHHW

0.1U/10V_4
AJ4

+3V_HDA_IO_ICH

AJ3

+3V_VCCSUSHDA

AC8
F17

TP_VCCSUS1_05_ICH_1
TP_VCCSUS1_05_ICH_2

AD8

TP_VCCSUS1_5_ICH_1

F18

VCCSUS1_5_INT_ICH

T26
T37

R459

EV@0_6

C657

R460

[email protected]_4

0.1U/10V_4

R461
IV@10K_6

T25

A18
D16
D17
E22

1.5V / 3.3V
S0:11mA
S3/4/5:1mA

NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
be used on the platform.

VCCSUS1_05 power by VCC1_05 in S0 / VCCSUS3_3 in S3/S4/S5

VCCSUS1_5 power by VCC1_5_A in S0 / VCCSUS3_3 in S3/S4/S5

AF1

+3V_S5

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
G22

VCCCL1_05_INT_ICH

G23

VCCCL1_5_INT_ICH

A24
B24

+3V_S5

5/10 change R8382 value to 12.1K

0.1U/10V_4

C343

C349

C352

0.022U/16V_4

0.022U/16V_4

0.1U/10V_4

C390
0.1U/10V_4

C388

C389

*1U/10V_4

*0.1U/10V_4

3.3V
S0:212mA
S3/4/5:53mA

VCCCL1_05 power by VCC1_05_A in S0

VCCCL1_5 power by VCC1_5_A in S0

3.3V
S0:19mA
S3/4/5:73mA

VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]

+3V

VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

U23E
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

+1.05V

C397

GLAN POWER

If use SB MAC for LAN function.

And support wake up need
connect to relation power.
+1.5V

A10
A11

VCC_DMI[1]
VCC_DMI[2]

USB CORE

C329

AA7
AB6
AB7
AC6
AC7

VCCDMIPLL

ATX

C331

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

ARX

C662

AJ19

V5REF_SUS

VCCA3GP

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

V5REF

CORE

0.1U/10V_4

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCP_CORE

C595

VCCRTC

PCI

A6

C592

5V
2mA
+3V

1.05V
1634mA

U23F
A23

+VCCRTC

VCCPSUS

PER INTEL SUGGESTION:

CHANGE TO 100OHM & 1UF

EV@

VCCPUSB

IV@

If use SB MAC for LAN function. And

support wake up need connect to
relation power.

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH9MREV1.0

VCCGLAN3_3
ICH9MREV1.0

C372

3.3V
1mA

4.7U/6.3V_6

+3V

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

ICH9 POWER
Date:
5

Monday, July 12, 2010

1

Sheet 15

of

43

DDR3 (DDR)

+3V

STD H=4.0 MM

DGMK4000004

FOX

DGMK4000117

LTK

2,14,28 PDAT_SMB
M_A_DQ[63:0]

TP4

R269
R268

10K/F_4
10K/F_4

8
8
8
6
6
6
6
6
6
6
6
8
8
8

M_A_BS0
M_A_BS1
M_A_BS2
M_CS#0
M_CS#1
M_CLK0
M_CLK#0
M_CLK1
M_CLK#1
M_CKE0
M_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#

17
17

SCL_DDR
SDA_DDR

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

DIMM0_SA0
DIMM0_SA1
SCL_DDR
SDA_DDR

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
W E#
SA0
SA1
SCL
SDA

116
120

6
M_ODT0
6
M_ODT1
8 M_A_DM[7:0]

8 M_A_DQS[7:0]

8 M_A_DQS#[7:0]

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

11
28
46
63
136
153
170
187

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186

ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

10K_4

10K_4
SDA_DDR

Q15

8
+3V

SCL_DDR

Q16
RHU002N06
+1.5V_SUS

CN9B

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199

+3V

77
122
125
198
30

6 PM_EXTTS#0
6,17 DDR3_DRAMRST#

1
126

+SMDDR_VREF

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2
G1
G2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

C459

C460

C449

C457

C461

C477

C451

C448

5/13 Add

C464 *470P/50V_4

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

*0.1U/10V_4

0.1u/10V_4

*0.1U/10V_4

0.1u/10V_4

*0_6

+SMDDR_VTERM 17,40,42

C67
+

10U/6.3V_6

+SMDDR_VREF

4/29 Modfiy type

C454

+SMDDR_VTERM

G1
G2

DDR3-DIMM0

Place these Caps near So-Dimm0.

C475

203
204

R272
C458

RHU002N06

2,14,28 PCLK_SMB

DDR3-DIMM0

+1.5V_SUS

R306

M_A_A[14:0]

R307

PC2100 DDR3 SDRAM SO-DIMM

(204P)

PC2100 DDR3 SDRAM SO-DIMM

(204P)

CN9A
D

16

QCI P/N

C489

0.1u/10V_4

R271
*22U/6.3V_8

R270

*10K/F_4

*10K/F_4

+1.5V_SUS

330U/2V_7343

+3V

+SMDDR_VREF

+SMDDR_VTERM

7/05 Modfiy_del C539.

C462

C463

C455

C456

C536

C552

C533

C553

C556

C555

0.1u/10V_4

2.2U/6.3V_6

2.2U/6.3V_6

0.1u/10V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

*10U/6.3V_6

10U/6.3V_6

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

DDR3 DIMM-0(H=5.2)
Date:
5

Sheet 16

Monday, July 12, 2010

1

of

43

DDR3 (DDR)

STD H=8.0 MM

17

QCI P/N

LTK

DGMK4000097

FOX

DGMK4000130

M_B_DQ[63:0] 8

M_B_A[14:0]

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

TP3

R263
R262

10K/F_4
10K/F_4

+3V

8
8
8
6
6
6
6
6
6
6
6
8
8
8

M_B_BS0
M_B_BS1
M_B_BS2
M_CS#2
M_CS#3
M_CLK2
M_CLK#2
M_CLK3
M_CLK#3
M_CKE2
M_CKE3
M_B_CAS#
M_B_RAS#
M_B_WE#

DIMM1_SA0
DIMM1_SA1

16 SCL_DDR
16 SDA_DDR

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
W E#
SA0
SA1
SCL
SDA

116
120

6
M_ODT2
6
M_ODT3
8 M_B_DM[7:0]

8 M_B_DQS[7:0]

8 M_B_DQS#[7:0]

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

11
28
46
63
136
153
170
187

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186

ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

PC2100 DDR3 SDRAM SO-DIMM

(204P)

CN10A
8

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

+1.5V_SUS

CN10B

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199

+3V

77
122
125
198
30

6 PM_EXTTS#1
6,16 DDR3_DRAMRST#

1
126

+SMDDR_VREF

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

DDR3-DIMM1

+1.5V_SUS

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2
G1
G2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

+SMDDR_VTERM

G1
G2

DDR3-DIMM1

Place these Caps near So-Dimm1.

5/6 Modfiy

C483

C488

C476

C478

C482

C481

C486

C473

C487

C479

C474

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

*0.1U/10V_4

0.1u/10V_4

*0.1U/10V_4

0.1u/10V_4

0.1u/10V_4

C490
330U/2V_7343

+3V

+SMDDR_VREF

+SMDDR_VTERM

7/05 Modfiy_del C538.

C485

C484

C453

C452

C543

C547

C540

C537

C535

C534

0.1u/10V_4

2.2U/6.3V_6

2.2U/6.3V_6

0.1u/10V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

*10U/6.3V_6

10U/6.3V_6

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

DDR3 DIMM-1(H=9.2)
Date:
5

Sheet 17

Monday, July 12, 2010

1

of

43

GPU_1(VGA)

Modfiy it 5/4 Reversal PICE

U28A

7,26 PEG_TXP[0..15]
7,26 PEG_TXN[0..15]

0518 SWAP PCIE for VGA side

0518 SWAP PCIE for VGA side

7,26 PEG_RXP[0..15]

5/18 add
D

7,26
7,26

PEG_TXP0
PEG_TXN0

7,26
7,26

PEG_TXP1
PEG_TXN1

7,26
7,26

PEG_TXP2
PEG_TXN2

7,26
7,26

PEG_TXP3
PEG_TXN3

RN29

1
3

2 EV@0_4P2R PEG_TXP0_R AA38

4
PEG_TXN0_R Y37

RN30

1
3

2 EV@0_4P2R PEG_TXP1_R Y35

4
PEG_TXN1_R W36

RN31

1
3

2 EV@0_4P2R PEG_TXP2_R W38

4
PEG_TXN2_R V37

1
3

2 EV@0_4P2R PEG_TXP3_R V35

4
PEG_TXN3_R U36

RN32

PEG_TXP4
PEG_TXN4

7
7

PEG_TXP5
PEG_TXN5

7
7

PEG_TXP6
PEG_TXN6

7
7

PEG_TXP7
PEG_TXN7

7
7

PEG_TXP8
PEG_TXN8

7
7

PEG_TXP9
PEG_TXN9

7
7

PEG_TXP10
PEG_TXN10

7
7

PEG_TXP11
PEG_TXN11

7
7

PEG_TXP12
PEG_TXN12

7
7

PEG_TXP13
PEG_TXN13

7
7

PEG_TXP14
PEG_TXN14

7
7

PEG_TXP15
PEG_TXN15

PEG_TXP4
PEG_TXN4

U38
T37

PEG_TXP5
PEG_TXN5

T35
R36

PEG_TXP6
PEG_TXN6

R38
P37

PEG_TXP7
PEG_TXN7

P35
N36

PEG_TXP8
PEG_TXN8

N38
M37

PEG_TXP9
PEG_TXN9

M35
L36

PEG_TXP10
PEG_TXN10

L38
K37

PEG_TXP11
PEG_TXN11

K35
J36

PEG_TXP12
PEG_TXN12

J38
H37

PEG_TXP13
PEG_TXN13

H35
G36

PEG_TXP14
PEG_TXN14

G38
F37

PEG_TXP15
PEG_TXN15

F35
E37

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

7
7

PCIE_RX0P
PCIE_RX0N

PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

Y33
Y32

CPEG_RXP0
CPEG_RXN0

C217
C226

[email protected]/10V_4
[email protected]/10V_4

W33
W32

CPEG_RXP1
CPEG_RXN1

C199
C209

[email protected]/10V_4
[email protected]/10V_4

U33
U32

CPEG_RXP2
CPEG_RXN2

C187
C197

[email protected]/10V_4
[email protected]/10V_4

U30
U29

CPEG_RXP3
CPEG_RXN3

C184
C179

[email protected]/10V_4
[email protected]/10V_4

T33
T32

CPEG_RXP4
CPEG_RXN4

C168
C163

[email protected]/10V_4
[email protected]/10V_4

T30
T29

CPEG_RXP5
CPEG_RXN5

C159
C150

[email protected]/10V_4
[email protected]/10V_4

P33
P32

CPEG_RXP6
CPEG_RXN6

C148
C141

[email protected]/10V_4
[email protected]/10V_4

P30
P29

CPEG_RXP7
CPEG_RXN7

C135
C126

[email protected]/10V_4
[email protected]/10V_4

N33
N32

CPEG_RXP8
CPEG_RXN8

C123
C114

[email protected]/10V_4
[email protected]/10V_4

N30
N29

CPEG_RXP9
CPEG_RXN9

C112
C109

[email protected]/10V_4
[email protected]/10V_4

L33
L32

CPEG_RXP10
CPEG_RXN10

C103
C99

[email protected]/10V_4
[email protected]/10V_4

L30
L29

CPEG_RXP11
CPEG_RXN11

C97
C89

[email protected]/10V_4
[email protected]/10V_4

K33
K32

CPEG_RXP12
CPEG_RXN12

C80
C83

[email protected]/10V_4
[email protected]/10V_4

J33
J32

CPEG_RXP13
CPEG_RXN13

C72
C79

[email protected]/10V_4
[email protected]/10V_4

K30
K29

CPEG_RXP14
CPEG_RXN14

C62
C61

[email protected]/10V_4
[email protected]/10V_4

H33
H32

CPEG_RXP15
CPEG_RXN15

C71
C66

[email protected]/10V_4
[email protected]/10V_4

Y30

R91

[email protected]/F_4

Y29

R90

EV@2K/F_4

7 PEG_RXN[0..15]

18

PEG_TXP[0..15]
PEG_TXN[0..15]
PEG_RXP[0..15]
PEG_RXN[0..15]

PEG_RXP0 7
PEG_RXN0 7

PEG_RXP1 7
PEG_RXN1 7
PEG_RXP2 7
PEG_RXN2 7
PEG_RXP3 7,26
PEG_RXN3 7

Item

Quanta P/N

Park

AJ077400T08

Robson

AJ007740T02

PEG_RXP4 7
PEG_RXN4 7
PEG_RXP5 7
PEG_RXN5 7
PEG_RXP6 7
PEG_RXN6 7

PEG_RXP7 7
PEG_RXN7 7
PEG_RXP8 7
PEG_RXN8 7
PEG_RXP9 7
PEG_RXN9 7
PEG_RXP10 7
PEG_RXN10 7
PEG_RXP11 7
PEG_RXN11 7
PEG_RXP12 7
PEG_RXN12 7

PEG_RXP13 7
PEG_RXN13 7
PEG_RXP14 7
PEG_RXN14 7
PEG_RXP15 7
PEG_RXN15 7

CLOCK
AB35
AA36

2 CLK_PCIE_VGA
2 CLK_PCIE_VGA#

For Broadway, Madison and Park

the PWRGOOD ball must be conneccted to ground
R112

T19

EV@10K_4
GPU_RST#

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

AJ21
AK21
AH16
AA30

NC#1
NC#2
PWRGOOD
PERSTB

PCIE_CALRP
PCIE_CALRN

+1V

+1.0V

For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V

Quanta Computer Inc.

EV@Madison/Park_M2

PROJECT : ZQ5
Size

Document Number

Rev
1A

Madison/Park M2-PCIE I/F

Date:
5

Monday, July 12, 2010

Sheet
1

18

of

45

TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N

MUTI GFX
DPA

TX1P_DPA1P
TX1M_DPA1N

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

NC on Park
23 RAM_STRAP0
23 RAM_STRAP1
23 RAM_STRAP2

GPU Power-on sequence

T144

1 => +3V_D
2 => +VGPU_CORE
3 => +1V
4 => +1.5V_GPU
5 => +1.8V_GPU
6 => dGPU_PWROK

1.8V GPIO

NC on Park
+3V_D

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC

TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N

DPD
R115
EV@10K_4

R118
EV@10K_4

TX4P_DPD1P
TX4M_DPD1N

I2C
AK26
AJ26

TX5P_DPD0P
TX5M_DPD0N

T13

1/21 ramp remove IO_VID0

+3V_D

R155

3.3V GPIO

*EV@10K_4

25 EV_LVDS_BLON
23 SOUT_GPIO8
23 SIN_GPIO9
23 SCLK_GPIO10
23 GPU_GPIO11
23 GPU_GPIO12
23 GPU_GPIO13
T20
41

GPU_VID1
T15

23 ALT#_GPIO17
T146
41

+3V_D
R151

GPU_VID2
T10

23 SCS#_GPIO22

EV@10K_4
R154

+3V_D

R132
R133

*EV@10K/F_4

+3V_D

R126

*EV@10K_4 GPIO24_TRSTB
*EV@10K_4
T18
27M_CLK
*EV@10K_4
T17

D3D

2 PEG_CLKREQ#
R153
B

*EV@10K/F_4

26 HDMI_HP_EV

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AK24

+1.8V_GPU

27M_NONSS

R488
R487

*EV@0_4
*EV@0_4

XTALI_27M
27M_CLK

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG

G
GB
B
BB

DAC1

HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2
R2B
G2
G2B
B2
B2B
C
Y
COMP

HPD1

A2VDDQ
VREFG
A2VSSQ

C256
R135
EV@249/F_4

[email protected]/10V_4
[email protected]/10V_4

AT25
AR24

HDMITX0P_C
HDMITX0N_C

C677
C676

[email protected]/10V_4
[email protected]/10V_4

AU26
AV25

HDMITX1P_C
HDMITX1N_C

C694
C693

[email protected]/10V_4
[email protected]/10V_4

AT27
AR26

HDMITX2P_C
HDMITX2N_C

C679
C678

[email protected]/10V_4
[email protected]/10V_4

AR30
AT29

[email protected]/10V_4

R2SET

+1.8V_GPU

DDC/AUX
PLL/CLOCK

C294
EV@10u/6.3V_6

C286
EV@1u/6.3V_4

C295

DPLL_PVDD

[email protected]/10V_4
C688

EV@SBY100505T-121Y-N/300mA/120ohm_4
C258

C253

EV@10u/6.3V_6

EV@1u/6.3V_4

[email protected]/10V_4

+1.8V(5mA)
L16

EV@SBY100505T-121Y-N/300mA/120ohm_4
C261

C243

EV@10u/6.3V_6

[email protected]/10V_4

Y4
EV@27MHZ
C689

XTALI_27M
XTALO_27M
R499
EV@1M/F_4

AV33
AU34

AUX1P
AUX1N

DPLL_VDDC

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N

EV@27p/50V_4
23
23

+1.8V_GPU

AN31

EV@27p/50V_4

DPLL_VDDC

C267

DPLL_VDDC

TS_VDD

DDC1CLK
DDC1DATA

DPLL_PVDD
DPLL_PVSS

L21

+1.0V(125mA)
+1V

AM32
AN32

AF29
AG29

GPU_D+
GPU_DT11

TS_VDD

AK32
AJ32
AJ33

AK27
AJ27

VARY_BL
DIGON

EV_LVDS_BRIGHT
EV_LVDS_VDDEN

25
25

HDMITX0P 26
HDMITX0N 26
HDMITX1P 26
HDMITX1N 26

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

HDMITX2P 26
HDMITX2N 26

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

5/5 Add

AK35
AL36

AH35
AJ36
AG38
AH37

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AF35
AG36

TXOUT_U3P
TXOUT_U3N

AT33
AU32

C-test

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AR32
AT31
LVTMDP

AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16

T139
T135

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

T136
T140

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

T138
T134

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

T141
T145

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AU20
AT19

AP34
AR34

EV_TXLCLKOUT+ 25
EV_TXLCLKOUT- 25

AW37
AU35

EV_TXLOUT0+ 25
EV_TXLOUT0- 25

AR37
AU39

EV_TXLOUT1+ 25
EV_TXLOUT1- 25

AP35
AR35

EV_TXLOUT2+ 25
EV_TXLOUT2- 25

AN36
AP37

TXOUT_L3P
TXOUT_L3N

5/6 modify

AT21
AR20

Channel D N.C for Park-M2

AU22
AV21

EV_LVDS_VDDEN

R150

EV@10K_4

EV_LVDS_BRIGHT

R158

*EV@10K_4

EV_LVDS_BLON

R160

EV@10K_4

EV@Madison/Park_M2

AT23
AR22
ramp remove short pad

AD39
AD37

EXT_CRT_RED

AE36
AD35

EXT_CRT_GRN

AF37
AE38

EXT_CRT_BLU

DPLUS
DMINUS

THERMAL

DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
TSVDD
TSVSS

EV_CRT_RED

AC36
AC38
AB34

EV_HSYNC
EV_VSYNC
R95

R505
EV@150/F_4

23,25
23,25

R507
EV@150/F_4

25

EV_CRT_GRN

25

EV_CRT_BLU

25

R509
EV@150/F_4

EV@499/F_4

AD34
AE34

AVDD

AC33
AC34

VDD1DI

+1.8V_GPU

(1.8V@70mA AVDD)
AVDD

L20

EV@SBY100505T-121Y-N/300mA/120ohm_4

5/17 modify
AC30
AC31

R101

EV@0_4

AD30
AD31

R97

EV@0_4

AF30
AF31

R107

EV@0_4

C249
[email protected]/10V_4

C259
EV@1u/6.3V_4

C260
EV@10u/6.3V_6

(1.8V@100mA VDD1DI)
VDD1DI

L15

EV@SBY100505T-121Y-N/300mA/120ohm_4

SP@
C235
[email protected]/10V_4

DAC2 will be NC on future ASIC

AC32
AD32
AF32

C241
EV@1u/6.3V_4

C247
EV@10u/6.3V_6

Seymour no stuff
5/7

5/5 Modify

AD29
AC29

H2SYNC
V2SYNC

AG31
AG32

VDD1DI
R119

AG33

A2VDD

AD33

A2VDDQ

C251

DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

SP@
R517

R103

EV@715/F_4

Seymour no stuff
5/7
MXM_DDCCK_C 26
MXM_DDCDAT_C 26

+1.8V_GPU

(1.8V@2mA A2VDDQ)
A2VDDQ

AN20
AM20

L59
C710
[email protected]/10V_4

EV@SBY100505T-121Y-N/300mA/120ohm_4

C711
EV@1u/6.3V_4

T14
T16

AL29
AM29

AK30
AK29

Seymour no stuff
5/7

SP@

HDMI

AM19
AL19

AN21
AM21

*EV@10U/6.3V_8

+3V_D

AM27
AL27

AJ30
AJ31

*EV@10U/6.3V_8

(3.3V@130mA A2VDD)
EV@0_4

C225
[email protected]/10V_4

AM26
AN26

AL30
AM30

C242

EV@0_4

AF33
AA29

5/5 add for CRT issue

23
23

SP@

SP@
DPLL_PVDD

EV@SBY100505T-121Y-N/300mA/120ohm_4

HDMICLK+ 26
HDMICLK- 26

AV31
AU30

+1.8V(75mA)
L26

LVDS CONTROL

H2SYNC
V2SYNC

A2VDD
AH13

C692
C691

DAC2

R144
EV@499/F_4
VREFG

HDMICLK+_C
HDMICLK-_C

R
RB

VDD2DI
VSS2DI

5/6 Modify

AU24
AV23

SCL
SDA
GENERAL PURPOSE I/O

23
GPU_GPIO0
23
GPU_GPIO1
23
GPU_GPIO2
23 GPIO3_SMBDAT
23 GPIO4_SMBCLK

19

U28G

U28B

GPU_2(VGA)

EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
EV_CRTDCLK
EV_CRTDDAT

25
25

25
25

DDC AUX4 NC for Park_M2

LVDS
CRT
DDC AUX7 NC for Park_M2

Quanta Computer Inc.

EV@Madison/Park_M2

PROJECT : ZQ5
Size

Document Number

Date:

Monday, July 12, 2010

Rev
1A

Madison/Park M2-HOST I/F

5

Sheet
1

19

of

45

20

GPU_3(VGA)
Park M2-channel B used(S3 package use Channel A)

+1.5V_GPU

R58
[email protected]/F_4
MVREFDA

R59
EV@100/F_4

C84
[email protected]/10V_4

+1.5V_GPU

R62
[email protected]/F_4
MVREFSA

R60
EV@100/F_4

C88
[email protected]/10V_4

Used for Park-M2

+1.5V_GPU

R68

*EV@MD@243/F_4

R70

EV@PK@243/F_4

R110

*EV@MD@243/F_4

R64

EV@PK@243/F_4

R69
R111

*EV@MD@243/F_4
*EV@MD@243/F_4

Note by AN_M96_C1
Used for Madison-M2

MVREFDA
MVREFSA

L18
L20
L27
N12
AG12
M12
M27
AH12

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

WEA0B
WEA1B
GDDR5

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MEMORY INTERFACE A

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DDR2
GDDR5/GDDR3
DDR3

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA0_8
MAA1_8

24 VMB_RDQS[7..0]
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

24 VMB_WDQS[7..0]
24 VMB_MA[13..0]
24
24
24

VMB_DQ[63..0]
VMB_DM[7..0]
U28D
DDR2
GDDR3/GDDR5
DDR3

VMB_RDQS[7..0]
VMB_WDQS[7..0]
VMB_DQ0
VMB_DQ1
VMB_DQ2
VMB_DQ3
VMB_DQ4
VMB_DQ5
VMB_DQ6
VMB_DQ7
VMB_DQ8
VMB_DQ9
VMB_DQ10
VMB_DQ11
VMB_DQ12
VMB_DQ13
VMB_DQ14
VMB_DQ15
VMB_DQ16
VMB_DQ17
VMB_DQ18
VMB_DQ19
VMB_DQ20
VMB_DQ21
VMB_DQ22
VMB_DQ23
VMB_DQ24
VMB_DQ25
VMB_DQ26
VMB_DQ27
VMB_DQ28
VMB_DQ29
VMB_DQ30
VMB_DQ31
VMB_DQ32
VMB_DQ33
VMB_DQ34
VMB_DQ35
VMB_DQ36
VMB_DQ37
VMB_DQ38
VMB_DQ39
VMB_DQ40
VMB_DQ41
VMB_DQ42
VMB_DQ43
VMB_DQ44
VMB_DQ45
VMB_DQ46
VMB_DQ47
VMB_DQ48
VMB_DQ49
VMB_DQ50
VMB_DQ51
VMB_DQ52
VMB_DQ53
VMB_DQ54
VMB_DQ55
VMB_DQ56
VMB_DQ57
VMB_DQ58
VMB_DQ59
VMB_DQ60
VMB_DQ61
VMB_DQ62
VMB_DQ63

VMB_MA[13..0]

VMB_BA0
VMB_BA1
VMB_BA2

VMB_BA0
VMB_BA1
VMB_BA2

A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
+1.5V_GPU
K24
K27
M13
K16

R102
[email protected]/F_4

K21
J20

MVREFDB
MVREFSB

K26
L15
R96
EV@100/F_4
H23
J19

C198
[email protected]/10V_4
+3V_D

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
AA12

DDR2
GDDR5/GDDR3
DDR3

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

WEB0B
WEB1B

D3D
R120
R100

*EV@10K_4
EV@10K_4 AD28
AK10
AL10

GDDR5

24 VMB_DM[7..0]

MEMORY INTERFACE B

24 VMB_DQ[63..0]
U28C
DDR2
GDDR3/GDDR5
DDR3

TESTEN
CLKTESTA
CLKTESTB

MAB0_8
MAB1_8

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA2
VMB_BA0
VMB_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

VMB_DM0
VMB_DM1
VMB_DM2
VMB_DM3
VMB_DM4
VMB_DM5
VMB_DM6
VMB_DM7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

VMB_RDQS0
VMB_RDQS1
VMB_RDQS2
VMB_RDQS3
VMB_RDQS4
VMB_RDQS5
VMB_RDQS6
VMB_RDQS7

QSB[7..0]

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

VMB_WDQS0
VMB_WDQS1
VMB_WDQS2
VMB_WDQS3
VMB_WDQS4
VMB_WDQS5
VMB_WDQS6
VMB_WDQS7

QSB#[7..0]

T7
W7

VMB_ODT0 24
VMB_ODT1 24

L9
L8

VMB_CLKP0
VMB_CLKN0

AD8
AD7

VMB_CLKP1
VMB_CLKN1

T10
Y10

VMB_RAS0#
VMB_RAS1#

W10
AA10

VMB_CAS0#
VMB_CAS1#

P10
L10

VMB_CS0#

AD10
AC10

VMB_CS1#

U10
AA11

VMB_CKE0
VMB_CKE1

N10
AB11

VMB_WE0#
VMB_WE1#

T8
W8
AH11

VMB_CLKP0
VMB_CLKN0

24
24

VMB_CLKP1 24
VMB_CLKN1 24
VMB_RAS0#
VMB_RAS1#
VMB_CAS0#
VMB_CAS1#

24
24
24
24

VMB_CS0#

24

VMB_CS1#

24

VMB_CKE0
VMB_CKE1

24
24

VMB_WE0#
VMB_WE1#

24
24

VMB_MA13
R148

EV@10/F_4 R149

EV@51_4

MEM_RST# 24
B

+1.5V_GPU
AL31

R114
*EV@0_4

RSVD

R124
*EV@0_4

R140

C282
EV@120p/50V_4

[email protected]/F_4
EV@Madison/Park_M2

R106
[email protected]/F_4

R104
EV@100/F_4

EV@Madison/Park_M2

Place all these components very close to GPU (Within

25mm) and keep all component close to each Other (within
5mm)

C223
[email protected]/10V_4

5/17 Modify

Quanta Computer Inc.

PROJECT : ZQ5
Size

Document Number

Date:

Monday, July 12, 2010

Rev
1A

Madison/Park M2-MEM I/F

5

Sheet
1

20

of

45

21

GPU_4(VGA)
U28F
U28E

For DDR3, MVDDQ = 1.5V (3A)

MEM I/O

+1.5V_GPU

+1.8V_GPU
PCIE

C100
C118
C93
C96
C188
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6

C124
C208
C195
C108
C185
C85
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

C101
C113
C90
C169
C98
C122
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

C91
C139
C125
C164
C106
EV@1u/6.3V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4

C670
C233
C220
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4
+3V_D
C245
C237
C234
C240
EV@10u/6.3V_6
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

C255
C262
EV@1u/6.3V_4
[email protected]/10V_4

V12
U12

T8
T7

PCIE_PVDD

(1.8V@150mA MPV18)

AN9

SPV10

EV@SBY100505T-121Y-N/300mA/120ohm_4

AN10
C87
C105
C94
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

L24

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB

PCIE_PVDD
MPV18#1
MPV18#2
SPV18
SPV10
SPVSS

VOLTAGE
SENESE

(1.8V@75mA SPV18)

EV@SBY100505T-121Y-N/300mA/120ohm_4
T21
C278
C264
EV@10u/6.3V_6
[email protected]/10V_4

+1V

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

T9
T12

120 ohm/300mA
(1.0V@120mA SPV10)
L57
EV@SBY100505T-121Y-N/300mA/120ohm_4
C695
C690
EV@10u/6.3V_6
[email protected]/10V_4

L61

C206
C207
C180
C173
C721
C186
C720
C213
[email protected]/10V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
[email protected]/10V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@10u/6.3V_6

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

+1V

([email protected] PCIE_VDDC)

C152
C142
C92
C107
C162
C120
C146
C102
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@10u/6.3V_6

+VGPU_CORE
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

(30A or more)

C157
C160
C181
C182
C158
C221
C210
C155
C156
C204
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

AF28
AG28
AH29

FB_VDDC
FB_VDDCI
FB_GND

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

C200
C224
C193
C236
C214
C192
C165
C196
C178
C161
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

C191
C171
C190
C170
C143
C172
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6

BIF_VDDC should be connected to VDDC if BACO feature not used.

For BACO, refer to the databook

PIN different between Broadway and Madison

Pin

Broadway

5/14 modify

Madison

N27

VDDC BIF_VDDC

AL31

TS_A NC_TS_A

AL21

GND

+VGPU_IO

+VGPU_CORE

L12
EV@TI201209G121_8_3A
L10
EV@TI201209G121_8_3A

PX_EN

(DDR3 1.12V@4A VDDCI) or more

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

C144
C183
C127
C138
C205
C119
C110
C153
C133
C140
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

+3V
C218
C130
C117
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6

R162
*EV@0_6

EV@AO3413
Q5

EV@Madison/Park_M2

C306

C304

C305

EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

+3V

Q19
EV@DTC144EUA

PowerXpress control signal for Madsion and Park only

If not used, can be disconnected.
PX_EN = LOW, turn on
PX_EN = HIGH, turn off
PX_EN is used to turn ON/OFF some
regulators for PowerXpress mode. An
output high 3.3V will turn the regulators
OFF. An output low 0V will turn the
regulators ON. PX_EN outputs low (0V)
by default.
If this signal is unused, it can be NC (not
connected) or connected to ground.
R145 *EV@0_4

35,41,43 VGPU_ON

R164

*EV@0_4

R165

EV@0_4

Pin AL21 to Ground for Broadway

GPU Power-on sequence

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

1 => +3V_D
2 => +VGPU_CORE
3 => +1V
4 => +1.5V_GPU
5 => +1.8V_GPU
6 => dGPU_PWROK

A39
AW1
AW39

C307
*EV@1u/6.3V_4

Quanta Computer Inc.

+3V_D
C669

C673

C674

Spec: 0.15A
Rating: 3A

PROJECT :ZQ5

EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

Size
Date:

Document Number

Rev
1A

Madison/Park M2 (PWR/GND)

Modfiy it 5/4
5

0.5A

Q7
EV@DTC144EUA

C3C

+3V_D

R139
*EV@0_4

B-test

R157
*EV@0_6
EV@AO3413
Q6

3
2

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

R161
*EV@0_6

Fine-tune Power-on sequence

Q20
EV@2N7002K
35,38,40,42 MAINON

+1.8V_GPU

GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99

EV@Madison/Park_M2

3
2

Spec: 0.15A
Rating: 3A

+3V

R163
[email protected]_4

GPU +3V power

dGPU_PWROK 35

R474
EV@10K_4

+3V_D_EXT 23,41

0.5A

R490
EV@10K_4

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

+3V_D_EXT
VDDC_SENSE/VSS_SENSE and
VDDCI_SENSE/VSS_SENSE route as differetial pair

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

C238
C239
C212
C189
C246
C229
C216
C166
C215
C230
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

+3V

GPU all PWROK

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

EV@HCB1608KF-181T15/1.5A/180ohm_6

+1.8V_GPU

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

(1.8V@400mA PCIE_VDDR)

PCIE_VDDR

+VGPU_IO
AM10

SPV18
L13

AB37
H7
H8

MPV18
C719
C723
C722
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

+1.8V_GPU

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

PLL

(1.8V@40mA PCIE_PVDD)

EV@SBY100505T-121Y-N/300mA/120ohm_4

CORE

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

L60

AD12
AF11
AF12
AG11

M20
M21

T6
T5

+1.8V_GPU

AF23
AF24
AG23
AG24
AF13
AF15
AG13
AG15

EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4

L19

AF26
AF27
AG26
AG27

I/O

(3.3V@60mA))

+1.8V_GPU

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

POWER

VDDC_CT

EV@SBY100505T-121Y-N/300mA/120ohm_4

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

LEVEL
TRANSLATION

(1.8V@110mA VDD_CT)

L56

+1.8V_GPU

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

Monday, July 12, 2010

Sheet
1

21

of

45

GPU_5(VGA)

22

U28H
DP C/D POWER
DPC_VDD18

AP20
AP21

DPC_VDD10

AP13
AT13

DP A/B POWER

DPC_VDD18#1
DPC_VDD18#2

DPA_VDD18#1
DPA_VDD18#2

DPC_VDD10#1
DPC_VDD10#2

DPA_VDD10#1
DPA_VDD10#2

DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

DPD_VDD18#1
DPD_VDD18#2

DPB_VDD18#1
DPB_VDD18#2

DPD_VDD10#1
DPD_VDD10#2

DPB_VDD10#1
DPB_VDD10#2

DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

DPCD_CALR

DPAB_CALR

AN24
AP24

DPA_VDD18

AP31
AP32

DPA_VDD10

+1V

AN17
AP16
AP17
AW14
AW16

+1.8V_GPU

(1.8V@130mA DPA_VDD18)
L28

EV@SBY100505T-121Y-N/300mA/120ohm_4

DPA_VDD18

C285
C292
C279
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/10V_6

EV@SBY100505T-121Y-N/300mA/120ohm_4

DPC_VDD10

AP22
AP23

AP14
AP15

DPC_VDD18

C288
C287
C272
[email protected]/10V_4
EV@10u/6.3V_6
EV@1u/10V_6

AN27
AP27
AP28
AW24
AW26

AN19
AP18
AP19
AW20
AW22

R494

EV@150/F_4 DPCD_CALR AW18

AP25
AP26

AH34
AJ34

DPE_VDD10

AL33
AM33

DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2

DP PLL POWER
DPA_PVDD
DPA_PVSS

L22

EV@SBY100505T-121Y-N/300mA/120ohm_4

(1.0V@110mA DPC_VDD10)

L23

EV@SBY100505T-121Y-N/300mA/120ohm_4

DPA_VDD18
C276
C269
C263
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

AN33
AP33

DPA_VDD10

AN29
AP29
AP30
AW30
AW32

AW28

DPAB_CALR R498

EV@150/F_4

+1.8V_GPU

(1.8V@20mA DPA_PVDD)

DPA_PVDD
DPE_VDD18

(1.0V@110mA DPA_VDD10)

C271
C252
C257
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

DPC_VDD10
DPC_VDD18

(1.8V@130mA DPC_VDD18)
L29

DPA_VDD10

AU28
AV27

L27

EV@SBY100505T-121Y-N/300mA/120ohm_4

C280
C265
C266
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4
+1.8V_GPU

+1.8V_GPU
L14

(1.8V@400mA DPE/F_VDD18)
EV@HCB1608KF-181T15/1.5A/180ohm_6

DPB_PVDD
DPB_PVSS

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

DPC_PVDD
DPC_PVSS

AN34
AP39
AR39
AU37
AW35

DPE_VDD18

AF34
AG34

(1.0V@400mA DPE/F_VDD10)

180 ohm/1.5A
L18
EV@HCB1608KF-181T15/1.5A/180ohm_6

DPE_PVDD
DPE_PVSS
DPE_VDD10

AK33
AK34

DPF_VDD10#1
DPF_VDD10#2
NC_DPF_PVDD
NC_DPF_PVSS

AF39
AH39
AK39
AL34
AM34

R503

EV@150/F_4 DPEF_CALR AM39

(1.8V@20mA DPB_PVDD)

L30

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

EV@SBY100505T-121Y-N/300mA/120ohm_4

C297
C283
C290
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

AU18
AV17

+1.8V_GPU

(1.8V@20mA DPC_PVDD)

L58

DPF_VDD18#1
DPF_VDD18#2

DPE_VDD10

C248
C244
C273
[email protected]/10V_4
EV@10u/6.3V_6
EV@1u/6.3V_4

DPB_PVDD

DPC_PVDD
DPD_PVDD
DPD_PVSS

+1V

AV29
AR28

DPE_VDD18

C228
C227
C232
[email protected]/10V_4
EV@10u/6.3V_6
EV@1u/6.3V_4

DPE_VDD10#1
DPE_VDD10#2

EV@SBY100505T-121Y-N/300mA/120ohm_4

AV19
AR18
C680
C687
C697
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4
AM37
AN38

+1.8V_GPU
DPD_PVDD

(1.8V@20mA DPD_PVDD)

L31

AL38
AM35

EV@SBY100505T-121Y-N/300mA/120ohm_4

C303
C293
C299
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4

+1.8V_GPU

(1.8V@40mA DPE/F_PVDD)

DPE_PVDD

L25

EV@SBY100505T-121Y-N/300mA/120ohm_4

C298
C291
C275
EV@10u/6.3V_6
[email protected]/10V_4
EV@1u/6.3V_4
A

DPEF_CALR
EV@Madison/Park_M2

Quanta Computer Inc.

PROJECT : ZQ5
Size

Document Number

Rev
1A

Madison/Park M2 (DP_PWR/GND)
Date:
5

Monday, July 12, 2010

Sheet
1

22

of

45

PIN STRAPS(VGA)

+3V_D

23

CONFIGURATION STRAPS
19

GPU_GPIO0

19

GPU_GPIO1

R128

19 GPIO3_SMBDAT
19 GPIO4_SMBCLK

*EV@10K_4

R127

*EV@10K_4

R122

*EV@10K_4

R123

*EV@10K_4

SCS#_GPIO22 R475

*EV@10K_4

R129

*EV@10K_4

R138

*EV@10K_4

R136

EV@10K_4

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

ROM Table
STRAPS

Size of the primary

memory apertures

19

GPU_GPIO13

19

GPU_GPIO12

19

GPU_GPIO11

19

GPU_GPIO2

19,25 EV_HSYNC
19,25 EV_VSYNC
SIN_GPIO9
19

V2SYNC

19

H2SYNC

5/17 Modify

R134

*EV@10K_4

R512

EV@10K_4

R518

EV@10K_4

R476

*EV@10K_4

R156

*EV@10K_4

R159

*EV@10K_4

SCS#_GPIO22 R121

*EV@10K_4

GPU_GPIO13

R125

*EV@10K_4

GPU_GPIO12

R137

*EV@10K_4

GPU_GPIO11

R131

*EV@10K_4

CONFIG[2:0]

128 MB

000

256 MB

001

64 MB

010

32 MB

011

EXT_HSYNC

EXT_VSYNC

0
0
1
1

5/17 Add

Discription
No Audio

0
1
0
1

DESCRIPTION OF DEFAULT SETTINGS

GPIO0

0 = 50% TX OUTPUT SWING

1 = FULL TX OUTPUT SWING

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED

0 = TX DE-EMPHASIS DISABLED
1 = TX DE-EMPHASIS ENABLED
ENABLE EXTERNAL BIOS ROM
0 = DISABLE
1 = ENABLE

GPIO_22_ROMCSB

ROMIDCFG(2:0)

GPIO[13:11]

BIF_GEN2_EN_A

GPIO2

GPIO_8_ROMSO
H2SYNC
GPIO_21_BB_EN

GPIO8
H2SYNC
GPIO21

AUD[1]

HSYNC

AUD[0]

VSYNC

001

0 = PCIE DEVICE AS 2.5GT/S CAPABLE

1 = PCIE DEVICE AS 5GT/S CAPABLE

Reserved Only

AUD[1:0]
00: NO AUDIO FUNCTION.
01: AUDIO FOR DISPLAYPORT AND HDMI IF
ADAPTER IS DETECTED.
10: AUDIO FOR DISPLAYPORT ONLY.

11

table 3-35

See Audio table

0 = VGA controller capacity enable

GPIO9

VIP_DEVICE_STRAP_ENA

V2SYNC

0 = DRIVER would ignore the value sample on VHAD_0 during RESET.

DDR3 Memory Aperture size(GPU)

EEPROM(VGA)
U25
19

11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.

GPIO_9_ROMSI

Both DP & HDMI

REMARK

Primary Memory Aperture size requested at PCI Configuration

Any one by dectec

DP only

DEFAULT

TX_PWRS_ENB

BIOS_ROM_EN

ROM Table
5/5 Modify

PIN

SIN_GPIO9

SIN_GPIO9

19 SCLK_GPIO10

R441

B-test

Vendor P/N

STN B/S P/N

RAM_STRAP2

RAM_STRAP1

RAM_STRAP0

DVPDATA_2

DVPDATA_1

DVPDATA_0

AKD5LGGT506
(64M*16)

AKD5MGGT500
(128M*16)

8
R438
*EV@10K_4

Vendor

HOLD

*EV@10K_4

SOUT_GPIO8 19

+3V_D_EXT

DDR3 Memory Aperture size

SOUT_GPIO8

SCS#_GPIO22

19 SCS#_GPIO22

VCC

VSS

Hynix

*EV@M25P10-AVMN6P

H5TQ1G63BFR-12C

AKD5LZGTW04
(64M*16)

C665
*[email protected]/10V_4
B

Thermal Sensor(VGA)
Vendor
5/6 modify

+3V_D_EXT

Samsung

P/N

WINDBOND

AL83L771K01

GMT

AL000780000

K4W1G1646E-HC12
K4W2G1646B-HC12

USD0.16

B-test
+3V_D_EXT

R418
EV@10K_4

R419
EV@10K_4

C641

[email protected]/10V_4
+1.8V_GPU

U24

35 VGA_CLK

35 VGA_DATA

7
6

19 ALT#_GPIO17

35 VGA_THERM#

SCLK

VCC

SDA

DXP

ALERT#
OVERT#

DXN
GND

GPU_D+

19
19 RAM_STRAP2

C645

*EV@10K_4
EV@10K_4

R486

*EV@10K_4

R493

EV@10K_4

R484

*EV@10K_4

R491

EV@10K_4

EV@2200p/50V_4
GPU_D-

19
19 RAM_STRAP1

EV@G780P81U(MSOP-8)

B-test

R485
R492

RAM_STRAP2 SET DDR3 Vendor

RAM_STRAP[1:0] SET SIZE.

Quanta Computer Inc.

$''5(66+

19 RAM_STRAP0

PROJECT :ZQ5
Size

Document Number

Rev
1A

Strip/Thermal
Date:

Monday, July 12, 2010

Sheet
1

23

of

45

24

CHANNEL B: 512MB DDR3 (16*64M*4pcs)

VMB_DQ[63..0]

20 VMB_DQ[63..0]

VMB_DM[7..0]

20 VMB_DM[7..0]
20 VMB_RDQS[7..0]
20 VMB_WDQS[7..0]

VMB_RDQS[7..0]

QSA[7..0]

VMB_WDQS[7..0]

QSA#[7..0]

20
20
20
20
20
20
20
20
20
20
20
20
20
20

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13

20
20
20

VMB_BA0
VMB_BA1
VMB_BA2

20
20
20

VMB_CLKP0
VMB_CLKN0
VMB_CKE0

20
20
20
20
20

VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#

20

U4

VREFC_VMB1
VREFD_VMB1

M8
H1

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VMB_BA0
VMB_BA1
VMB_BA2

M2
N8
M3

VMB_CLK0
VMB_CLK0#
VMB_CKE0

J7
K7
K9

VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#

K1
L2
J3
K3
L3

VMB_RDQS0
VMB_RDQS3

F3
C7

VMB_DM0
VMB_DM3

E7
D3

VMB_WDQS0
VMB_WDQS3

G3
B7

MEM_RST#

T2

MEM_RST#
VMB_ZQ1

L8

U30

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

E3
F7
F2
F8
H3
H8
G2
H7

VMB_DQ4
VMB_DQ3
VMB_DQ5
VMB_DQ0
VMB_DQ6
VMB_DQ1
VMB_DQ7
VMB_DQ2

D7
C3
C8
C2
A7
A2
B8
A3

VMB_DQ26
VMB_DQ27
VMB_DQ28
VMB_DQ31
VMB_DQ24
VMB_DQ29
VMB_DQ25
VMB_DQ30

0
3

VREFC_VMB2
VREFD_VMB2

M8
H1

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VMB_BA0
VMB_BA1
VMB_BA2

M2
N8
M3

VMB_CLK0
VMB_CLK0#
VMB_CKE0

J7
K7
K9

+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

R73
EV@240/F_4
J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#

K1
L2
J3
K3
L3

VMB_RDQS2
VMB_RDQS1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMB_DM2
VMB_DM1

E7
D3

VMB_WDQS2
VMB_WDQS1

G3
B7

MEM_RST#

T2

VMB_ZQ2

B1
B9
D1
D8
E2
E8
F9
G1
G9

L8

100-BALL
SDRAM DDR3
SP@VRAM_DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

E3
F7
F2
F8
H3
H8
G2
H7

VMB_DQ19
VMB_DQ21
VMB_DQ17
VMB_DQ18
VMB_DQ20
VMB_DQ22
VMB_DQ16
VMB_DQ23

D7
C3
C8
C2
A7
A2
B8
A3

VMB_DQ15
VMB_DQ11
VMB_DQ14
VMB_DQ10
VMB_DQ12
VMB_DQ9
VMB_DQ13
VMB_DQ8

2
1

VREFC_VMB3
VREFD_VMB3

M8
H1

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VMB_BA0
VMB_BA1
VMB_BA2

M2
N8
M3

VMB_CLK1
VMB_CLK1#
VMB_CKE1

J7
K7
K9

+1.5V_GPU

BA0
BA1
BA2

R524
EV@240/F_4
J1
L1
J9
L9

U27

VREFCA
VREFDQ

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

20
20
20

VMB_CLKP1
VMB_CLKN1
VMB_CKE1

20
20
20
20
20

VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#

K1
L2
J3
K3
L3

VMB_RDQS4
VMB_RDQS7

F3
C7

VMB_DM4
VMB_DM7

E7
D3

VMB_WDQS4
VMB_WDQS7

G3
B7

MEM_RST#

T2

VMB_ZQ3

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

R506
EV@240/F_4

100-BALL
SDRAM DDR3
SP@VRAM_DDR3

BOT Down

L8

U7

VREFCA
VREFDQ

NC#J1
NC#L1
NC#J9
NC#L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

VMB_DQ36
VMB_DQ39
VMB_DQ33
VMB_DQ35
VMB_DQ37
VMB_DQ32
VMB_DQ38
VMB_DQ34

VREFC_VMB4
VREFD_VMB4

M8
H1

VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

D7
C3
C8
C2
A7
A2
B8
A3

VMB_DQ62
VMB_DQ58
VMB_DQ63
VMB_DQ56
VMB_DQ61
VMB_DQ57
VMB_DQ60
VMB_DQ59

VMB_BA0
VMB_BA1
VMB_BA2

M2
N8
M3

VMB_CLK1
VMB_CLK1#
VMB_CKE1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#

K1
L2
J3
K3
L3

VMB_RDQS6
VMB_RDQS5

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMB_DM6
VMB_DM5

E7
D3

VMB_WDQS6
VMB_WDQS5

G3
B7

MEM_RST#

T2

4
7

+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU

L8

VMB_ZQ4

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

VMB_DQ40
VMB_DQ47
VMB_DQ42
VMB_DQ46
VMB_DQ43
VMB_DQ45
VMB_DQ41
VMB_DQ44

6
D

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE

DQSL
DQSU

VMB_DQ52
VMB_DQ50
VMB_DQ55
VMB_DQ49
VMB_DQ53
VMB_DQ48
VMB_DQ54
VMB_DQ51

+1.5V_GPU

BA0
BA1
BA2

ODT
CS
RAS
CAS
WE

E3
F7
F2
F8
H3
H8
G2
H7

+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSL
DQSU

RESET
ZQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3
SP@VRAM_DDR3

TOP Up

Group-B0 VREF

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

R93
EV@240/F_4

100-BALL
SDRAM DDR3
SP@VRAM_DDR3

TOP Down

VREFCA
VREFDQ

BOT Up

Group-B1 VREF
+1.5V_GPU

+1.5V_GPU

R76
[email protected]/F_4

R67
[email protected]/F_4

VREFC_VMB1

R75
[email protected]/F_4

+1.5V_GPU

C136
[email protected]/10V_4

R523
[email protected]/F_4

VREFD_VMB1

R63
[email protected]/F_4

+1.5V_GPU

C104
[email protected]/10V_4

+1.5V_GPU

R528
[email protected]/F_4

R516
[email protected]/F_4

+1.5V_GPU

R521
[email protected]/F_4

+1.5V_GPU

R105
[email protected]/F_4

R142
[email protected]/F_4

VREFC_VMB2

VREFD_VMB2

VREFC_VMB3

VREFD_VMB3

VREFC_VMB4

VREFD_VMB4

R525
C731
[email protected]/F_4
[email protected]/10V_4

R529
C742
[email protected]/F_4
[email protected]/10V_4

R511
C709
[email protected]/F_4
[email protected]/10V_4

R522
C726
[email protected]/F_4
[email protected]/10V_4

R109
C219
[email protected]/F_4
[email protected]/10V_4

R141
C281
[email protected]/F_4
[email protected]/10V_4

Group-B0 decoupling CAP

MEM_B0 CLK

+1.5V_GPU

Group-B1 decoupling CAP

+1.5V_GPU

MEM_B1 CLK

+1.5V_GPU
VMB_CLK1

VMB_CLK0

VMB_CLK1#
C733
C95
C751
C748
C57
C151
C301
C752
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

VMB_CLK0#
R66
R65
[email protected]/F_4
[email protected]/F_4

C203
C698
C70
C211
C78
C137
C708
C707
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

+1.5V_GPU

R108
R113
[email protected]/F_4
[email protected]/F_4

+1.5V_GPU

C222
[email protected]/16V_4

C116
[email protected]/16V_4

C728
C194
C58
C750
C718
C63
C56
C300
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

C746
C696
C684
C296
C716
C717
C268
C744
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4

+1.5V_GPU

+1.5V_GPU

C729
C60
C82
C743
C749
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6

Quanta Computer Inc.

C289
C134
C745
C685
C683
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6

PROJECT : ZQ5
Size

Document Number

Date:

Monday, July 12, 2010

Rev
1A

MEMORY 2 channel B
5

Sheet
1

24

of

45

CRT Switch

CRT

EV@ --> dGPU only

.1u/10V_4

F2
2

+5V_CRT

CRTVDD5
D33

16

+5V

SSM22LLPT

CN20
CRT

SMD1206P110TFT

iGPU
only

7
7
7
7
7
7
7

INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
INT_VSYNC
INT_HSYNC
INT_CRT_DDCDAT
INT_CRT_DDCCLK

INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
INT_VSYNC
INT_HSYNC
INT_CRT_DDCDAT
INT_CRT_DDCCLK

R424
R422
R423
R434
R435
R427
R428

VGA_RED
VGA_GRN
VGA_BLU
VSYNC
HSYNC
CRTDDATA
CRTDCLK

IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4

VGA_RED

L3

BK1608LL680_6

CRT_R1

VGA_GRN

L2

BK1608LL680_6

CRT_G1

VGA_BLU

L1

BK1608LL680_6

CRT_B1

REV:B
6/14

R4

R3

R2

C7

C6

C5

150/F_4

150/F_4

150/F_4

5p/50V_4

5p/50V_4

5p/50V_4

C1

C2

C3

5p/50V_4

5p/50V_4

5p/50V_4

6
1
7
2
8
3
9
4
10
5

11

CRT_11

12

DDCDAT_1

13

CRTHSYNC

14

CRTVSYNC

15

DDCCLK_1

T1

17

25

updatefootprint 4/19 ZQ2

C791

12/29 Modify

IV@ --> iGPU only

R553

4/16

dGPU
only

D32

35 CRT_SENSE#
19
19
19
19,23
19,23
19
19

EV_CRT_RED
EV_CRT_GRN
EV_CRT_BLU
EV_VSYNC
EV_HSYNC
EV_CRTDDAT
EV_CRTDCLK

EV_CRT_RED
EV_CRT_GRN
EV_CRT_BLU
EV_VSYNC
EV_HSYNC
EV_CRTDDAT
EV_CRTDCLK

R433
R431
R432
R455
R456
R436
R437

EV@0_4
EV@0_4
EV@0_4
EV@0_4
EV@0_4
EV@0_4
EV@0_4

VGA_RED
VGA_GRN
VGA_BLU
VSYNC
HSYNC
CRTDDATA
CRTDCLK

R1
C4

10K_4

+3V

BAS316

CRT_SEN#

*0_4
2.2u/6.3V_6

4/14 Modify

+3V
C8

U33
CRTVDD5

CRT_BYP

7
8

.1u/10V_4
C786

0.22u/25V_6
2

+3V

VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO SYNC_IN1

16
14

CRT_VSYNC2
CRT_HSYNC2

15
13

R11
R14

VSYNC
HSYNC

CRT_R1
CRT_G1
CRT_B1

.1u/10V_4

3
4
5
6

VIDEO_1
VIDEO_2
VIDEO_3

DDC_IN1
DDC_IN2
DDC_OUT1
DDC_OUT2

GND

10
11

CRTDCLK
CRTDDATA

9
12

DDCCLK_1
DDCDAT_1

R21
R22

+3V

2.7K_4
2.7K_4

*.1u/10V_4

CRTVDD5

C11

*10p/50V_4

CRTVSYNC

C15

*10p/50V_4

CRTHSYNC

C774

10p/50V_4

DDCCLK_1

C777

10p/50V_4

DDCDAT_1

C779

CRTVDD5

REV:B
6/14

C9

CRTVSYNC
CRTHSYNC

15_4
15_4

R545

R547

2.7K_4

2.7K_4

CM2009-02QR

LCD_ON (LCD Power)

LVDS

5/11 Swap net

iGPU only

+3V

INVCC0
+3V

Stuff R713 on 2 CH.

+5V

Stuff R712 on 1 CH.

RN22
RN23
RN7

IV@0_4P2R
IV@0_4P2R
IV@0_4P2R
IV@0_4P2R
IV@0_4P2R

TXLCLKOUTTXLCLKOUT+
TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+
TXLOUT2TXLOUT2+
LCD_EDIDDATA
LCD_EDIDCLK

C725

C724

C121

C167

R147

.1u/10V_4

1000p/50V_4

4.7u/25V_8

1000p/50V_4

R152
4/20 Modify

0_6

R98

LCDVCC

*0_8

C302

LCDVCC_R

LVDS_VDDEN

C231

RN28
RN25

5/11 Swap net

RN26
RN27
RN6

2
4
4
2
4
2
4
2
4
2

EV@0_4P2R
EV@0_4P2R
EV@0_4P2R
EV@0_4P2R
EV@0_4P2R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

+3V

TXLCLKOUTTXLCLKOUT+
TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+
TXLOUT2TXLOUT2+
LCD_EDIDDATA
LCD_EDIDCLK

LCDVCC_L

R515
R510

2.2K_4
2.2K_4

LCD_EDIDCLK
LCD_EDIDDATA
TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+

4/29 Modify it
C

TXLOUT2TXLOUT2+
TXLCLKOUTTXLCLKOUT+
USBP11-_R
USBP11+_R
CCD_PWR

Brightness
LVDS_BRIGHT L55

VIN

35

CONTRAST

C174

C201

C202

C175

*.1u/10V_4

*2.2u/10V_8

.1u/10V_4

0.01U/25V_4

22u/6.3V_8

*0_8
*0_8

INVCC0

R453

IV@0_4

R72
R71

R452

EV@0_4

C115

C177

*1000p/50V_4

*1000p/50V_4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Item

7 INT_LVDS_DIGON

R117

EV@0_4

R116

IV@0_4

LVDS_VDDEN

QCI P/N

AAT

AL004280001

GMT

AL005243001

Backlight Control

+3V
34
33
32
31

34
33
32

R191

31

R167

10K_4
BL_ON

10K_4

LVDS

D10

1 BAS316

LID591#

14,35

7 L_BKLT_CTRL

LVDS_BRIGHT_R
BL_ON
SBY100505T-121Y-N

2A

LVDS_BRIGHT

*EV@0_4

C254
5

GND

BL#

5/21 change Connector

3

19 EV_LVDS_BRIGHT

R454

LCDVCC

100K_4

19 EV_LVDS_VDDEN

CN14
1
3
3
1
3
1
3
1
3
1

ON/OFF

*1000p/50V_4

INVCC0
EV_TXLCLKOUTEV_TXLCLKOUT+
EV_TXLOUT0EV_TXLOUT0+
EV_TXLOUT1EV_TXLOUT1+
EV_TXLOUT2EV_TXLOUT2+
EV_LVDS_DDCDAT
EV_LVDS_DDCCLK

GND

R130

5/5 Add

EV_TXLCLKOUTEV_TXLCLKOUT+
EV_TXLOUT0EV_TXLOUT0+
EV_TXLOUT1EV_TXLOUT1+
EV_TXLOUT2EV_TXLOUT2+
EV_LVDS_DDCDAT
EV_LVDS_DDCCLK

OUT

IN

AAT4280-4

C250

*1000p/50V_4

19
19
19
19
19
19
19
19
19
19

IN

1U/6.3V_4

5/6 Modify

4/29 Modify it

dGPU only

U8

*0_1206

LVDS_BLON
R168

+3V

R146

EC_FPBACK#

35

Q10
DTC144EU

Q8
2N7002D
1

100K_4

CCD

2
Q9
2N7002D
1

RN21

4
2
2
4
2
4
2
4
2
4

INT_TXLCLKOUTINT_TXLCLKOUT+
INT_TXLOUT0INT_TXLOUT0+
INT_TXLOUT1INT_TXLOUT1+
INT_TXLOUT2INT_TXLOUT2+
INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK

3
1
1
3
1
3
1
3
1
3

RN24

7
7
7
7
7
7
7
7
7
7

INT_TXLCLKOUTINT_TXLCLKOUT+
INT_TXLOUT0INT_TXLOUT0+
INT_TXLOUT1INT_TXLOUT1+
INT_TXLOUT2INT_TXLOUT2+
INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK

CCD_PWR

*0_8

C274

C700

*1000p/50V_4

*1000p/50V_4

5/6 Modfiy

Lid Switch (HSR)

+3VPCU
+3VPCU
C342

Close to USB

R193

1u/10V_4

RN8

*470K_4
2

PT3661-BB (PLC) : AL003661003

ME268-002 (FCE) : AL000268000

13
13

HE1
PT3661-BB
SOT23_123-2_8-1_9

0_4P2R
4
2

3
1

USBP11USBP11+

19 EV_LVDS_BLON
USBP11-_R
USBP11+_R

7 INT_LVDS_BLON

R174

EV@0_4

R177

IV@0_4

LVDS_BLON

L17
4
1

LID591#

4
1

3
2

3
2

*DLW21HN900SQ2L

5/24 Modify it

4/22 add it

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

CRT/LVDS/CAMERA/LID
Date:
1

Monday, July 12, 2010

Sheet 25
8

of

43

iGPU HDMI LEVEL SHIFTER

IV@ --> iGPU only

R26

+3V

*[email protected]_4
DDCBUF_EN
CFG

EV@ --> dGPU only

REV:B
6/15

C16

C19

[email protected]/10V_4

[email protected]/10V_4

[email protected]/10V_4

+3V

HDMITX2_P
HDMITX2_N
HDMITX1_P
HDMITX1_N

close to pin2/11/15/21/26/33/40/46
+3V

+3V

C43

[email protected]/10V_4

[email protected]/10V_4

For PS8101T

R27
R28

[email protected]_4
*[email protected]_4

PC0

+3V

R24

[email protected]_4

PC1

R25

[email protected]_4
*[email protected]_4

R34
R42

*[email protected]_4
*[email protected]_4

3
2

HDMI_HPD_EC#

35 HDMI_HPD_EC#

24
23
22
21
20
19
18
17
16
15
14
13

Q28
EV@2N7002D

MB_HDMITX0P
MB_HDMITX0N
2

HDMI_MB_HP

+3V

MB_HDMITX2P
MB_HDMITX2N
MB_HDMITX1P
MB_HDMITX1N

+3V

+5V

R550

Q29
2N7002D

*10K_4

MB_HDMICLK+
MB_HDMICLK-

SDVO I2C Control

IV@PS8101T

5/7 Modify part number

+3V

MB_HDMITX2P
R7

*IV@100/F_4

SP@499/F_4
MB_HDMITX2N

Control by pin4 HPDEN_R

MB_HDMITX1P
HDMI_HP_IV#

R32
R30

REV:B
6/15

GND
OUT_D1OUT_D1+
VCC
OUT_D2OUT_D2+
GND
OUT_D3OUT_D3+
VCC
OUT_D4OUT_D4+

PC0
PC1

from MCH

+3V

To dGPU HPD
HDMI_HP_EV 19

R15
10K_4

4/20 Modify

36
35
34
33
32
31
30
29
28
27
26
25
GND
IN_D1IN_D1+
VCC
IN_D2IN_D2+
GND
IN_D3IN_D3+
VCC
IN_D4IN_D4+
GND

LS_REXT

C42

[email protected]/10V_4

37
38
39
40
41
42
43
44
45
46
47
48
49

1
2
3
4
5
6
7
8
9
10
11
12

HDMICLK_P
HDMICLK_N
C780

R542
EV@10K_4

C27

[email protected]/10V_4

+3V

OE# control for

power saving

C26

[email protected]/6.3V_6

26

+3V

+3V

GND
CCT2
CCT1
VCC
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
OE#

HDMITX0_P
HDMITX0_N
C771

+3V

GND
VCC
TRIM
HPDEN
GND
REXT
HPD_S
SDA_S
SCL_S
NC
VCC
GND

from MCH 4/20

+3V

Active Buffer
U1

HDMI_MB_HP
MB_HDMI_DDCDATA
MB_HDMI_DDCCLK
HDMI_HPD_EC#

R23

IV@0_4

INT_HDMI_HPD

DDCBUF_EN

R6

*IV@100/F_4

+5V
MB_HDMITX1N

CFG

6 SDVO_CTRLDATA

SDVO_CTRLDATA

R19

IV@0_4

HDMI_DDCDATA_SW

SDVO_CTRLCLK

R20

IV@0_4

HDMI_DDCCLK_SW
R8

1
RB501V-40

SDVO I2C
CSP@ HDMI
For IV: 2.2K ohm

MB_HDMITX0P

6 SDVO_CTRLCLK

D29 2

5/24 Add it

*IV@100/F_4

R536
2.2K_4

For ES:4.7K ohm

Q23
EV@BSN20

MB_HDMITX0N

L
H
L
H

8dB
4dB
12dB
0dB

+3V

5/7 Add

HP-detect for
PS8101 only

*IV@100/F_4

R532
*IV@20K/F_6
HDMI_HP_IV#

SP@SN75DP139
1.Pin34 HPDINV for 8101T Stuff R32
2.Stuff R24
3.R25 change 3.9K (CS23902FB14)

19 MXM_DDCCK_C

MB_HDMICLK+
R5

R568
EV@10K_4

MXM_DDCCK

R535

R92

*short0402

PEG_RXP3

R569
EV@10K_4

PEG_RXP3 7,18

Item
R533
*[email protected]/F_4

+5V

D30 2

R548

*SHORT_6 HDMI_DDCCLK_MB

1
RB501V-40

C787
*.1u/10V_4
R537
2.2K_4

For ES:4.7K ohm

QCI P/N
1

PS8101TQFN48GTR

AL008101001

PS8101QFN48GTR

AL008101000

SN75DP139RGZR

AL000139000

MXM_DDCDAT

R538

EV@0_4 MB_HDMI_DDCDATA

R549

*SHORT_6 HDMI_DDCDATA_MB

Q24
EV@BSN20

C788
*.1u/10V_4

Q26
*IV@DMN601K-7

EV@0_4 MB_HDMI_DDCCLK

SDVO I2C
CSP@ HDMI
For IV: 2.2K ohm

+3V

19 MXM_DDCDAT_C
INT_HDMI_HPD

MB_HDMICLK-

L
L
H
H

PC0
internal PD
PC1
internal PD
DDCBUF_EN
internal PD
CFG
internal PD
DDC_EN
internal PU

PC1 PC0
PIN4 PIN3 EQ Control

Equalization Control

GPU Switchable Graphic HDMI source

updatefootprint 4/19 ZQ2

HDMI connector
Close to HDMI connector
6/15 Swap

From Discrete
To Discrete

19
19

HDMITX0N
HDMITX0P

19
19

HDMITX1N
HDMITX1P

19
19

HDMITX2N
HDMITX2P

19
19
R563
R564
R560
R559
R562
R561
R557
R558

MB_HDMITX0N
MB_HDMITX0P
MB_HDMITX1P
MB_HDMITX1N
MB_HDMITX2N
MB_HDMITX2P
MB_HDMICLKMB_HDMICLK+

7,18 PEG_TXP2
7,18 PEG_TXN2
7,18 PEG_TXP1
7,18 PEG_TXN1
7,18 PEG_TXP0
7,18 PEG_TXN0

Q1

7,18 PEG_TXP3
7,18 PEG_TXN3

+5V

HDMICLKHDMICLK+

1
3

2 EV@0_4P2R
4

MB_HDMITX0N
MB_HDMITX0P

RN34

1
3

2 EV@0_4P2R
4

MB_HDMITX1N
MB_HDMITX1P

RN35

1
3

2 EV@0_4P2R
4

MB_HDMITX2N
MB_HDMITX2P

RN33

1
3

2 EV@0_4P2R
4

MB_HDMICLKMB_HDMICLK+

MB_HDMITX2P
MB_HDMITX2N
MB_HDMITX1P
MB_HDMITX1N
MB_HDMITX0P
MB_HDMITX0N
MB_HDMICLK+

12/29 Modify

MB_HDMICLK-

+5V

From GMCH (iHDMI)

EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4

1/11 Add C928 by EMI.

CN21

RN36

PEG_TXP2
PEG_TXN2

RN5

1
3

2 IV@0_4P2R
4

HDMITX0_P
HDMITX0_N

PEG_TXP1
PEG_TXN1

RN3

1
3

2 IV@0_4P2R
4

HDMITX1_P
HDMITX1_N

PEG_TXP0
PEG_TXN0

RN4

1
3

2 IV@0_4P2R
4

HDMITX2_P
HDMITX2_N

PEG_TXP3
PEG_TXN3

RN2

1
3

2 IV@0_4P2R
4

HDMICLK_P
HDMICLK_N

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

F1
1

+5V_HDMI_D D1

SSM22LLPT

SMD1206P110TFT

+5V_HDMI
HP_DET

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

SHELL1
D2+ SHELL3
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL4
SHELL2

20
22
+3V

C781
2200p/50V_4

23
21

QJ1119C-NK01-8F
HDMI_MB_HP

R565

*SHORT_4

R556
100K_4

EV@2N7002D
1

R10
EV@100K_4

352-(&7=4
4XDQWD&RPSXWHU,QF

5/11 Swap

4/29 Modify

Close to NB couple cap & PCIE RESARRAY

Size

Document Number

Date:

Monday, July 12, 2010

Rev
1A

HDMI (PS8101)
5

Sheet 26

of

43

SATA HDD(HDD)

SATA ODD(ODD)

27

CN6

GND23
GND1
RXP
RXN
GND2
TXN
TXP
GND3

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
GND24

23
1
2
3
4
5
6
7

SATA_TXP0 12
SATA_TXN0 12
SATA_RXN0_C
SATA_RXP0_C

C508
C513

0.01u/16V_4
0.01u/16V_4

SATA_RXN0 12
SATA_RXP0 12

CN5

14

GND14

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

For ESD
U13
*CM1293A-04SO

SATA_TXN0

120mil

+5V

SATA_TXP0

CH1

CH4

VN
CH2

VP
CH3

SATA_RXN0_C

5
4

+5V

+3V
C354

C314

*4.7u/6.3V_6

*4.7u/6.3V_6

*0.1u/16V_4

SATA_RXN1_C
SATA_RXP1_C

SATA_DP

C529
C525

R305

0.01u/16V_4
0.01u/16V_4

U14
*CM1293A-04SO
SATA_RXP1_C

1
2

C18534-11305-L

SATA_RXN1_C

CH1

CH4

VN

VP

CH2

5/4 change footprint (ZQ2)

CH3

35

LED1

SUSLED#
PWRLED#

R212

330_4

R215

330_4

+5V

SATA_TXN1

C512

C511

C510

C509

4.7u/6.3V_6

0.1u/16V_4

0.1u/16V_4

0.01u/16V_4

0.01u/16V_4

C514

C526

+3V_S5

4/22 modify

Battery LED

LED2
35

BATLED1#

35

BATLED0#

R220

330_4

R232

330_4

120mil

+5V

Power LED

LED_A/B

SATA_TXP1

LED_A/B

+5V
C506

Power/Suspend: Green/Amber

LED(UIF)
35

For ESD

SATA_HDD
C

5/5 Modify

SATA_RXN1 12
SATA_RXP1 12

*1K_4

+5V

15

GND15

24

SATA_TXP1 12
SATA_TXN1 12

8
9
10
11
12
13

DP
+5V
+5V
RSVD
GND
GND

SATA_RXP0_C

C499

1
2
3
4
5
6
7

GND1
RXP
RXN
GND2
TXN
TXP
GND3

5/11 Modify

C527

C528

C524

C523

C522

10u/6.3V_8

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

28

D15

WLAN_LED#

+3VPCU

R226

*1M_6

R229

*1M_6

AMBER

R249

4/28 Add WiFi LED

4/29 change to amber

182/F_4

4/28 DEL CAPS and NUM LED

EV@100u/6.3V_3528

R243
10K_4

Bule

5/12 UMA no stuff

U9
TC7SH08FU

Bule

SATA_LED#_R

182/F_4

R61

182/F_4

D1 Power LED near PW SW

2
3

SATA_LED#

R246

DEL D2 4/29
D8

4
12

+3V
SATA_LED#_R D13

+3V

5/12 UMA no stuff

EV@100u/6.3V_3528

Modify it 4/26
R244

*0_4

FAN(THM)

25mil

TP CONN
+3V

R405

*0805

35

3 THER_OVERT#
35 PWM_FAN1

PWM_FAN1 R402

0_4

4.7K_4

L40
L41

TPDATA
TPCLK

VIN

VO
GND
FON# GND
GND
VSET GND

3
5
6
7
8

+5V

R301

+5V

0_6 TP_VCC

C515

BK1608LL121_6_150mA
BK1608LL121_6_150mA

0.1u/16V_4

CN4

TPDATA_R
TPCLK_R
C518

C520

10p/50V_4

10p/50V_4

TP_RIGHT#

FANSIG

30 MIL

U22

2.2u/6.3V_6

4.7K_4

R304

R399
10K_4

+5V

C630

35
35

R302

22u/6.3V_8

D11

2 *Uclamp0511P_4_ESD

TP_RIGHT#

D16

2 *Uclamp0511P_4_ESD

C636 C628
0.01u/16V_4
1000p/50V_4

1
2
3

13
14

Aces88501-120N

4
5

SW3

FAN

TP_RIGHT# 3
1

G991

change footpirnt as SA6

4/23

FANPWR = 1.6*VSET

TP_LEFT#

CN12

TH_FAN_POWER
C633

TP_LEFT#

1
2
3
4
5
6
7
8
9
10
11
12

SW2

2
4
5
6
MISAKI_SW_H1.5

TP_LEFT#

3
1

4/30 update footprint ZQ9

2
4
5
6

352-(&7=4
4XDQWD&RPSXWHU,QF

MISAKI_SW_H1.5
Size

Document Number

HDD/ODD/LED/SW/TP/FAN/MMB
Date:
5

Sheet 27

Monday, July 12, 2010

1

of

Rev
1A
43

MINI-CARD(MPC)

4/21 change footprint

Bluetooth
(BTM-3.0)

andy(ZYD) H=7.0

+3V
+3VSUS

CN15

13
PCIRST#
2 PCLK_DEBUG
+3V

R94

13
13
13
13

+3V_MINI_R_A

*0_6

TV use +3V

C176

*0.1u/16V_4

PCIE_TXP4
PCIE_TXN4
PCIE_RXP4
PCIE_RXN4

15
13
11
9
7
5
3
1
53

2 CLK_PCIE_MINI1
2 CLK_PCIE_MINI1#
2 MINI_CLKREQ#
+5V_TV-CARD

*0_6 +5V_TV-CARD_R_A
*0_6 +5V_TV-CARD_R_B

R520
R519

TV use +5V

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
Reserved
GND

GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
PAD53

PCIE_WAKE_WL_R_#

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V
PAD54

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

R276

35 BT_POWERON#

4.7u/6.3V_6

*short0402

CON5_BT_L

RN11
3
1

WLAN_LED# 27
13
13

USBP3+
USBP3-

3
2

16
14
12
10
8
6
4
2
54

Bluetooth
(BTM-2.1)

LFRAME# 12,35
LAD3
12,35
LAD2
12,35
LAD1
12,35
LAD0
12,35

+3V
+3VSUS

R572

7
6

*0_6

Q30

PLO

BT_POWER_1

AO3413

C792
4.7u/6.3V_6

BT_POWERON#

R573

*short0402

CON5_BT_L

Close to USB

For EMI

R89

13
13

RN37 1
3

USBP7+
USBP7-

2 0_4P2R
4
T151

1
4

*22_4

1
4

R99

7
6

Modify follow ZQ1 5/5

USBP7+_R
USBP7-_R
BT_LED_1

5
4
3
2
1

L69
2
3

2
3

5
4
3
2
1

7
6

7
6

CN22
C793
*0.01u/16V_4
B

*DLW21HN900SQ2L
Q4

4.7K_4

*DTC144EUA
1

PCIE_WAKE_WL_R_#

Modify 6/15
REV:B

R81
+3V
10K_4

P$PLO

2,14,16 PDAT_SMB

+1.5V

1
Q3
DMN601K-7

EXT. USB(USB)

MINI_SMDATA

+5VPCU

PLO

+5V_TV-CARD
R80
C712

C715

C149

C736

C531

10u/10V_8

C530

1u/10V_4

CN7
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

*0_4

C737
R79

*0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

4.7u/6.3V_6

+3V

4/22 add it

*4.7u/6.3V_6

1
Q2
DMN601K-7
R78

+3V

13

10K_4

2,14,16 PCLK_SMB

MINI_SMCLK

C738

C131

C740

C739

4.7u/6.3V_6

4.7u/6.3V_6

*4.7u/6.3V_6 *4.7u/6.3V_6

USBOC#6
USBP2-_R
USBP2+_R
USBP0-_R
USBP0+_R

*0_4

35

5
4
3
2
1

CN8
C532
*0.01u/16V_4

5/22 SWAP net

*10p/50V_4

*0_6

4
1

3
2

PLTRST# 13,31,33,35
RF_EN 35

RF_EN

+3VSUS

R508

USBP3+_R
USBP3-_R
BT_LED

*DLW21HN900SQ2L

PCLK_DEBUG

+5V

5
4
3
2
1

L35
4
1

MINI_SMDATA
MINI_SMCLK

C147

14,31 PCIE_WAKE#

0_4P2R
4
2
T85

USBP4+ 13
USBP4- 13

MINICARD_A

C480

Close to USB
WLAN_LED#

28

PLO

BT_POWER

AO3413

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

*0_6

Q14

+3V

+1.5V

R275

USBON#

18
17

USB_DBFFCCONN

C735

C741

C145

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

5/11 update footprint

Close to USB
13
13

USBPWRP1

13
13

0_4P2R
4
2

3
1

USBP6USBP6+

USBP6-_R
USBP6+_R

1
2
3
4

L4
4
1

4
1

3
2

3
2

5/22 SWAP net

0_4P2R
4
2

USBP2-_R
USBP2+_R

4
1

3
2

3
2

*DLW21HN900SQ2L

+ C775

CN18
1
2
3
4

4
1

USBPWR1
L5
TI201209G121_8_3A

Close to USB
RN1

RN13
3
1
L39

PLO

updatefootprint 4/19 ZQ2

INT. USB(USB)

USBP2USBP2+

USBP2USBP2+

8
7
6
5

8
7
6
5

100U/25V_6.3X5.8
+
C18
470p/50V_4
*100u/6.3V_3528
C10

USB_MB

C21

Close to USB

*470p/50V_4
13
13

USBP0USBP0+

USBP0USBP0+

RN12
1
3

0_4P2R
2
4

USBP0-_R
USBP0+_R

L38

*DLW21HN900SQ2L
1
4

QCI P/N

Item

5/22 SWAP net

1
4

2
3

2
3

*DLW21HN900SQ2L
D

AL000547000

GMT
+5VPCU
C17

10u/10V_8

C25

1u/10V_4
USBON#

2
3
4
1
9

PLO

U2
G547F2P81U
IN1
IN2

OUT3
OUT2
OUT1

EN#
GND
GND-C
13

OC#

8
7
6
5

USBOC#10

AL008015K00

ROH

USBPWR1

USBOC#10

R17

USBP6+

D4

1 *PESD5V0U1BL

USBP6-

D3

1 *PESD5V0U1BL

352-(&7=4
4XDQWD&RPSXWHU,QF

*6.34K/F_4
Size

Document Number

Add it 4/26

Rev
1A

MINI/USB/BT/HOLE
Date:

4/29 Modify it

Monday, July 12, 2010

7

Sheet

28
8

of

43

Codec(ADO)

HP

30

HP-R

MUTE(AMP)

30

HP-L

5/11 Modfiy it

30

HPOUT_JD

R50

29

+5VA

SENSEB
5.1K/F_4

C111

C128

C129

0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
INSPKR+

R530

36K/F_6

C86
4.7U/6.3V_6

0.47u/10V_6

R56

33K/F_6

FRONT-R+2

16

C48
+5VA

0.1u/10V_4 10u/6.3V_6

ADOGND

2.2u/6.3V_6 2.2u/6.3V_6

FRONT-R+1

BYPASS

LIN+

RVO1

RIN+

LINE2-L
Sense A

24

T3

23

SHDN#

36K/F_6
R85

+5V_S5

*100K_4

R86

REV:B
6/11 Modify

ADOGND

LVO1
LVO2

C81

4.7U/6.3V_6

12
9

ADOGND

INSPKR+

30

INSPKR-

30

1
4

*0_4

+5V_S5

ADOGND

MIC1-R

21

MIC1-L

MIC1-R

30

MIC1-L

30

MIC

35

AMP_MUTE#

T2

22

U6
4

EAPD#

20
19

MIC2-VREFO

R87

R84

TC7SH08FU

Vender

0_4

HP_MUTE# 30

C154

*0_4

*4.7u/10V_6

QCI P/N

18
17

MIC2_INT_R

C40

1U-16V_6

16

MIC2_INT_L

C39

1U-16V_6

MIC2_INTL1_R R41

1K_4

MIC2_INTL1

GMT

AL001453000

GMT

AL001465000

15
14
13

PCBEEP

Split by DGND

R57

RVO2

SENSEA

20K/F_4 MIC1_JD

R39

MIC1_JD

30

ANALOG

12

DVDD1

SPDIFO1

LINE2-R

RESET#

EAPD

10u/6.3V_6

26

25
AVDD1

27
VREF

AVSS1

MIC1-VREFO

30

28

29
CBP

CBN

32

31
CPVEE

HPOUT-R

34

35

33
HPOUT-L

Sense B

FRONT-R

MIC2-L

DMIC-CLK1/2

SYNC

48
EAPD#

MIC2-R

SPDIFO2

DVDD-IO

47

Split by DGND

DMIC-CLK3/4

11

46

MIC2-VREFO
LINE1-VREFO

10

45

NC

SDATA-IN

DIGITAL

ALC272X<LQFP-48>

AVSS2

DVSS2

44

43

T4

ANALOG

LINE2-VREFO

ADOGND

ADOGND

Place next to pin 38

MIC1-L

SURR-R

BIT-CLK

42

JDREF

SDATA-OUT

41

40

20K/F_4

MIC1-R

DVSS1

R53

LINE1-R
LINE1-L

ADOGND

C41

0.1u/10V_4

G1453L

SURR-L

DMIC-3/4/GPIO1

C74
C76
10u/6.3V_6 0.1u/10V_4

C44

INSPKR-

AVDD2

39

DMIC-1/2/GPIO0

38

+5VA

MONO-OUT

37

MONO-OUT

FRONT-L

36

14
U3

RIN-

Place next to pin 25

5/10 Add

13

LIN-

NC

C69

NC

FRONT-R-2

VSS

33K/F_6

VCC

R55

VCC

*0.47u/10V_6 FRONT-R-1

10

C50

ADOGND

C68

VSS

C52
+

FRONT-L

0.47u/10V_6

FRONT-L

C55

Speaker

15

MONO-OUT C747

THERMALPAD

5/11 Del FRONT-R

17

Place next to pin 27

FRONT-L= (L+R)/2

U5

11

ADOGND

REV:B
6/11 Modify

MIC1-VREFO 30
ADOGND

DIGITAL
1.6Vrms
+3V

PCBEEP
C75

C38

C64

1u/10V_6 BEEP_1

R43

C32

10u/6.3V_6 0.1u/10V_4

100p/50V_4

47K/F_4

PCSPK

14

R40
4.7K_4

REV:B
6/11
R570

IV@0_6 +1.5V

R47

EV@0_6 +3V

Place next to pin 1

ACZ_RST#_AUDIO 12

ACZ_SYNC_AUDIO
C51

12

*22p/50V_4

C59

22_4

C53

0.1u/10V_4

10u/6.3V_6

*100p/50V_4

4/29 Add it
ACZ_SDIN0_R R49

C54
C49

Place next to pin 9

ACZ_SDIN0 12
ACZ_SDOUT_AUDIO

12

ACZ_BITCLK_AUDIO

12

22p/50V_4

5/6 modify

Power (ADO)
DIGITAL
+5V

INT MIC 5/7 update the footprint name

ANALOG

L62

UPB201209T-310Y-N/6A/31ohm_8

R31
R54
R74
R88
R534
R16
R82
R531
C13
C34

+5VA
U29
3
2
A

IN

OUT

GND
SHDN

SET

R527

*29.4K/F_4

*G923-330T1UF
R526
*10K/F_4
C730

C734

C732

10u/10V_3216

0.1u/10V_4

1
2

R77
1
2

INT_MIC

MIC2-VREFO
2.2K_4

*22P_4
A

5/26 update Mic Partnumber

ADOGND
R83

MIC2_INTL1
C132

ADOGND

C727
+

0.1u/10V_4

CN1

*0_6
*0_6
*0_6
*0_6
*0_6
*0_6
0_6
0_6
*1000p/50V_4
*1000p/50V_4

C73

0.1u/10V_4

352-(&7=4
4XDQWD&RPSXWHU,QF

**0_4

Tied at one point only under

the codec or near the codec

10u/10V_3216
ADOGND

ADOGND
Size
ADOGND

cap place close to MIC-connector

C730, C787 close U37 pin3 and L65

5

Document Number

Rev
1A

REALTEK ALC663&888/MDC
Date:
2

Monday, July 12, 2010

1

Sheet 29

of

43

MIC
29 MIC1-VREFO

D2

BAS316

D5

BAS316

30

4/21
change footprint (ZQ2)

Internal Speaker
Normal OPEN Jack
R29
4.7K/F_4

R543
4.7K/F_4

PINK
D

29
29

C30

MIC1-L

C768

MIC1-R

4.7u/6.3V_6
4.7u/6.3V_6

MIC1_L2

R33

MIC1_R2

R541

MIC1_L3

1K/F_4

MIC1_R3

1K/F_4
29

L7
BLM15AG121SS1/0.5A/120ohm_4
L67
BLM15AG121SS1/0.5A/120ohm_4

1 CN17
2
6
3
4

MIC1_L
MIC1_R
MIC1_JD

SPEAKER-CONN

29
29

R387
R386

INSPKRINSPKR+

R_SPK-_1
R_SPK+_1

0_6
0_6

8
5
JAS7331-P30H9-7F

MIC1_JD
C776
470p/50V_4

Max. 100mVrms input for Mic-IN

2
1

CN11

C33
470p/50V_4

MIC1_JD

2
1

C607
C608
*0.22u/25V_6 *0.22u/25V_6

5/5 Modify

Modify it 5/4

ADOGND
ADOGND

D31
*VPORT_6

ADOGND
C

HP_MUTE#

2N7002K
29
56/F_4
56/F_4

HPL-1
HPR-1

BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS
BLM15AG121SS1/0.5A/120ohm_4
HPR_SYS
29
HPOUT_JD
C65
C45

L11
L9

R44

R52

*1K_4

*1K_4

HPOUT_JD

Q25

HP-L-2

7
R48

*0_6

8
5
JAS7331-P30H9-7F

2200p/50V_4 2200p/50V_4

HP_MUTE#
2N7002K

ADOGND
ADOGND

Normal OPEN Jack

29

HP-R

HP-L-2 R51
HP-R-2 R45

1 CN16
2
6
3
4

HP-L

29

HP/SPDIF

Q27

HP-R-2
B

R46

4/29 Modify

*0_6

6/18 change it andy

REV:B

HPOUT_JD

D6
2

*VPORT_6

352-(&7=4
4XDQWD&RPSXWHU,QF

ADOGND

Size

Document Number

Rev
1A

AMP /AUDIO JACK CONN

Date:
5

Monday, July 12, 2010

Sheet
1

30

of

43

31

Giga-LAN BCM57780
+3V_S5
U32

15mil
42

+3V_S5

6
15
41

VAUX_12
D

L6

15mil

VAUX_12

C22
C28

BLM18AG601SN1D_6

AVDDL
4.7U/6.3V_6
0.1u/10V_4_X7R

27
33
39

VDDO

BIASVDDH

VDDC
VDDC
VDDC

XTALVDDH

AVDDL
AVDDL
AVDDL

AVDDH

BCM57780
7mm X 7mm

AVDDH

25

BIASVDD
C764

L65
BLM18AG601SN1D_6
0.1u/10V_4_X7R

14

XTALVDD
C761

L64
BLM18AG601SN1D_6
0.1u/10V_4_X7R

30

AVDDH

L68

36

C784

48-Pin QFN
L63

15mil
C760
C763

BLM18AG601SN1D_6
L8

GPHY_PLLVDD
4.7U/6.3V_6
0.1u/10V_4_X7R

15mil

BLM18AG601SN1D_6

C36
C37

PCIE_PLLVDD

4.7U/6.3V_6
0.1u/10V_4_X7R

24

18
21

GPHY_PLLVDDL

TRD2_N
TRD2_P
PCIE_PLLVDDL
TRD1_N
TRD1_P
PCIE_PLLVDDL
TRD0_N
TRD0_P

C762
C759

13
GLAN_RXP
13
GLAN_RXN
13
GLAN_TXP
13
GLAN_TXN
14,28 PCIE_WAKE#
13,28,33,35 PLTRST#
2 CLK_PCIE_LAN
2 CLK_PCIE_LAN#

0.1u/10V_4_X7R PCIE_RXP1_LAN_R
0.1u/10V_4_X7R PCIE_RXN1_LAN_R

17
16
22
23
4
2
20
19

LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#
PCIE_TXDP
PCIE_TXDN
PCIE_RXDP
PCIE_RXDN
WAKE#
PERST#
PCIE_REFCLK_P
PCIE_REFCLK_N

MODE

+3V

VMA_PRES
LOW_PWR

1K/F_4
4.7K_4

40
1

EEDATA

SR_LX
SR_VFB
R539

200_4

XTALO
XTALI

13
12

R540

1.24K/F_4

RDAC

26

27p/50V_4

1.2H

Y6
25MHz

35
34
31
32
29
28

32
32

LAN_TRD2N
LAN_TRD2P

32
32

LAN_TRD1N
LAN_TRD1P

32
32

LAN_TRD0N
LAN_TRD0P

32
32

48
47
46
45

LAN_LINKLED#

LAN_LINKLED#

LAN_ACTLED#

LAN_ACTLED#

32
32

44

BCM_EEC

43

BCM_EED
VAUX_12

XTALO
XTALI

SR_VDDP
SR_VDD

11
8

L66

10
9

4.7uh

Don't route under Choke.

+3V_S5
C12

RDAC

4.7U/6.3V_6

2
C758

0.1u/10V_4_X7R

LAN_TRD3N
LAN_TRD3P

VMAIN_PRSNT
LOW_PWR

5/19 Modify
C757

37
38

EECLK
R13
R551

0.1u/10V_4_X7R

C24
TRD3_N
TRD3_P

BLM18AG601SN1D_6

C20

C47
10u/6.3V_6
0.1u/10V_4_X7R
C46

0.1u/10V_4_X7R

27p/50V_4
+3V_S5
R546

R544

*4.7K_4

CLK_REQ#

NC

0_4 BCM_CLKREQ#

49

GND

2 LAN_CLKREQ#

BCM57780

EEPROM

LAN POWER
+3V_S5

C785
C766

REV:B
6/11

+3V_S5

20mil

VAUX_12
4.7U/6.3V_6
0.1u/10V_4_X7R

C31

R567
*1K_4

4.7U/6.3V_6

C35

0.1u/10V_4_X7R

C23

0.1u/10V_4_X7R

C769

0.1u/10V_4_X7R

R566
1K_4

U34
5
6

BCM_EED
BCM_EEC

7
R555
1K_4

R554
*1K_4

SDA
SCL

A0
A1
A2

1
2
3

WP
GND
*AT24C02

VCC

+3V_S5
C790
0.1u/10V_4_X7R

EEPROM Strapping
EEPROM Type

EECLK EEDATA

24LC02

Internal

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

GLAN BCM57780
Date:
5

Monday, July 12, 2010

1

Sheet 31

of

43

32

4/27 modify it

TRANSFORMER

U31

C753

C754

0.1u/10V_4_X7R

0.1u/10V_4_X7R

C755

C756

0.1u/10V_4_X7R

0.1u/10V_4_X7R

31
31

LAN_TRD0P
LAN_TRD0N

31
31

LAN_TRD1P
LAN_TRD1N

31
31

LAN_TRD2P
LAN_TRD2N

31
31

LAN_TRD3P
LAN_TRD3N

LAN_TRD0P
LAN_TRD0N

1
2
3

LAN_TRD1P
LAN_TRD1N

4
5
6

LAN_TRD2P
LAN_TRD2N

7
8
9

LAN_TRD3P
LAN_TRD3N

10
11
12

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

24
23
22

X-TX0P
X-TX0N

21
20
19

X-TX1P
X-TX1N

18
17
16

X-TX2P
X-TX2N

15
14
13

X-TX3P
X-TX3N

TRANSFORMER
R35
75/F_8

R36
75/F_8

R37
75/F_8

R38
75/F_8

4/21 change Part number

DB0Z06LAN00 (follow Z08)
C29
1500p/3KV_18
B

For EMI

RJ45 Conn

CN19
C

31 LAN_ACTLED#
+3V_S5

31 LAN_LINKLED#
+3V_S5

R18

R552

220_8

220_8

LAN_ACTLED#
LAN_ACT_LED_PWR

9
10

X-TX0P
X-TX0N
X-TX1P
X-TX2P
X-TX2N
X-TX1N
X-TX3P
X-TX3N

1
2
3
4
5
6
7
8

LAN_LINKLED#
LAN_LNK_LED_PWR

11
12

YELLOW_N
YELLOW_P
0+
01+
2+
213+
3-

GND2
GND1

14
13

R9
R12

*0_6
*0_6

LAN_TRD0P

C765

*10p/50V_4

LAN_TRD0N

C767

*10p/50V_4

LAN_TRD1P

C772

*10p/50V_4

LAN_TRD1N

C770

*10p/50V_4

LAN_TRD2P

C773

*10p/50V_4

LAN_TRD2N

C778

*10p/50V_4

LAN_TRD3P

C782

*10p/50V_4

LAN_TRD3N

C783

*10p/50V_4

GREEN_N
GREEN_P
RJ45

LAN_ACTLED#
LAN_LINKLED#

C14

C789

*0.1u//50V_8

352-(&7=4
4XDQWD&RPSXWHU,QF

*0.1u//50V_8

Size

Document Number

Rev
1A

LAN Transformer and RJ45

Date:
1

Monday, July 12, 2010

7

Sheet 32
8

of

43

2 IN 1 CARD READER (SD/MMC)

CARD READER Controller

SD_WP

VCC_XD
SD_CMD
SD_DAT3
SD_DAT2

5/10 modify

4
13

SD-CARD

CD/SW

DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
DATA3
DATA2

GND1

SD_CLK

WP/SW
SW COM

GND

CN2
10
9
8
7
6
5
3
2
1

SD_DAT1
SD_DAT0

14

33

11
12

SD_CD#

5/10 Del R40001

VCC_XD
C284

C708 close PIN48, 47

XTALSEL

C682

0.1u/16V_4

0.1u/16V_4

U26

48
47
46
45
44
43
42
41
40
39
38
37

5/10 Modify
+3V_VDD

C686 *0.47u/10V_6
+3V

R514

0_6

+3V_VDD
C701
2

4.7u/10V_6

CLK_Card48
R502 330_4

13
13

USBP1+
USBP1C702

C704

*5p/50V_4

*5p/50V_4

Close to CN14 pin 14 & pin23

4.7u CAP close to pin23

XI
XO
+1.8V_VDD

1
2
3
4
5
6
7
8
9
10
11
12

8/14 C707 close PIN11, 12

CTRL0, CRTL 1 trace length shorter ,

and surround with GND.

VDDHM
GND
VDD
XTALSEL
TRIST
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6

13,28,31,35 PLTRST#

*100K_4

DFHS11FR033

0.1u/16V_4

5/10 change Card Redaer conn

footpirnt sdcard-sdsn09-08-xa-11p-smt

GPON7
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
VDD

36
35
34
33
32
31
30
29
28
27
26
25

CTRL0
CTRL2
GPI4

DATA0

SD_DAT0

DATA1

SD_DAT1

DATA2

SD_DAT2

DATA3

SD_DAT3

T142
DATA3
DATA2
GPI2
T147
EEPDATA
GPI1

T148
T149

Close to connector
2

13
14
15
16
17
18
19
20
21
22
23
24

AU6437-GBL

CTRL0
DATA5
CTRL2
GPI4
DATA4
DATA3
DATA2
XDWPN
GPI2
XDCEN
EEPDATA
GPI1

V18
CF_V33
VCC33
AGND5V
V33
VDDHM
GND
VDD
CTRL4
XDCDN
SDWPEN
EEPCLK

R500
0_4

Second
T137
T143

C681

8/14 ZH7 remove R136, R591 and C775

R501

DFHS11FR011

XTALSEL
CRMD_N
NBMD
CTRL1
CTRL3
DATA1
DATA0

+3V_VDD
*0_4

Main
C743 close PIN46, 47

+1.8V_VDD

R496

C277

4.7u/10V_6

Clock input selection

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input

crystal trace width needs at least 10 mils.

8/14 pin13 output 20mils

EEPCLK

*18p/50V_4

XI
4.7u/10V_6

C706

*18p/50V_4

CTRL0

R504
*270K_4
*0_4

VCC_XD

Y5
*12MHz

T150

VCC_XD

C705
C703

XO

+1.8V_VDD

4/20 Modify

+3V_VDD

+3V_VDD
C713

C714

4.7u/10V_6

0.1u/16V_4

R143
SD_CLK
BLM15AG121SS1/0.5A/120ohm_4

CTRL1

SD_WP

CTRL2

SD_CMD

CTRL3

SD_CD#

C270
*10p/50V_4

R513

SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

AU6433 CardReader
Date:
A

Monday, July 12, 2010

Sheet
E

33

of

43

34

(OTH)

HOLE13
*H-C315D118P2

HOLE4
*H-C315D118P2

HOLE10
*H-C315D118P2

HOLE7
*H-TC205BC276D146P2

HOLE6
*H-TC205BC276D146P2

HOLE9
*H-TC205BC276D146P2

5/25 Modify

HOLE3
*HG-C315D118P2
7
6
8
5
9
4

HOLE11
*HG-C315D118P2
7
6
8
5
9
4

HOLE2
*HG-C315D118P2
7
6
8
5
9
4

1
2
3

HOLE21
*HG-C315D118P2
7
6
8
5
9
4

1
2
3

HOLE1
*HG-C315D118P2
7
6
8
5
9
4

1
2
3

HOLE19
*HG-C315D118P2
7
6
8
5
9
4

1
2
3

HOLE20
*H-C315I178D118P2

HOLE5
*HG-C315D110P2
7
6
8
5
9
4

1
2
3

5/21 Modify

HOLE17
H-C197D87P2

1
2
3

HOLE8
H-C256D161P2

1
2
3

HOLE15
HG-C315D154P2
7
6
8
5
9
4
1
2
3

5/21 Modify

HOLE16
H-C256D161P2

HOLE12
H-C256D161P2

7/08 Modify for ESD issue.

7/08 Add for ME.

HOLE14
*H-C1417D1417N

HOLE18
*H-C315I178D118P2

HOLE22
*h-o94x134d94x134n

+3V_S5

+1.5V_SUS

C427

+1.05V

+VGPU_CORE

C503

*0.1u/10V_4

C368

*1000p/50V_4

C77

*1000p/50V_4

*1000p/50V_4

For EMI(EMI)
A

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

MINI/USB/BT/HOLE
Date:
5

Monday, July 12, 2010

Sheet
1

34

of

43

EC(KBC)

L37

BK1608HS220_6_1A

+3V

Modify on 9/15
+3VPCU

C502

C501

0.1u/16V_4

4.7u/10V_6

I/O ADDRESS SETTING

E775AGND

R293

2.2_6

D23

0.03A(30mils)

+3VPCU_EC

C497

4.7u_6

0.1u/16V_4

*0.1u/16V_4

0.1u/16V_4

*0.1u/16V_4

0.1u/16V_4

U12

C516

C521

4.7u_6

0.1u/16V_4

Modify to 1000P on 9/17

No stuff 1000P on 4/29

C504

VDD

C498

102

C519

AVCC

C505

VCC1
VCC2
VCC3
VCC4
VCC5

PCLK_591

C500

19
46
76
88
115

BAS316

E775AGND

R300

121

12

10K_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5

RCIN#

14 EC_SCI#
25 EC_FPBACK#
25

CRT_SENSE#

13,28,31,33

+3VPCU

28
14
CN3

28 1
27 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

29

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0

EC_FPBACK#

CRT_SENSE#

124

USBON#
SERIRQ

USBON#

123

IRQ_SERIRQ

125
9

14 KBSMI#

FFC_26P_KB

5/12 add GND pin

36
MBCLK
36
MBDATA
3
2ND_MBCLK
3 2ND_MBDATA

Modfiy 4/19

5/11 Swap

27
27

CP2
B

1
3
5
7

2
4
6
8

MY10
MY11
MY12
MY13

28 BT_POWERON#
21,38,40,42 MAINON
23 VGA_THERM#

14 ICH_SUSCLK

CP3

2
4
6
8

TPCLK
TPDATA

T78

*220PX4

1
3
5
7

PLTRST#

PLTRST#

R279

0_6

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

54
55
56
57
58
59
60
61

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

70
69
67
68

TPCLK
TPDATA
PCH_ACIN
VGA_THERM#

72
71
10
11
12
13

E775_32KX1

77

GPIO11/CLKRUN
GA20
KBRST

*20M_6

E775_32KX2

79

GPIO24/LDRQ
GPIO10/LPCPD
LREST
GPIO67/PWUREQ
SERIRQ
GPIO65/SMI

KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
GPIO25/PSCLK3
GPIO12/PSDAT3

2
4
6
8

Y1

MY4
MY5
MY6
MY7

PS/2

GPIO56/TA1
GPIO20/TA2
GPIO14/TB1

TIMER

SPI

C493
*15p_4

2
4
6
8

MX0
MX1
MX2
MX3

32KX2
WPCE781

*33K/F_4

GPIO72/IRRX1/SIN2
GPIO70/IRRX2_IRSL0
GPIO71/IRTX/SOUT2
GPIO87/CIRRXM/SIN_CR
GPIO34/CIRRXL
GPIO16/CIRTX
GPO83/SOUT_CR/BADDR1
F_SDI
F_SDO
F_CS0
F_SCK
GPIO55/CLKOUT

*32.768KHz

GPIO77/SPI_DI
GPO76/SPI_DO/SHBM
GPIO75/SPI_SCK

32KX1/32KCLKIN

L36

CP7

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO66/G_PWM

FIU

*220PX4

1
3
5
7

GPIO01/TB2
GPIO03/AD6
GPIO06
GPIO07/AD7
GPIO23/SCL3
GPIO30/CIRTX2
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO36/TB3
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/CIRRXM/TRST
GPO47/SCL4
GPIO50/TDO
GPIO51/TA3
GPIO52/CIRTX2/RDY
GPIO53/SDA4
GPIO81
GPO82/TRIS
GPO84/BADDR0
GPIO41

BK1608HS220_6_1A

C494
*15p_4

97
98
99
100
108
96
101
105
106
107
64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28
91
110
112
80

C495

*1000P_4 ICMNT

C496

0.01u/16V_4

VCC_POR
VREF

SHBM=0: Enable shared memory with host BIOS

WL_SW
TPD_TRIP

T62
T63

DIGVOL_UP
DIGVOL_DN

T65
T61

ICMNT

POWER_SAVE

T81

TP_LED#
TP_SW#

T64
T67

36

ACIN

Del

T70

36

SM BUS PU

LID591# 14,25
SUSB# 6,14
VGA_CLK 23

Change pull-up resistor (R148

/R154) from 10K to 4.7Kohm

ACPRN on 9/18

VGA_DATA 23
BATLED0# 27
BATLED1# 27
VR_ON 39
SUSLED# 27

VGPU_ON
T77
T75
T71

CPUFAN#

T73

4/21 add

R285
R280

4.7K_4
4.7K_4

Del VIN_ON on 4/19

C

+3V
26

T74

VGA_CLK
VGA_DATA

DNBSWON# 14
T69
T66
T58

RF_LED_EN#
3G_WKAE_2

2ND_MBCLK
2ND_MBDATA

4.7K_4
4.7K_4

4/22 DEL PWM

D/C#
36
S5_ON 37,44
HDMI_HPD_EC#

EC_ODD_EN

R281
R286

+3V

AMP_MUTE# 29

3G_SW

+3VPCU
MBCLK
MBDATA

4/20 Modify
VGPU_ON 21,41,43

3G_WKAE_1
VIN_ON

10K_4

1/13 Comfirm by vendor mail :

Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware

4/22 add

NBSWON#

ACPRN_ACLED

R289

SHBM_R

SHBM

Change Pin 98 to WL_SW

Pin99 for SML1ALERT#
on 9/10
PWM_FAN1 27

R297
R299

2.2K_4
2.2K_4
Modify on 4/19

Del DP_HPD_EC#

31
117
63
32
118
62
81
84
83
82

100K_4

RTC_EC

RTC_EC 12
SUSON 40,42
FANSIG 27
CONTRAST 25

NUMLED#

T80

CAPSLED#

T57

PWRLED# 27

ODD_EJ
SHBM_R
Back_SW

SPI FLASH

4/28 Modfiy it

SPI_SDI_uR R291

T59

R294

75
73
74
113
14
114
111

RSMRST#_uR

R288

*Short_4

PWROK_EC_uR

R287

*Short_4

86
87
90
92

SPI_SDI_uR
SPI_SDO_uR_R
SPI_CS0#_uR
SPI_SCK_uR_R

CIRR_X2
HWPG
P_SAVE_LED#

+3VPCU
U11

T60

22_4 SPI_SDI_uR_R

100K_4

SPI_SDI_uR pull-down 100Kohm at B-test

RSMRST# 14
SUSC# 6,14
PWROK_EC 14
RF_EN 28

+3VPCU

R292

10K_4

SPI_SDO_uR

SPI_SCK_uR

SPI_CS0#_uR

SO
SI

VDD
HOLD

SCK
CE

WP
VSS

8
7

C492

0.1u/16V_4

W25X16AVSSIG

T76
T68

R283

22_4

SPI_SDO_uR

R284

22_4

SPI_SCK_uR

30

ECDB_CLOCK

T72

85

VCC_POR#

R282

104

VREF_uR

R290

47K/F_4
*Short_4

1/13 Comfirm by vendor mail :

If the Southbridge enables 'Long Wait Abort' by
default, the flash device should be 50MHz (or faster)

At 11/24 add
Winbond W25X16AVSSIG
MXIC
MX25L1605DM2I-12G
AMIC
A25L016M-F

+3VPCU

SM Bus 1

R298
10K_4

42 HWPG_1.8V

Battery

38 HWPG_1.05V

SM Bus 2

PCH

SM Bus 3

VGA Thermal

6,40 HWPG_1.5V

1u_4

37 SYS_HWPG
43 PG_1.5V_EN

E775AGND

+3V

HWPG

C517

AKE38FP0N01
AKE38FP0Z00
AKE38ZN0800

+A3VPCU

SM BUS ARRANGEMENT TABLE

E775AGND

*220PX4

TEMP_MBAT 36

R303

SMB IR

5
18
45
78
89
116

R278
CP5

GPIO

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

*220PX4

1
3
5
7

LPC

ECSCI/GPIO54

MY8
MY9
R277

GPI94/DA0
GPI95/DA1
GPI96/DA2
GPI97/DA3

D/A

GND1
GND2
GND3
GND4
GND5
GND6

RP1
10
9
8
7
6

122

VCORF

CLKRUN#

12 GATEA20
+3VPCU

GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05/AD4
GPIO04/AD5

A/D

AGND

14

LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK

VCORF_uR 44

C507
*10p/50V_4

3
126
127
128
1
2

LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_591

LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_591

103

12,28
12,28
12,28
12,28
12,28
2

*22_4

28
27

35

+A3VPCU

30mil

MX4
MX5
MX6
MX7

SM Bus 4

Add

21 dGPU_PWROK

D22

BAS316

D21

BAS316

D20

HWPG
R295
*Short_4

BAS316

D19

BAS316

D17

EV@BAS316

D18

EV@BAS316

MPWROK 6,14

CP6

1
3
5
7

2
4
6
8

MX4
MX5
MX6
MX7

2
4
6
8

MY0
MY1
MY2
MY3

POWER-ON Switch

*220PX4

POWER-ON PAD(UIF)

POWER-Smart Key(UIF)

INTERNAL KEYBOARD STRIP SET

CP4

1
3
5
7

+3VPCU
SW1
MISAKI_SW_H1.5

CP1

2
4
6
8

D7
*VPORT_6

MY14
MY15
MY16
MY17

2
4
5
6

DEL it 5/5
1

2
Size

*SHORT_PAD

*220PX4

R296

10K_4

352-(&7=4
4XDQWD&RPSXWHU,QF

G1
NBSWON#

1
3
5
7

1
3

NBSWON#

*220PX4

MY0

Document Number

Rev
1A

WPCE81 & FLASH

Date:
5

Monday, July 12, 2010

1

Sheet 35

of

43

SP@POWER_JACK
dcjk-2dc2003-000111-3p-v
PJ2
1
2

VA1

EMI Add 4/26

PR16
0.01_3720

PD10
SBR1045SP5-13
1

PL12
HI0805R800R-00_8

VA

PQ56
FDD6685
3
4

VA2

Close to PR9002

VIN

36

PQ39
FDD6685
3

PC158

2200p/50V_6

PR19
220K_4

1
PR17
220K_4

Modfiy 4/28 andy

ZH9

Yellow

PC6
2200p/50V_6

PR40
33K/F_4

CSIP_1
D/C#

PR39
10K_4

35

PR14
*0/short_4

PQ5
IMD2AT108

CSIN_1
CSIP_1

QCI P/N

PQ15
DMN601K-7

EMI Add 4/22

Color

PC5
0.1u/50V_6

CSIN_1

*47u/25V_6.3*6
PD1
SW1010CPT

65W

PR21
SHORT_PAD_4

Add 5/14

PC166
0.1u/50V_6

Item

PR20
SHORT_PAD_4

PD11
SMAJ20A

VIN

DFPJ06MR012

PC101
0.1u/50V_6

27 CSIN

PC85
1u/16V_6

26

5
6
7
8
PD6
*RB500V-40

11
35

MBDATA

35

MBCLK

PR131
100K_4

35

10
13

ACIN
PR78
49.9/F_6

VDDSMB
SDA

UGATE

SCL

PHASE

ACOK

LGATE
PGND

22

88731ACSET

4/21
change footprint (ZQ3)

PL1
HI0805R800R-00_8

ACIN

CSOP

ICOMP
NC

BAT-V

C114F3-108A1-L_Batt_Conn
PL2
HI0805R800R-00_8

PR27
100_4

VCOMP

20

ISL88731_LGATE

BAT-V

PR81
*4.7_6

19
PQ26
AO4468

18 CSOP

CSOP_1
PC59
*680p/50V_6

CSOP_1

PC27
2200p/50V_6

BAT-V

PC119
10u/25V_1206
PC124
10u/25V_1206

17 CSON

BAT-V

Modify 6/18
B

PR86
10/F_4

16

NC

15
29

BAT-V
PR174
100_4

12

PR142
2.21K/F_4

14

TEMP_MBAT 35

PL4
6.8uH

GND

GND

PR28
100K_4

ISL88731_PHASE

0.01_3720
PR160

PQ25
AO4468

PR125
*0/short_4

VBF

NC

TEMP_MBAT

23

NC

ICM

10 1
2
3
4
5
6
7
9 8

ISL88731_UGATE

PC86
0.1u/50V_6

VREF

MBAT+

PU3
ISL88731A

CSON
4

24

PC74

*10u/25V_1206
PC64
*10u/25V_1206
10u/25V_1206
PC65
2200p/50V_6

PC58
0.1u/50V_8
88731B_1

PR87
10/F_4

PR150
22K/F_4

PR124
2.7_6
25 88731B_2

DCIN

PR149
82.5K/F_4

PC17
100p/50V_6

VDDP
BOOT

PC88
0.1u/50V_6
DCIN

PC18
0.1u/50V_6
2
1

VCC

PC100
0.1u/50V_6

CSSN

NC
GND
GND
GND
GND
CSSP

+3VPCU

+3VPCU

PC79

ISL88731_VDDP

21

1
33
32
31
30
28 CSIP

PR92
4.7_6

3
2
1

DFPJ06MR013

PC90
1u/16V_6

PR72
10/F_4

5
6
7
8

Blue

PR67
10/F_4

3
2
1

90W

PC12
0.1u/50V_6

PC165
0.1u/50V_6

PL13
HI0805R800R-00_8

PC168

7
6
5
4

+3VPCU

PJ1
PC20
47p/50V_6

PC19
47p/50V_6

PC110
0.01u/50V_6
ICMNT

PR26
*0/short_4

PR30
100_4

PR29
100_4

PC106
PC105
*1u/16V_6 0.01u/50V_6

ISL88731 thermal pad

tie to Pin12
ICMNT

35

PC104
*0.01u/50V_6

MBCLK
A

MBDATA
PU6
CM1293A-04SO

1
2
TEMP_MBAT

CH1
VN
CH2

CH4
VP
CH3

6
5
4

MBDATA

352-(&7=4
4XDQWD&RPSXWHU,QF

Modfiy 4/19 andy

+3VPCU
MBCLK
Size

Add ESD diode base on EC FAE suggestion

Date:
5

Document Number

Rev
1A

Charger(ISL88731A)
4

Sheet

Monday, July 12, 2010

1

36

of

43

SUSD
MAIND

SUSD

42

MAIND

40,42

37
VL
3,44 SYS_SHDN#

PR169
*0/short_4
VIN

PR156
39K/F_4

5.4A

PC117
0.1u/50V_6
PC116
0.01u/16V_4

+5VPCU

PC111
1u/16V_6
PC109
0.1u/50V_6
REF

8206_ONLDO

8
7
6
5
PC21
0.1u/50V_6

PQ13
AO4710

PR44
*0/short_4

PR164
1/F_6

3
2
1
PR57
220K/F_4
2

3V_LX

SKIP
DDPWRGD_R
3V_EN

PR140
*0_4

PC63
*680p/50V_6

Modify 6/18
PC108
0.1u/50V_6
PR152
1/F_6
2

PR91
*4.7_6

PD5
*SX34

REFIN2
1

5
6
7
8

32
31
30
29
28
27
26
25

PC95
0.1u/50V_6

PC84
330u/6.3V_6X5.7

PQ22
AO4710

1
PR146
1
PR147

+3VPCU_OUT

2
*0/short_4
2
*0_4

3V_DL

LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF

8
7
6
5
4
3
2
1

PC121
0.1u/50V_6

PC128
*680p/50V_6

1
2
3

PC23
*10u/25V_1206

PAD
PAD
PAD

PD2
*SX34

PL3
2.2uH_7X7X3

5V_DL

Change footprint 5/14

+3VPCU

REFIN2
ILIM2
OUT2
SKIP#
PGOOD2
EN2
DH2
LX2

PU4
RT8206B

PQ21
AO4468

3
2
1

BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD

17
18
19
20
21
22
23
24

PR175
*4.7_6

PR151
*0_6

BST1
DL1
PVCC
NC
GND
PGND
DL2
BST2

1
2
3

1
PR43
169K/F_4

5V_LX

8
7
6
5

+5VPCU
PR167
*0_4

9
10
11
12
DDPWRGD_R 13
5V_EN 14
15
16
37
36

+5VPCU

35
34
33

PR159
150K_4

5V_DH

PQ14
AO4468

Modify 6/18
PL8
2.2uH_7X7X3

+3VPCU

3V_DH

Change footprint 5/14

7A

PR148
*0_4

5
6
7
8

PR158
390K_4

PC53
10u/25V_1206

OCP:9A

PC25
10u/25V_1206

3V_EN

OCP:7A

PC127
*10u/25V_1206

5V_EN

PC26
2.2n/50V_6

PR143
*0/short_4

PC52
2.2n/50V_4

PR168
*0/short_4

PR157
*0/short_4
PR153
*0/short_4

PC94
100u/25V_6X7.7

PC122
4.7u/10V_8

2
3V5V_EN

VL

VIN

PR46
*0_6

+5VPCU_FB

2
PD3
CHN217

PR170
*0/short_6

PC112
1u/16V_6

SKIP

VL

PC43
0.1u/50V_6

PD4
CHN217

PC42
0.1u/50V_6

+15V_ALWP

+15V
PR80
22_8

Iocp=7-(2.525/2)=5.74A
Vth=5.74A*14.2mOhm=0.08147V
R(Ilim)=(81.47mV*10)/5uA=163K

2
+3VPCU

OCP:9A

L(ripple current)
=(9-3.3)*3.3/(2.2u*0.5M*9)=1.9A
Iocp=9-(1.9/2)=8.05A
Vth=8.05A*14.2mOhm=0.11431V
R(Ilim)=(114.31mV*10)/5uA=228.62K
I_peak(choke)=11.479A

2
1

L(ripple current)
=(9-5)*5/(2.2u*0.4M*9)
~2.525A

PR141
*0_4

PR50
*0/short_6

OCP:7A
B

REF

PR56
*0/short_4

1
PC48
0.1u/50V_6

2
PR55
*0_4

PC134
330u/6.3V_6X5.7

PR77
*200K/F_4

PR47
*39K/F_4

DDPWRGD_R

SYS_HWPG 35
PR145
*0/short_4

PC51
0.1u/50V_6

PR144
*100K/F_4

I_peak(choke)=11.187A

+3VPCU
VIN

+3V_S5

+15V

+5V_S5

VIN

+5VPCU

+5VPCU

+3VPCU

+3VPCU

PR32
1M_6

PR31
*1M_6

5
6
7
8

PR35
22_8

5
6
7
8

PR36
22_8

PR34
1M_6

5
6
7
8

Modfiy 4/19 andy

4

S5D

SUSD

MAIND

PQ42
AO4468

PQ28
AO4468

PQ9
DMN601K-7

PC22
*2.2n/50V_4

0.21A

+3VSUS

2.8A

352-(&7=4
4XDQWD&RPSXWHU,QF

+5V_S5
+5V

0.002A

PQ23
AO3404

3
2
1

+3V_S5

PQ11
DMN601K-7

PQ24
AO4468

PQ8
AO3404

3
2
1

PQ10
DMN601K-7

PR33
1M_6

PQ7
DTC144EU

S5_ON

MAIND 4

3
2
1

35,44

S5D

2.4A

+3V

4.01A

Size

Document Number

Rev
1A

SYSTEM 5V/3V (RT8206)

Date:
5

Monday, July 12, 2010

Sheet
1

37

of

43

38
[PWM]
VIN
+5V_S5

+1.05V
PR172
2.2/F_6

PD7
RB500V-40

PR42
1M/F_4

PC120
*0.1u/50V_6

1
2

PR162
*10K/F_4

3
4

35 HWPG_1.05V

6
5
14

EN/DEM
TON
VOUT
VDD
FB
PGOOD

PC125
0.1u/50V_6
BOOT
UGATE
PHASE
OC
VDDP
LGATE

GND

PGND

NC

TPAD

PQ40
AOL1448

PC129
2.2n/50V_4

PC130
10u/25V_1206

PC24
10u/25V_1206

13
*0/short_6
12

UGATE-1.05V

11

PHASE-1.05V

10
9

PL9
1uH

PR37
3.9K/F_4

16

PR171

PC126
1u/16V_6

LGATE-1.05V

PR177
*4.7_6

7
PQ41
AOL1718

17

1
2
3

15

1
2
3

PU5
UP6111AQDD

+3V

PC114
1u/16V_6

PC113
4.7u/6.3V_6

21,35,40,42 MAINON

PR161
10_6

PR38
*0/short_4

OCP:20A
16A

PC133
*680p/50V_6

NC

PC118
*1000p/50V_6

PC135
560u/2.5V

R1

PR48
4.02K/F_4

PC137
*10u/10V_8

PC136
0.1u/50V_6

PC115
*33p/50V_6

1.05V_FB

R2

PR49
10K/F_4

07/06 modify to short-pad.

PR217
*0/short_6

TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
TON=3.85p*1M*1/(Vin-0.5)
Frequency=1/(0.0036767)=272K

L(ripple current)
=(19-1.05)*1.05/(1u*272k*19)
~3.647A
RILIM=4.3mohm*20-1.823/20uA=3.907Kohm
I(choke)peak=23.647A

PR154
*0/short_6

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

+1.05V (UP6111A)
Date:
5

Sheet 38

Monday, July 12, 2010

1

of

43

+3VPCU

PR98
*0_4

PR94
*0_4

39

+3VPCU

PR123
*0_4

PR126
*0_4

PR97
*0_4

PR93
*0_4

DELAY_VR_PWRGOOD

PR89
*0_4

T82

3,6,14

T79

VIN
H_VID6

H_VID5

H_VID4

H_VID3

H_VID2

H_VID1

VIN

H_VID0
+
PC38
PC47
2200p/50V_6 10u/25V_1206

PC41
10u/25V_1206

PC37
0.1u/50V_6

PC102
100u/25V_6X7.7
D

07/06 modify to short-pad.

6266A_UG1
VIN

PR112
*0/short_8
PR119
10_4

PR102
1.91K/F_4

PR70
*0/short_6

GND

PR138

BOOT1

PSI#

PR108

*0_4

PGD_IN

PR110

147K/F_6

4
5

H_PROCHOT#

PR173
470K_4NTC

PR109
4.02K/F_4
VSOFT
PC67
0.022u/50V_6

PC66
0.01u/16V_4

Panasonic
ERT-J0EV474J

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

35

37

H_VID1

38

H_VID2

39

H_VID3

40

H_VID4

41

H_VID5

42
43

H_VID6
PR121
*0/short_4
PR99
499/F_4

VR_ON

6,14 PM_DPRSLPVR
3,6,12 ICH_DPRSTP#
14 VR_PWRGD_CK410#

H_VID0

VR_ON

44

DPRSLPVR 45

PR104

*0/short_4 ICH_DPRSTP#_R

46

PR120

*0/short_4

47

CLKEN#

PHASE1
PSI#
LGATE1
PGD_IN
PGND1
RBIAS
ISEN1

PR134

*0_6

PC97
0.22u/25V_8

34

ISEN2
T84

32
33
24

ISEN1
VIN

VR_TT#
NTC
PVCC

+5V_S5
31

SOFT

PR118
100/F_4

+
PC45
PC107
2200p/50V_6 10u/25V_1206

PC98
4.7u/10V_8

VID0
PU2
ISL6266A

VID1
VID2

UGATE2
BOOT2

13

26

6266A_UG2
PR137
2.2_6

VID4
PHASE2
VID5
LGATE2
VID6
PGND2
VR_ON
ISEN2

PC99
0.22u/25V_8

DPRSTP#

28
30
29

PL7
0.36uH

PR51
*2.2_6

23

ISEN2

6266A_LG2

NC

PC93
0.22u/25V_6

25

PC70
1000p/50V_4

PR116
97.6K/F_4

10

PC72
220p/50V_4

PQ38
AOL1718

19

PC35
*2200p/50V_6

PC83
*0.068u/25V_6

FB

PR95
2.7K/F_4
3.65K/F_6

PR133

10K/F_6

PR176
10K_6NTC

ISL6266_VO

Panasonic
ERT-J1VR103J

1/F_6

PR128

*0_6

17

PC77
0.33u/10V_6

ISEN1

Close to Phase 1 Inductor

PR96
1K/F_4
VCC_CORE

PC78
330p/50V_4

PC80
330p/50V_4

PR129

18

DFB

DROOP
16

VSEN
14

VW

PR132
VSUM

PR122
11K/F_4

COMP

PR100
3.9K/F_4

PR85
*0/short_6

PR114
13.3K/F_4

VSUM

FB2

RTN

+
PC30
*330u/2V_7343

6/29 Modify

15

PR115
11.3K/F_4

PC29
*330u/2V_7343

VDIFF

VO
PC68
1000p/50V_6

+
PC31
*330u/2V_7343

PR82
*0/short_6

PC82
0.22u/25V_6
PC71
100P/50V_4

PC96
100u/25V_6X7.7

6266A_PH2

CLK_EN#

VSUM

11

PC103
0.1u/50V_6

Modify 6/18
REV:B

PQ35
AOL1448

DPRSLPVR

PR106
1K/F_4

12

PC39
10u/25V_1206

27

VID3

OCSET

PC73
2200p/50V_6

VIN

PC54
0.22u/25V_6

PR117
1K/F_4

T83

PSI#_1

1/F_6

1
2
3

+3V_S5

*0/short_4

10K/F_6

PR135

PR111
*10K/F_4

PR103

3.65K/F_6

PR65

36
PR136
2.2_6

VR_ON

PR75
*0/short_6

35

Throttling temp.
105 degree C

PR107
10K/F_6

PC132
330u/2V_7343

VSUM

UGATE1
GND_T

1
2
3

49

PC36
*2200p/50V_6

22
21

Close to Phase 1 Inductor

VIN

VCC

PC89
1u/25V_8

48

PGD_IN
PC69
0.1u/50V_6

+
PC131
330u/2V_7343

PQ37
AOL1718

3V3

PR84
10/F_6

PC76
0.1u/50V_6

4
1
2
3

PC87
0.1u/50V_6

PGOOD

PWR_MON

PL6
0.36uH

PR52
*2.2_6

20

PR113
4.99K/F_6

VCC_CORE

PR127
10/F_6

6266A_LG1

PSI#

36A

Modify 6/18
REV:B

PQ34
AOL1448

6266A_PH1

+5V_S5

+3V

1
2
3

PR218
*0/short_8

PC81
180p/50V_4
PC75
0.01u/16V_4

PR101
10/F_6

Parallel
VCCSENSE

VSSSENSE 4

352-(&7=4
4XDQWD&RPSXWHU,QF

PR105
10/F_6
Size

Document Number

Rev
1A

CPU CORE(ISL6266A)
Date:
5

Sheet

Monday, July 12, 2010

1

39

of

43

40

[PWM]
PC57
10u/10V_8
PR74
*0/short_6

VIN

8207A_DH

0.3A

PC61
10u/10V_8

PC60
10u/10V_8

8207A_LX

PC49
0.1u/50V_6

8207A_VBST

+SMDDR_VTERM

8207A_DL

19
DRVL

LL

DRVH

VBST

PGND

VTTSNS

CS_GND
RT8207A
PU1

GND

CS

PC50
2200p/50V_6

PC55
10u/25V_1206

18

+1.5V_SUS

17
PQ33
AOL1718

16

PR64
4.7K/F_4

6/29 Modify

VTTREF

V5FILT

15
14

NC
12

S5
11

PR63
100K/F_4

S5_1.8V
S3_1.8V
PR79
*0_4

PR83
10K/F_4

PC46
1u/6.3V_4

PC40
*680p/50V_6

PC123
560u/2.5V

PC28
10u/10V_8

+3V_S5

VIN

(For RT8207A

PR71
*0/short_4

SUSON

35,42

PR76
*0/short_4

MAINON

21,35,38,42

400KHZ ) close to PC2008

+5V_S5

Vout = (PR150/PR149) X 0.75 + 0.75

AO1718 Rdson=3.8~4.3mOhm
L(ripple current)
=(19-1.5)*1.5/(0.56u*400k*19)
~6.168A
Vtrip= (20-(6.168/2))*(4.3mohm/2)=0.03637V
RILIM=0.8133/10uA=3.636K

8207A_SET
B

07/06 modify to short-pad.

PQ31
AOL1718

HWPG_1.5V 6,35
PR66
620K/F_4

PC56
*33p/50V_6

PR61
5.1/F_6

PC44
1u/6.3V_4

13

PR59
*4.7_6

REV:B andy 6/11

S3

VDDQSET
9

FOR DDR III

NC

PGOOD

10

COMP

VDDQSNS

+5V_S5

0.0375A

PC62
0.033u/50V_6

+5V_S5

+SMDDR_VREF

V5IN

1
2
3

MODE

1
2
3

+1.5V_SUS

OCP 20A
17.2A

PC92
10u/25V_1206
PL5
0.56uH

VTTGND

PQ29
AOL1448

VLDOIN

VTT

GND

1
2
3

20

21

22

23

25

24

PR88
10K/F_4

S5_1.8V

PR73
*0_4

S3_1.8V

PR219
*0/short_6

5
6
7
8

+1.5V_SUS

PR90
*0/short_6
37,42

MAIND

MAIND

4
PQ12
AO4468

S5

REF

VTT

+1.5V

+1.5VSUS
ON

ON

ON

3.6A

S3

ON

ON

OFF

S4/S5

OFF

OFF

OFF

3
2
1

S3
S0

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

DDR 1.5V(TPS51116)
Date:
5

Sheet 40

Monday, July 12, 2010

1

of

43

5/26 Modify Andy

+5V_S5

TP6

TP5

VIN

VIN

41
OCP=15A
11A

+VGPU_CORE
PR6
*EV@0_4

+3V

EV@1u/10V_6

PC167

EV@1u/10V_6

2
8792VCC

13
14

43 PG_1V_EN
*EV@0/short_4

PR211

*EV@0_4

8792EN

TON
DH

5/4 Modify andy

PR3

BST

8792BST
PR207
EV@1_6

EN
SKIP#
REFIN

FB

8792LX

8792DL

PC155
EV@2200p/50V_4

PC8
EV@10u/25V_1206

PC4
[email protected]/25V_6

5/26 change to DC-10F0M102

Andy

TP1

PL11
EV@1uH
PR18
*[email protected]_6

8
4

REF-2V
11

REF

ILIM

8792ILIM

07/06 modify to short-pad.

PC11
*EV@1000p/50V_4

PQ55
EV@AOL1718

15

R1

PR2
[email protected]/F_4

PR220
*0/short_6

EP

8792REF

PR214
[email protected]/F_4

R3

5/26 Modify Andy

PQ57
EV@AOL1448

PU11

DL

[email protected]/10V_4
PR212
EV@100K_4

8792DH

PGOOD

*EV@0_4
8792REFIN 10

8792TON

VCC

EV@MAX8792ETD+T LX
8792SKIP# 12

PC161

1
2
3

21,23 +3V_D_EXT
21,35,43 VGPU_ON

PR209

VDD

1
2
3

PC160

TP2

PC156
EV@10u/25V_1206

PR215
EV@100K_4

PC9
*EV@10u/25V_1206

PR208
EV@200K/F_4

PC10
*EV@330u/2V_7343

5/26 Modify Andy

PR210
*0/short_6

PC13
*EV@4700P/25V_4

PC157
[email protected]/50V_6

PC7
EV@330u/2V_7343

Place near GND pin15

PR8
EV@332K/F_4

PC169
EV@1000P/50V_4

5/26 change to 41.2K/F_4

Andy

PR213
EV@100K_4

Frequency(PR220=200K)

PQ2
EV@DMN601K-7

R2

GPU_VID1 (GPIO15)

PR4
EV@130K/F_4

+VGPU_CORE

1.12V

1.05V

0.95V

0.9V

2
8792EN

PQ3
EV@DTC144EU

PQ1
EV@DMN601K-7

PR12
EV@1M_6

PQ4
EV@DMN601K-7

PR5
EV@3K_4

GPU_VID2 (GPIO20)

PR13
EV@22_8

R4

GPU_VID2

PR15
EV@1M_6

AMD Park VID Table

+VGPU_CORE

PR1
[email protected]/F_4

PC2
[email protected]/16V_4

19

300K
VIN

PR10
EV@3K_4

GPU_VID1

19

PC1
[email protected]/16V_4

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

GPU CORE(MAX8792)
Date:
1

Sheet

Monday, July 12, 2010

5

41

of

43

42

+3V_S5

PC151
[email protected]/25V_4

PC152
EV@10u/10V_8

2.18A
PU9
1
2

PR24
*EV@0/short_4

15

MAINON

54418-1.8_VFB

7
8

PC14

EV@1000p/50V_4
PR200
EV@15K/F_4

PR198
EV@182K/F_4

PC149
*EV@100P/50V_4

VIN
VIN

PH

VIN

PH

EN

BOOT

VSNS

PWRGD

COMP

GND

RT/CLK

GND

SS

+1.8V

11

PL10
EV@1uH_7X7X3

12
13

PR197

*EV@0/short_6

14

PC146
[email protected]/50V_6

R1

PR25
EV@100K/F_4

3
4
HWPG_1.8V 35

AGND

PR199
EV@100K/F_4

54418-1.8_VFB
PC147
PC16
PC15
EV@10u/10V_8
[email protected]/25V_4
EV@10u/10V_8

+3V

22
21
20
19
18
17

PR22
EV@100K/F_4

EV@HPA00835RTER
10
PH

PAD
PAD
PAD
PAD
PAD
PAD

16

PC148
[email protected]/25V_4

PR23
[email protected]/F_4

R2

PC150
EV@1200p/50V_4

V0=0.8*(R1+R2)/R2

+3V_S5
VIN

+SMDDR_VTERM

+15V
2

+3VSUS

2.18A

PR130
1M_6

+1.8V
3
2
1

37

SUSD

SUSD
3

SUS_ON_G

PQ47
IV@AOL1448

SUSON

PC91
*2200p/50V_4

PQ32
DMN601K-7

PQ27
DMN601K-7

IV@22U/6.3V_8

+5V

+1.5V

EN
FB

HWPG_1.8V

PR187
IV@47/F_6

MAINON

Modfiy 4/19 andy

PC141
IV@33n/50V_6

+15V

+5VPCU

VCC

PR190 Rh
IV@100/F_4
+3V

PGD

07/06 modify from 1206 to 0805.

VIN

DRV

Rg

PQ30
DMN601K-7
1

PR165
1M_6

1
PR163
100K_4

PQ36
DTC144EU

PC143

PR189
IV@100K_4 5/18 Modify

PU8
IV@G9334
5

PR188
IV@261/F_4

35,40
B

+3V_S5

PC142
PC140
IV@10u/[email protected]/25V_6

PR155
22_8

PR139
22_8

GND

PR166
1M_6

PC144
[email protected]/25V_6

Vout1 = (1+Rg/Rh)*0.5
PR68
1M_6

PR60
22_8

PR41
22_8

PR62
22_8

PR45
1M_6

37,40

MAIND

MAIND
3

MAINON_ON_G

PQ18
DMN601K-7

PC33
*2200p/50V_4

PQ19
DMN601K-7
1

PQ20
DTC144EU

PR58
100K_4

PQ17
DMN601K-7

PQ16
DMN601K-7

352-(&7=4
4XDQWD&RPSXWHU,QF

PR69
1M_6

MAINON

21,35,38,40 MAINON

Size

Document Number

Rev
1A

VCCP 1.8V(UP6111A)
Date:
5

Monday, July 12, 2010

Sheet 42
1

of

43

43

+1.5V_SUS
+1.5V_GPU

PR205
EV@1M_4
D

+15V

PR202
EV@22_8

PR201
EV@1M_4

5
6
7
8

VIN

PR204
*EV@0_4

dGPU_D1
3

2.97A

21,35,41 VGPU_ON
PR206
EV@1M_4

PG_1.5V_EN

PQ6
EV@AO4468
2

PC153
PQ52
*[email protected]/50V_4
EV@DMN601K-7

PQ54
EV@DMN601K-7

VIN

PQ53
EV@DTC144EUA

PC154
EV@1u/10V_4

+1.5V_GPU

2
3
2
1

PR203
*EV@0/short_4

+1.8V_GPU

+1.8V

+15V

PR192
EV@22_8

PR191
EV@1M_4

PR193
EV@1M_4

+1.5V_GPU

3
3

dGPU_D
PR196
EV@1K_4

PC145
PQ49
*[email protected]/50V_4
EV@DMN601K-7

PQ50
EV@DMN601K-7
1

PQ51
EV@PDTC143TT

0.25A

+1.8V_GPU

PR195
EV@100K_4

PQ48
EV@AO3404

PR194
EV@1M_4

+3V_S5

+5VPCU

PR216
EV@10K_4
4

41

PG_1V_EN

3
8
9

+1.5V_SUS

VPP PGOOD
VEN
VIN
GND
GND

PG_1.5V_EN

PG_1.5V_EN 35

+1V

1.8A
NC

5
PR11
[email protected]/F_4

PR9
EV@100K_4

VO

PU10
EV@RT9018A

ADJ

PC159
[email protected]/50V_6

PC164

5/5 Modify

EV@22U/6.3V_8

07/06 modify from 1206 to 0805.

0.8V
PC162
PC163
PC3
EV@10u/10V_8
[email protected]/50V_6
[email protected]/50V_6
PR7
EV@34K/F_4

352-(&7=4
4XDQWD&RPSXWHU,QF

Vout =0.8(1+R1/R2)
=1V

Size

Document Number

Rev
1A

GPU_POWER
Date:
5

Sheet 43

Monday, July 12, 2010

1

of

43

44

VIN

PD8
SW1010CPT

35,37

PR178
1M_6

S5_ON

S5_ON

Thermal protection

PQ44
AO3409

PQ43
DTC144EU

VL

S5_ON

VL

TH_ON 2

SYS_SHDN# 3,37
PR184
1.33K/F_4

PR183
200K/F_4

PR180
200K/_6

PC138
0.1u/50V_6
2.469V

PQ45
DMN601K-7

PU7A
LM393

PC139
0.1u/50V_6

PR186
200K/F_4

PR185
10K_6NTC

+3VPCU

VL
S5_ON

2
PR179
100K/F_6

PQ46
DMN601K-7
1

PR182
10K/F_6

PU7B
5
4.95V

PD9
7

NC_TEMP

T96

RB500V-40
LM393

PR181
1M/F_6

For EC control thermal protection (output 3.3V)

D

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

Thermal Protection
Date:
1

Monday, July 12, 2010

Sheet 44
5

of

43

MODEL:

MODEL

REV

CHANGE LIST
PAGE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

First release
1.Page40:change HWPG_1.5V pull up to +3V_S5 for S3 issue
2.Page29:Add R570 pull up +1.5V for uma Audio I/O
3.Page26:Swap HDMI Lane2 for HDMI issue
4.Page31:U34 and R567 no stuff ,R555 stuff it for LAN ID issue
5.Page02:Q12 and Q13 change Part number from BAM700200F6 to BAM700200H2
6.Page29:R55 and R56 change Part number to CS33303F911(33K) for Audio
7.Page29:change R86 and U6 Pin5 pull up to +5V_S5
8.Page29:change R84 value to 0 ohm
9.Page30:change Q25 and Q27 Part number to BAM70020002 as ZYB
10.Page25:L1,L2,L3 change to CX8LL680001
11.Page25:C1,C2,C3,C5,C6,C7 change to CH-5006JBD4
12.Page25:R11,R14 change to CS01502JB12
13.Page28:Add another BT circuit (USB port5),Add Q30,RN37,C792,CN22
14.Page07:Change R425,R426 to CS02492FB29 for CRT issue
15.Page13:Change BT 2.1 to USB port 7
16.Page28:Change BT 2.1 to USB port 7
17.Page25:chage 0805 to SHORT Pad R71,R72,R98,R146
18.Page29:Stuff R84 U6 and no stuff R86 for Audio bobo noise
19.Page10:change R171 and R429 to bead CX8PG181001
20.Page30:stuff Q25 and Q27 and no stuff R46 R48 for Audio bobo noise
21.Page40:Add PR219
22.Page38:Add PR217
23.Page41:Add PR220
24.Page39:Add PR218
25.Page36: Change PR16 (0.01/F_7520) to CS+0108GL13 (0.01_3720)
26.Page41: DEL JP1 and JP4
27.Page39: DEL JP2 and JP3
28.Page38:change PR171,PR38 to short Pad
29.Page36:change PR125,PR14,PR26 to short Pad
30.Page37:change PR143,PR145,PR146,PR153,PR157,PR168,PR169,PR170,PR50,PR44,PR56 to short Pad
31.Page39:change PR120,PR121,PR104,PR103,PR70,PR75,PR82,PR85 to short Pad
32.Page40:change PR71,PR76,PR74 to short Pad
33.Page41:change PR209 to short Pad (EV@)
34.Page42:change PR24,PR197 to short Pad (EV@)
35.Page43:change PR203 to short Pad (EV@)
36.Page36:Change PQ26 to AO4468
P/N
BAM44680003

37.Page37:PD2 and PD5 no stuff

38.Page39:PC29 and PC31 no stuff
39.Page36:PJ1 change Part number to DFHD08MR140

ZQ5 MB
D

01.Page39:PC83 no stuff
B

02.Page39:Change PR64 to CS24702FB10

ZR6 MB
FROM

TO

1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A

03.Page16: Del C539 (*10U/6.3V_6).

04.Page17: Del C538 (*10U/6.3V_6).

05.Page38: Change AGND (0 ohm) to Short Pad(0603): PR154

PR217.
06.Page40: Change AGND (0 ohm) to Short Pad(0603): PR219
PR90.
07.Page41: Change AGND (0 ohm) to Short Pad(0603): PR210
PR220.
08.Page39:Change AGND (0 ohm) to Short Pad(0805): PR112,PR218.
09.Page43:Change PC164 (22uF/10V_1206) to CH6221M9A07 (22uF/6.3V_0805)
10.Page42:Change PC143 (22uF/10V_1206) to CH6221M9A07 (22uF/6.3V_0805)
11.Page34:Modify HOLE18 to dummy net.
12.Page34:Add HOLE22 for ME.

MB Assy' P/N: 31ZQ5MB0000

Project :ZQ5 MB

Document No.:

Approved by :

Drawing by :Andy Chen

DATE: 2009/03/04

352-(&7=4
4XDQWD&RPSXWHU,QF
Size

Andy_Lin

Document Number

Rev
1A

Thermal Protection
Date:
2

Monday, July 12, 2010

Sheet 45
1

of

43