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Experiment No. 3.2

This document describes a fully dynamic positive edge-triggered D-flipflop circuit implemented using only 8 transistors. Clock overlap is an important concern, as the output Q can change on the falling edge if overlap is too large. Simulations are shown to determine the setup time of 38ps and clock-to-Q delay of 69ps. The data-to-Q delay is determined to be 107ps.

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Harshal Ambatkar
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22 views3 pages

Experiment No. 3.2

This document describes a fully dynamic positive edge-triggered D-flipflop circuit implemented using only 8 transistors. Clock overlap is an important concern, as the output Q can change on the falling edge if overlap is too large. Simulations are shown to determine the setup time of 38ps and clock-to-Q delay of 69ps. The data-to-Q delay is determined to be 107ps.

Uploaded by

Harshal Ambatkar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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2.

Dynamic
D
Tran
nsmission Ga
ate Edge Triiggered D-Fliipflop

A fully dynam
mic positive ed
dge-triggered register base d on the mastter-slave conccept is shownn in
above figu
ure. This imp
plementation of
o an edge-triiggered registter is very effficient as it requires only 8
transistorss. The hold tim
me is approxiimately zero, since the trannsmission gatte is turned off
ff on the clockk
edge and further inputss changes are ignored. Onee important coonsideration ffor such a dynnamic registeer is
that the sttorage nodes (i.e.,
(
the statee) has to be refreshed at perriodic intervaals to prevent a loss due to
charge leaakage, due to diode leakage as well as sub-threshold currents. In ddatapath circuuits, the refressh
rate is nott an issue sincce the registerrs are periodiccally clockedd, and the storrage nodes aree constantly
updated.
Clock
C
overlap is an importaant concern fo
or this registerr. The output Q can changge on the fallinng
edge if thee overlap periiod is large obviously an
a undesirablee effect for a ppositive edgee-triggered
register. The
T data mustt be stable durring the high--high (1-1) ovverlap period.. The 0-0 oveerlap can be
addressed
d by making sure that theree is enough deelay between the D input aand node 2 ennsuring that neew
data samp
pled by the maaster stage do
oes not propag
gate through tto the slave sttage.
Schematic Diagram:

VDD
M13

VDD

CLK
CLK

Data

Data

val0=1.8
val1=0

VDD

CLK

val0=0
val1=1.8

M12

gnd

gnd

CLKBAR

gnd
gnd
VDD

VDD

VDD

M2

M3

M10

CLKBAR

M1

M7
M8

M0

Data

VDD

M9

CLKBAR

CLK

gnd

CLK
gnd

gnd
gnd

1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2

CLK 0
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4

SEL>>
Data -0.1
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0
-0.139
0

5n

10n

15n

20n

25n

A1:(16.15000ns, 900.00000mV); A2:(16.12000ns, 900.00000mV); dif:(30.00000ps, 0.00000V)

time, s

30n

35n

40n

45n

48n

The D-input edge is skewed relative to the clock signal until the output Q stops following D-input.
For a skew of 30 ps, the incorrect value of input D is sampled and an incorrect value propagates to
the output Q .
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>

CLK -0.1
1.8
1.6
1.4

1.2
1
0.8
0.6
0.4
0.2
Data

0
1.8
1.6
1.4
1.2

1
0.8
0.6
0.4
Q

0.2

0
-0.148
0

5n

10n

15n

20n

A1:(16.15000ns, 900.00000mV); A2:(16.11200ns, 900.00000mV); dif:(38.00000ps, -14.32188fV)

25n

30n
time, s

For a skew of 38 ps, output Q follows D-input.


= 8

35n

40n

45n

48n

Date/Time Run: 4/8/2016 10:37:07 AM


1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>
-0.1

CLK
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0

Data
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0
-0.148
0

5n

10n

15n

20n

25n

30n

35n

40n

45n

48n

Q
time, s
A1:(16.21889ns, 900.00000mV); A2:(16.15000ns, 900.00000mV); dif:(68.89092ps, 0.00000V)
SymSpice

Clock-to-Q delay
.

Date/Time Run: 4/8/2016 10:37:07 AM

1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
SEL>>
-0.1

CLK
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0

Data
1.8
1.6
1.4
1.2
V

1
0.8
0.6
0.4
0.2
0
-0.148
0

5n

10n

15n

20n

25n

30n

35n

Q
time, s
A1:(16.21889ns, 900.00000mV); A2:(16.11200ns, 900.00000mV); dif:(106.89092ps, 0.00000V)
SymSpice

Data-to-Q delay
.

40n

45n

48n

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