Digital Integrated

Circuits
Jan M. Rabaey

AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic

Design
Methodologies
December 10, 2002
Digital Integrated Circuits2nd

Design Methodologies

100,000,000

.10 1,000,000

.35

Transistor/Staf Month

10,000,000

100,000 58%/Yr. compound

Complexity growth rate
10,000

1,000,000
100,000

1,000

10,000
X

10
2009

2007

2005

2003

2001

1991

1989

1987

1985

1983

100

21%/Yr. compound
Productivity growth rate

1
1981

1999

10

1,000

1997

X x

X X

1995

100
2.5

Productivity (Trans./Staf-Month)

10,000,000

1993

Logic Transistors per Chip (K)

The Design Productivity Challenge

A growing gap between design complexity and design productivity

Source: sematech97
Digital Integrated Circuits2nd

Design Methodologies

A Simple Processor

INPUT/OUTPUT

MEMORY

CONTROL

DATAPATH

Digital Integrated Circuits2nd

Design Methodologies

A System-on-a-Chip: Example

Courtesy: Philips

Digital Integrated Circuits2nd

Design Methodologies

None

Digital Integrated Circuits2nd

1-10

Embedded microprocessor

Configurable/Parameterizable

10-100

Hardwired custom

Energy Efficiency (in MOPS/mW)

100-1000

Domain-specific processor
(e.g. DSP)

Impact of Implementation Choices

0.1-1

Somewhat
flexible

Fully
flexible

Flexibility
(or application scope)

Design Methodologies

Design Methodology

Design process traverses iteratively between three abstractions:

behavior, structure, and geometry
More and more automation for each of these steps
Digital Integrated Circuits2nd

Design Methodologies

Implementation Choices
Digital Circuit Implementation Approaches

Custom

Semicustom

Cell-based

Standard Cells
Compiled Cells

Digital Integrated Circuits2nd

Macro Cells

Array-based

Pre-diffused
(Gate Arrays)

Pre-wired
(FPGA's)

Design Methodologies

The Custom Approach

Intel 4004

Digital Integrated Circuits2nd

Courtesy Intel

Design Methodologies

Transition to Automation and Regular Structures

Intel 4004 (71)

Intel 8080

Intel 8286
Digital Integrated Circuits2nd

Intel 8085

Intel 8486
Courtesy Intel

Design Methodologies

Cell-based Design (or standard cells)

Rows of cells

Feedthrough cell

Digital Integrated Circuits2nd

Logic cell

Routing
channel

Functional
module
(RAM,
multiplier,)

Routing channel
requirements are
reduced by presence
of more interconnect
layers

Design Methodologies

Standard Cell Example

[Brodersen92]

Digital Integrated Circuits2nd

Design Methodologies

Standard Cell The New Generation

Cell-structure
hidden under
interconnect layers

Digital Integrated Circuits2nd

Design Methodologies

Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

Digital Integrated Circuits2nd

Design Methodologies

Automatic Cell Generation

Initial transistor
geometries

Digital Integrated Circuits2nd

Placed
transistors

Routed
cell

Compacted
cell

Courtesy Acadabra

Finished
cell

Design Methodologies

A Historical Perspective: the PLA

Product terms
x0 x1
x2

AND
plane

OR
plane

f0
x0

Digital Integrated Circuits2nd

x1

f1

x2

Design Methodologies

Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)

minterm

Inverting format (NORNOR) more effective

Digital Integrated Circuits2nd

Design Methodologies

PLA Layout Exploiting Regularity

And-Plane

V DD

x0 x0 x1 x1 x2 x2
Pullupdevices
Digital Integrated Circuits2nd

Or-Plane

GND

f0 f1
Pullupdevices
Design Methodologies

Breathing Some New Life in PLAs

River PLAs

A cascade of multiple-output PLAs.

Adjacent PLAs are connected via river routing.

BUFFER

PRE-CHARGE

P R E -C H A R G E

BUFFER

PRECHARGE

BUFFER

P R E -C H A R G E

BUFFER

PRE-CHARGE

BU FFER

P R E -C H A R G E

BUFFER

PRECHARGE

BU FFER

BUFFER

Digital Integrated Circuits2nd

P R E -C H A R G E

No placement and routing needed.

Output buffers and the input buffers
of the next stage are shared.

Courtesy B. Brayton

Design Methodologies

Area:
RPLAs (2 layers)
1.23
SCs (3 layers) 1.00,
NPLAs (4 layers)
1.31
Delay
RPLAs
1.04
SCs
1.00
NPLAs
1.09
Synthesis time: for RPLA , synthesis time equals design time;
SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable

delay

Experimental Results

1.4

0.6

0.2
0

Layout of C2670

Standard cell,
2 layers channel routing

Digital Integrated Circuits2nd

2
SC

Standard cell,
3 layers OTC

Network of PLAs,
4 layers OTC

4
NPLA

area

RPLA

River PLA,
2 layers no additional routing

Design Methodologies

MacroModules

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator

Digital Integrated Circuits2nd

Design Methodologies

Soft MacroModules

Digital Integrated Circuits2nd

Synopsys DesignCompiler

Design Methodologies

Intellectual Property

A Protocol Processor for Wireless

Digital Integrated Circuits2nd

Design Methodologies

Semicustom Design Flow

Design Capture

Design Iteration

Pre-Layout
Pre-Layout
Simulation
Simulation

Post-Layout
Post-Layout
Simulation
Simulation
Circuit
CircuitExtraction
Extraction

Behavioral

HDL
HDL
Logic
LogicSynthesis
Synthesis

Structural

Floorplanning
Floorplanning
Placement
Placement

Physical

Routing
Routing
Tape-out

Digital Integrated Circuits2nd

Design Methodologies

The Design Closure Problem

Iterative Removal of Timing Violations (white lines)

Digital Integrated Circuits2nd

Courtesy Synopsys

Design Methodologies

Integrating Synthesis with

Physical Design
RTL (Timing) Constraints
Physical
PhysicalSynthesis
Synthesis
Macromodules
Fixed netlists

Netlist with
Place-and-Route Info

Place-and-Route
Place-and-Route
Optimization
Optimization
Digital Integrated Circuits2nd

Artwork

Design Methodologies

Late-Binding Implementation
Array-based

Pre-diffused
(Gate Arrays)

Digital Integrated Circuits2nd

Pre-wired
(FPGA's)

Design Methodologies

Gate Array Sea-of-gates

polysilicon
VD D

rowsof
uncommitted
cells

metal
possible
contact

GND

In 1 In2

Uncommited
Cell

In 3 In4

routing
channel

Committed
Cell
(4-input NOR)
Out

Digital Integrated Circuits2nd

Design Methodologies

Sea-of-gate Primitive Cells

O x id e - i s o l a t io n
PM O S
PMOS
NM OS

NM OS

NM OS

Using oxide-isolation

Digital Integrated Circuits2nd

Using gate-isolation

Design Methodologies

Example: Base Cell of Gate-Isolated GA

VDD

continuous
p-dif strip

continuous
n-dif strip

contact for
isolator
GND

Digital Integrated Circuits2nd

From Smith97

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

n-well
p-well
n-dif
p-dif
poly
m1
m2
contact

Design Methodologies

Example: Flip-Flop in Gate-Isolated GA

VDD

CLR
Q

CLK
Q
D

GND

Digital Integrated Circuits2nd

From Smith97

Design Methodologies

Sea-of-gates
Random Logic

Memory
Subsystem
LSI Logic LEA300K
(0.6 m CMOS)
Digital Integrated Circuits2nd

Courtesy LSI Logic

Design Methodologies

The return of gate arrays?

Via programmable gate arra

(VPGA)

Via-programmable cross-point

metal-5

metal-6

programmable via

Exploits regularity of interconnect

Digital Integrated Circuits2nd

[Pileggi02]

Design Methodologies

Prewired Arrays
Classification of prewired arrays (or field-programmable devices):

Based on Programming Technique

Fuse-based (program-once)
Non-volatile EPROM based
RAM based

Programmable Logic Style

Array-Based
Look-up Table

Programmable Interconnect Style

Channel-routing
Mesh networks

Digital Integrated Circuits2nd

Design Methodologies

Fuse-Based FPGA
antifuse polysilicon

ONO dielectric

n+ antifuse diffusion
2l

Open by default, closed by applying current pulse

Digital Integrated Circuits2nd

From Smith97

Design Methodologies

Array-Based Programmable Logic

I5

I4

I3

I2

I1

I0

Programmable
OR array

Programmable AND array

I3

I2

I1

I0

Programmable
OR array

Fixed AND array

O 3O 2O 1O 0

PLA

I5

I4

I3

I2

I1

I0

Fixed OR array

Programmable AND array

O3O2O1O0

PROM

O 3O 2O 1 O 0

PAL

Indicates programmable connection

Indicates fixed connection

Digital Integrated Circuits2nd

Design Methodologies

Programming a PROM
1

X2

X1

X0

: programmed node
NA NA f 1 f 0

Digital Integrated Circuits2nd

Design Methodologies

More Complex PAL

programmable AND arrayi 3
(2 jk)

k macrocells
product
terms

j -wide OR array
D

OUT

j
macrocell
CLK
A

i inputs

i inputs, j minterms/macrocell, k macrocells

Digital Integrated Circuits2nd

From Smith97

Design Methodologies

2-input mux
as programmable logic block
Configuration

0
F

Digital Integrated Circuits2nd

F=

0
0
0
0
X
Y
Y
1
1
1

0
X
Y
Y
0
0
1
0
0
1

0
1
1
X
Y
X
X
X
Y
1

0
X
Y
XY
XY
XY
X1 Y
X
Y
1

Design Methodologies

Logic Cell of Actel Fuse-Based FPGA

A
B

SA

Y
1

C
D

SB
S0
S1

Digital Integrated Circuits2nd

Design Methodologies

Memory

Look-up Table Based Logic Cell

Out

In

Out

00

00

01

10

11

ln1 ln2

Digital Integrated Circuits2nd

Design Methodologies

LUT-Based Logic Cell

4

C1....C4

xx
D4
D3
D2

Logic
function
of
xxx

D1

F2
F1

Logic
function
of
xxx

x
xxxxx

Xilinx 4000 Series

Digital Integrated Circuits2nd

xxxx

xxxx

xxxx
Bits
control

xx
xx
xx
xx
Logic
functionx
of
xxx

F4
F3

Figure must be
updated

xxxx
xx

x xx x

xx xx

x
x

x
Bits
control

xx
xx
xx
xx

xxxx
x xx x

xx

xx xx
H
P

Multiplexer Controlled
by Configuration Program

Courtesy Xilinx

Design Methodologies

Array-Based Programmable Wiring

M

Interconnect
Point

Programmed interconnection

Input/output pin

Cell

Horizontal

tracks

Vertical tracks

Digital Integrated Circuits2nd

Design Methodologies

Mesh-based Interconnect Network

Switch Box

Connect Box

Interconnect
Point

Digital Integrated Circuits2nd

Courtesy Dehon and Wawrzyniek

Design Methodologies

Transistor Implementation of Mesh

Digital Integrated Circuits2nd

Courtesy Dehon and Wawrzyniek

Design Methodologies

Hierarchical Mesh Network

Use overlayed mesh

to support longer connections
Reduced fanout and reduced
resistance

Digital Integrated Circuits2nd

Courtesy Dehon and Wawrzyniek

Design Methodologies

EPLD Block Diagram

Macrocell

Primary inputs

Digital Integrated Circuits2nd

Courtesy Altera

Design Methodologies

Altera MAX

Digital Integrated Circuits2nd

From Smith97

Design Methodologies

Altera MAX Interconnect Architecture

column channel

row channel

t PIA

LAB1

LAB2
LAB
PIA

t PIA

LAB6

Array-based
(MAX 3000-7000)
Digital Integrated Circuits2nd

Mesh-based
(MAX 9000)
Courtesy Altera

Design Methodologies

Field-Programmable Gate Arrays

Fuse-based
I / O B u ff e r s
P r o g r a m / T e s t / D ia g n o s t i c s
V e r ti c a l ro u te s

I/O B u ffe rs

I/O B u ffe r s

Standard-cell like
floorplan

R o w s o f lo g i c m o d u le s
R o u ti n g c h a n n e ls

I / O B u ff e r s

Digital Integrated Circuits2nd

Design Methodologies

Xilinx 4000 Interconnect Architecture

CLB

12

Quad

Single

Double

Long

2
3

12

Quad

Long

Global

Long

Clock

Digital Integrated Circuits2nd

Double Single Global

Direct

Connect

Long

2
Carry

Direct

Clock Chain Connect

Courtesy Xilinx

Design Methodologies

RAM-based FPGA

Xilinx XC4000ex
Digital Integrated Circuits2nd

Courtesy Xilinx

Design Methodologies

A Low-Energy FPGA (UC Berkeley)

Array Size: 8x8 (2 x 4
LUT)
Power Supply: 1.5V &
0.8V
Configuration: Mapped as
RAM
Toggle Frequency:
125MHz
Area: 3mm x 3mm

Digital Integrated Circuits2nd

Design Methodologies

Larger Granularity FPGAs

PADDI-2 (UC Berkeley)

Digital Integrated Circuits2nd

1-mm 2-metal
CMOS tech

1.2 x 1.2 mm2

600k transistors

208-pin PGA

fclock = 50 MHz

Basic Module: Datapath

av

= 3.6 W @ 5V

Design Methodologies

Design at a crossroad

500 k Gates FPGA

MultiSpectral
+ 1 Gbit DRAM
RAM
Imager
Preprocessing
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS

Digital Integrated Circuits2nd

Analog

System-on-a-Chip

C
system
+2 Gbit
DRAM
Recognition

Embedded applications where

cost, performance, and energy
are the real issues!
DSP and control intensive
Mixed-mode
Combines programmable and
application-specific modules
Software plays crucial role

Design Methodologies

Addressing the Design Complexity Issue

Architecture Reuse
Reuse comes in generations
Generation

Reuse element

Status

1st

Standard cells

Well established

2nd

IP blocks

Being introduced

3rd

Architecture

Emerging

4th

IC

Early research

Source: Theo Claasen (Philips) DAC 00

Digital Integrated Circuits2nd

Design Methodologies

Architecture ReUse

Silicon System Platform

Flexible architecture for hardware and software

Specific (programmable) components
Network architecture
Software modules
Rules and guidelines for design of HW and SW

Has been successful in PCs

Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)

Speed (compute power)

Dissipation
Costs
Real / non-real time data

Digital Integrated Circuits2nd

Design Methodologies

Platform-Based Design
Only the consumer gets freedom of choice;
designers need freedom from choice
(Orfali, et al, 1996, p.522)

A platform is a restriction on the space of possible implementation

choices, providing a well-defined abstraction of the underlying
technology for the application developer
New platforms will be defined at the architecture-micro-architecture
boundary
They will be component-based, and will provide a range of choices
from structured-custom to fully programmable implementations
Key to such approaches is the representation of communication in
the platform model

Digital Integrated Circuits2nd

Source:R.Newton

Design Methodologies

Berkeley Pleiades Processor

0.25um 6-level metal CMOS
FPGA

5.2mm x 6.7mm
1.2 Million transistors

Reconfigurable
Data-path
Interface

ARM8 Core

Digital Integrated Circuits2nd

40 MHz at 1V
2 extra supplies: 0.4V, 1.5V
1.5~2 mW power dissipation

Design Methodologies

Heterogeneous Programmable Platforms

FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O
Digital Integrated Circuits2nd

Courtesy Xilinx

Design Methodologies

Summary
Digital CMOS Design is kicking and healthy
Some major challenges down the road caused
by Deep Sub-micron

Super GHz design

Power consumption!!!!
Reliability making it work
Some new circuit solutions are bound to emerge

Who can afford design in the years to come?

Some major design methodology change in the
making!

Digital Integrated Circuits2nd

Design Methodologies