Circuit Design Using VHDL
Circuit Design Using VHDL
using VHDL
8/28/2015
Tools required
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8/28/2015
Number representation
in VHDL
Integers
Binary
Values
Unsigned
Values
Signed
Values
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8/28/2015
ENTITY
ARCHITECTURE.
ENTITY comp_add IS
PORT (a, b: IN INTEGER
RANGE 0 TO 7;
comp: OUT STD_LOGIC;
sum: OUT INTEGER RANGE 0
TO 15);
END ENTITY;
ARCHITECTURE circuit OF
comp_add IS
BEGIN
comp <= '1' WHEN a>b
ELSE '0';
sum <= a + b;
END ARCHITECTURE;
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Truth tables
Implement
operators.
Half adder
Full adder
S
Excrcies1
Excrcies2