Yet Another Latch

and Gotchas Paper

Don Mills
Microchip Technology, INC
Chandler, AZ

Discussion Topics

casez, casex, case inside

unique case & priority case still allow latches
SRFF: Synopsys RTL coding bug work-around
SV logic type NOT, what is SV logic really?

Yet Another Latch and Gotcha Paper

Don Mills

A little history
Past papers provide details on these topics
Clifford Cummings, full_case parallel_case, the Evil Twins of Verilog
Synthesis
Clifford Cummings, SystemVerilogs priority & uniqueA Solution to
Verilogs full_case & parallel_case Evil Twins!
Stuart Sutherland, SystemVerilog Saves the Daythe Evil Twins are
Defeated! unique and priority are the new Heroes
Don Mills and Clifford Cummings, "RTL Coding Styles That Yield
Simulation and Synthesis Mismatches
Stuart Sutherland and Don Mills, Standard Gotchas, Subtleties in the
Verilog and SystemVerilog Standards That Every Engineer Should
Know
Shalom Bresticker, Just When You Thought it Was Safe to Start Coding
AgainReturn of the SystemVerilog Gotchas
Don Mills, Being Assertive With Your X
3

Yet Another Latch and Gotcha Paper

Don Mills

Discussion Topics

casez, casex, case inside

unique case & priority case still allow latches
SRFF: Synopsys RTL coding bug work-around
SV logic type NOT, what is SV logic really?

Yet Another Latch and Gotcha Paper

Don Mills

Case Statement Definitions

Case expression

Case items

Default case item

always_comb begin
case (sel)
2'b00 : out
2'b01 : out
2'b10 : out
2'b11 : out
default : out
endcase
end

Yet Another Latch and Gotcha Paper

=
=
=
=
=

a;
b;
c;
d;
'X;

BORING

Don Mills

Case statement
always_comb begin
case (sel)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
endcase
end

always_comb begin
case (sel)
2'b00 : out
2'b01 : out
2'b10 : out
2b11 : out
endcase
end

=
=
=
=

a;
b;
c;
d;

3:1 mux case will

generate latches not
covering 2b11 state in
simulation or synthesis

4:1 mux case will not generate

latches in synthesis and usually
not in simulation
what is the simulation output
when sel has Xs or Zs in it?

Yet Another Latch and Gotcha Paper

Don Mills

Case statement with default

Propagating the X is common
In simulation, the X must be visible
Must trace back to the source of the X

always_comb begin
case (sel)
2'b00 : out
2'b01 : out
2'b10 : out
2'b11 : out
default : out
endcase
end

=
=
=
=
=

a;
b;
c;
d;
'X;

4:1 mux case will not generate

latches in synthesis and usually
not model latches in simulation

what is the simulation output

when sel has Xs or Zs in it?

Yet Another Latch and Gotcha Paper

Don Mills

if / else vs conditional operator for X prop

if / else is known to block X prop if sel is unknown
Many use the conditional operator (thinking it will always
propagate Xs) wrong!
assign out = sel ? a : b;
always_comb begin
if (sel)
out = a;
else
out = b;
end

sel
0
1
X

a
dead
dead
dead

b
beef
beef
beef

OR
always_comb
out = sel ? a : b;

out
dead
beef
beef

BOTH methods will

prevent X propagation
8

sel
0
1
X

a
dead
dead
dead

b
beef
beef
beef

out
dead
beef
xexx

dead

dead

dead

Yet Another Latch and Gotcha Paper

Don Mills

casex / casez statement

always_comb begin
{memce0, memce1, cs} = '0;
casex ({addr, en})
3'b101 : memce0 = '1;
3'b111 : memce0 = '1;
3'b0?1 : cs = '1;
endcase
end
always_comb begin
{memce0, memce1, cs} = '0;
casez ({addr, en})
3'b101 : memce0 = '1;
3'b111 : memce0 = '1;
3'b0?1 : cs = '1;
endcase
end

casex X or Z or ? (another
symbol for Z) are dont cares in
case items or case expression

casez Z or ? (another symbol

for Z) are dont cares in case
items or case expression
What if en or addr has
an X value

Previous guideline use casez over casex

better guideline coming
9

Yet Another Latch and Gotcha Paper

Don Mills

case inside statement with default

case inside allows case item dont cares using
X, Z or ?
X, Z in case expression is literal rather than
dont care
always_comb begin
{memce0, memce1, cs} = '0;
case ({addr, en}) inside
A case inside will simulate the
3'b101 : memce0 = '1;
exact way the casex synthesizes
3'b111 : memce0 = '1;
3'b0?1 : cs = '1;
default : begin
// synthesis translate_off
$display(Error in case expression);
// synthesis translate_on
end
endcase
end
10

Yet Another Latch and Gotcha Paper

Don Mills

casex immediate assertions

Assertions allow
- casex and casez to be same
- Localized X finding
- Can be disabled
always_comb begin
assert (!$isunknown({addr, en}))
else $error(%m : case_sel = X);
{memce0, memce1, cs} = '0;
always_comb begin
casex ({addr, en})
assert (!$isunknown({sel}))
3'b101 : memce0 = '1;
else $error(%m : case_sel = X);
3'b111 : memce0 = '1;
case (sel)
3'b0?1 : cs = '1;
2'b00 : out = a;
endcase
2'b01 : out = b;
end
2'b10 : out = c;
2b11 : out = d;
NOTE: use this same assertion
endcase
end
method for if statements
11

Yet Another Latch and Gotcha Paper

Don Mills

Discussion Topics

12

casez, casex, case inside

unique case & priority case still allow latches
SRFF Synopsys coding error revealed!
SV logic type NOT, what is SV logic really?

Yet Another Latch and Gotcha Paper

Don Mills

Synthesis Directives
Lots of papers on directives and SV
enhancements
full_case
parallel_case
Often represented the code differently in
synthesis than in simulation
Should only be used with inverse case
statement type coding
Note:

13

Yet Another Latch and Gotcha Paper

Don Mills

SV 2005 case enhancements

Lots of papers on SV Enhancements
unique case
priority case
Designed to provide same functionality in simulation

and synthesis
Provides simulation warnings of possible latch type
code
Unfortunately does not issue warning for all latch
conditions

14

Yet Another Latch and Gotcha Paper

Don Mills

unique case with latches

unique case only
looks at
case expression /
case items
No overlapping
conditions
A condition matches
each time the case is
entered

always_comb begin
unique case (sel)
2'b00 : begin out1
out2
end
2'b01 : out2 = b;
2'b10 : out1 = c;
default : begin out1
out2
end
endcase
end

This case statement has unique

case and a default but will still
generate latches with no warnings
until synthesis reports

15

Yet Another Latch and Gotcha Paper

Don Mills

= a1;
= a2;

= a1;
= a2;

unique case with external default

unique case
synthesizes same as
full_case
Defaults outside the
case may be ignored
by synthesis

always_comb begin
out1 = a1;
out2 = a2;
unique case (sel)
2'b00 : begin out1 = a1;
out2 = a2;
end
2'b01 : out2 = b;
2'b10 : out1 = c;
endcase
end

full_case (and unique case) assumes all the

content for the case is defined in the case and
all other conditions are dont cares for synthesis
16

Yet Another Latch and Gotcha Paper

Don Mills

Two possible solutions to

always prevent latches
always_comb begin
unique case (sel)
2'b00 : begin out1
out2
end
2'b01 : begin out1
out2
end
2'b10 : begin out1
out2
end
default : begin out1
out2
end
endcase
end

= a1;
= a2;
= a1;
= b;

always_comb begin
out1 = a1;
out2 = a2;
case (sel)
2'b01 : out2 = b;
2'b10 : out1 = c;
endcase
end

= c;
= a2;
= a1;
= a2;

Solution 2: Define default

outputs prior to any
conditional logic.
Small code no latches

Solution1: Define all outputs for

all case conditions messy with
lots of outputs
17

Yet Another Latch and Gotcha Paper

Don Mills

unique0 case solution

(if it was only supported)
unique0 case only
looks for case select /
case items
No overlapping
conditions
Does not require a
match when the case
is entered

always_comb begin
out1 = a1;
out2 = a2;
unique0 case (sel)
2'b01 : out2 = b;
2'b10 : out1 = c;
endcase
end

Currently, unique0 is not supported by

simulation or synthesis BUMMER!!!!!

This case statement

has unique0 case and
defaults before the
case
No latches
No priority encoder

(unique0 IS REALLY JUST PARALLEL

CASE)
18

Yet Another Latch and Gotcha Paper

Don Mills

Discussion Topics

casez, casex, case inside

unique case & priority case still allow latches
SRFF: Synopsys RTL coding bug work-around
SV logic type NOT, what is SV logic really?

19

Yet Another Latch and Gotcha Paper

Don Mills

SRFF RTL vs Synthesis Model

Are asynchronous Set/Reset Flip-Flops used?

YES
Asynchronous Set/Reset Flip-Flops manage
IC fuses for chip configuration
Google search microprocessor fuses
20

Yet Another Latch and Gotcha Paper

Don Mills

SRFF: Synthesis required coding style

always_ff @(

posedge clk
or negedge rst_n
or negedge set_n
);
if
(!rst_n) q <= '0;
else if (!set_n) q <= '1;
else
q <= d;
0

NOTE: rst_n has

priority over set_n
The set_n has no effect on
simulation results.
This code will synthesize
correctly but fails in this
simulation corner case
6

10

clk
rst_n
set_n
d
q

16hDEAD
X

16h0000

16hDEAD

16h0000

16hDEAD

?
21

Yet Another Latch and Gotcha Paper

Don Mills

SRFF: Simulation model for Synthesis

always_ff @(

posedge clk
or negedge rst_n
or negedge set_n
NOTE: rst_n has
priority over set_n
`ifndef SYNTHESIS
or posedge (rst_n & ~set_n)
`endif
);
This code will
if
(!rst_n) q <= '0;
simulate and
else if (!set_n) q <= '1;
synthesize correctly
else
q <= d;
0

10

clk
rst_n
set_n
d
q
22

16hBA5E
X

16h0000

16hBA5E

16h0000

16hFFFF

Yet Another Latch and Gotcha Paper

16hBA5E

Don Mills

Discussion Topics

casez, casex, case inside

unique case & priority case still allow latches
SRFF: Synopsys RTL coding bug work-around
SV logic type NOT, what is SV logic really?

23

Yet Another Latch and Gotcha Paper

Don Mills

SV Logic redefined in 1800-2009

IEEE 1800-2005
logic and bit

variable declaration

IEEE 1800-2009
logic and bit define a value set:
4 state or 2 state

IEEE 1800-2009 logic and bit still imply

variable types
except for input and inout ports
DOES THIS MATTER?
Why do I care?
24

Yet Another Latch and Gotcha Paper

Don Mills

IEEE 1800-2009 logic gotcha - inputs

Inputs default to wire logic type
You must specify var if you want a variable type
module M (input
input
input var

a,
logic b,
c,

Currently, presto
inout
still reads by the
inout wire
1800-2005 rules:inout tri
logic by itself inout
logic
implied var logic
output
output

25

d,
e,
f,
g,

h,
logic k);

//infers wire logic

//infers wire logic
//infers var logic

Why do I care??
Variables may only have a
single source.
Variable inputs may limit
simulation optimization.
Possibly an issue for large
designs

Yet Another Latch and Gotcha Paper

Don Mills

IEEE 1800-2009 logic gotcha - inouts

Whats the difference between input and inout?
Whats the difference between wire and tri?
module M (input
input
input var
Inside the simulator, there
may be an implementation
difference between input
and inout ports which will
affect speed for large
designs.
Externally, there is not
function difference.

26

a,
logic b,
logic c,

inout
inout wire
inout tri
inout
logic
output
output

d,
e,
f,
g,

//infers wire logic

//infers wire logic

//infers
//infers
//infers
//infers

wire
wire
wire
wire

h,
logic k);

Yet Another Latch and Gotcha Paper

Don Mills

logic
logic
logic
logic

IEEE 1800-2009 logic gotcha - outputs

logic outputs default to variable logic
module M (input
input
input var

a,
logic b,
logic c,

inout
inout wire
inout tri
logic
inout
output
output

27

d,
e,
f,
g,

h, //infers wire logic

logic k); //infers var logic

Yet Another Latch and Gotcha Paper

Don Mills

Personal preferences
Option 1 (Cliff Cummings - reviewer)
Use logic everywhere
except when a signal is multi-driven, then use wire

Option 2 (Don Mills)

The VHDL coming out in me

Use logic everywhere

except when a signal is multi-driven, then use tri
(self documenting)
To be pure in intent, should now use var logic for
inputs (but probably wont)
28

Yet Another Latch and Gotcha Paper

Don Mills

Conclusion
casez, casex, case inside
Use immediate assertion with casex or case inside

unique case & priority case still allow latches

Use defaults prior to any conditional logic to prevent
latches (Use unique0 when supported)

SRFF Synopsys coding error revealed!

Add simulation fix to sensitivity list

SV logic type NOT, what is SV logic really?

Use logic everywhere / except when a signal is multidriven then use tri (or wire)
29

Yet Another Latch and Gotcha Paper

Don Mills